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Removed BUFR and BUFMR, clock division implemented on logic. 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-09-24 10:45:09 +02:00
parent 31ba200080
commit 32feed6640
1 changed files with 17 additions and 14 deletions
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31
minitests/plle2_adv/src/plle2_test.v
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@ -13,24 +13,27 @@ output wire [5:0] O_CNT
// ============================================================================
// Input clock divider (to get different clkins)
wire clk100;
wire clk50;
reg clk50;
assign clk100 = CLK;
wire clkbuf;
BUFMR mr_buf (.I(CLK), .O(clkbuf));
always @(posedge clk100)
clk50 <= !clk50;
BUFR #
(
.BUFR_DIVIDE ("2")
)
bufr
(
.I (clkbuf),
.CLR (RST),
.CE (1'b1),
.O (clk50)
);
//wire clkbuf;
//BUFMR mr_buf (.I(CLK), .O(clkbuf));
//BUFR #
//(
//.BUFR_DIVIDE ("2")
//)
//bufr
//(
//.I (clkbuf),
//.CLR (RST),
//.CE (1'b1),
//.O (clk50)
//);
// ============================================================================
// The PLL