mirror of https://github.com/openXC7/prjxray.git
Added LiteX SoC project (VexRiscV + DRAM + Ethernet for Arty board)
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
991e7866b4
commit
01f77fd2b2
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@ -0,0 +1,5 @@
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*.bin
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*.bit
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*.edif
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*.fasm
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*.log
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@ -0,0 +1,14 @@
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VIVADO = /opt/Xilinx/Vivado/2017.2/bin/vivado
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all: top.bit
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clean:
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@rm -f *.bit
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@rm -rf build
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.PHONY: all clean
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top.bit: $(VIVADO)
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mkdir -p build
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cd build && $(VIVADO) -mode batch -source ../top.tcl -nojournal -tempDir build -log vivado.log -verbose
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cp build/*.bit ./
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File diff suppressed because it is too large
Load Diff
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create_project -force -name top -part xc7a35ticsg324-1L
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add_files {../top.v}
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add_files {../VexRiscv.v}
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read_xdc {../top.xdc}
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synth_design -top top -part xc7a35ticsg324-1L
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report_timing_summary -file top_timing_synth.rpt
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report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
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report_utilization -file top_utilization_synth.rpt
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opt_design
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place_design
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report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
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report_utilization -file top_utilization_place.rpt
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report_io -file top_io.rpt
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report_control_sets -verbose -file top_control_sets.rpt
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report_clock_utilization -file top_clock_utilization.rpt
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route_design
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phys_opt_design
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report_timing_summary -no_header -no_detailed_paths
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write_checkpoint -force top_route.dcp
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report_route_status -file top_route_status.rpt
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report_drc -file top_drc.rpt
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report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
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report_power -file top_power.rpt
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
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write_bitstream -force top.bit
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write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
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quit
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File diff suppressed because one or more lines are too long
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@ -0,0 +1,297 @@
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## serial:0.tx
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set_property LOC D10 [get_ports serial_tx]
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set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
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## serial:0.rx
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set_property LOC A9 [get_ports serial_rx]
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set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
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## cpu_reset:0
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set_property LOC C2 [get_ports cpu_reset]
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set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
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## clk100:0
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set_property LOC E3 [get_ports clk100]
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set_property IOSTANDARD LVCMOS33 [get_ports clk100]
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## eth_ref_clk:0
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set_property LOC G18 [get_ports eth_ref_clk]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_ref_clk]
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## ddram:0.a
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set_property LOC R2 [get_ports ddram_a[0]]
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set_property SLEW FAST [get_ports ddram_a[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]]
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## ddram:0.a
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set_property LOC M6 [get_ports ddram_a[1]]
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set_property SLEW FAST [get_ports ddram_a[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]]
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## ddram:0.a
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set_property LOC N4 [get_ports ddram_a[2]]
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set_property SLEW FAST [get_ports ddram_a[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]]
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## ddram:0.a
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set_property LOC T1 [get_ports ddram_a[3]]
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set_property SLEW FAST [get_ports ddram_a[3]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]]
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## ddram:0.a
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set_property LOC N6 [get_ports ddram_a[4]]
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set_property SLEW FAST [get_ports ddram_a[4]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]]
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## ddram:0.a
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set_property LOC R7 [get_ports ddram_a[5]]
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set_property SLEW FAST [get_ports ddram_a[5]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]]
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## ddram:0.a
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set_property LOC V6 [get_ports ddram_a[6]]
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set_property SLEW FAST [get_ports ddram_a[6]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]]
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## ddram:0.a
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set_property LOC U7 [get_ports ddram_a[7]]
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set_property SLEW FAST [get_ports ddram_a[7]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]]
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## ddram:0.a
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set_property LOC R8 [get_ports ddram_a[8]]
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set_property SLEW FAST [get_ports ddram_a[8]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]]
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## ddram:0.a
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set_property LOC V7 [get_ports ddram_a[9]]
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set_property SLEW FAST [get_ports ddram_a[9]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]]
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## ddram:0.a
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set_property LOC R6 [get_ports ddram_a[10]]
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set_property SLEW FAST [get_ports ddram_a[10]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]]
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## ddram:0.a
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set_property LOC U6 [get_ports ddram_a[11]]
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set_property SLEW FAST [get_ports ddram_a[11]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]]
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## ddram:0.a
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set_property LOC T6 [get_ports ddram_a[12]]
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set_property SLEW FAST [get_ports ddram_a[12]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]]
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## ddram:0.a
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set_property LOC T8 [get_ports ddram_a[13]]
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set_property SLEW FAST [get_ports ddram_a[13]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]]
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## ddram:0.ba
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set_property LOC R1 [get_ports ddram_ba[0]]
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set_property SLEW FAST [get_ports ddram_ba[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]]
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## ddram:0.ba
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set_property LOC P4 [get_ports ddram_ba[1]]
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set_property SLEW FAST [get_ports ddram_ba[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]]
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## ddram:0.ba
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set_property LOC P2 [get_ports ddram_ba[2]]
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set_property SLEW FAST [get_ports ddram_ba[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]]
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## ddram:0.ras_n
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set_property LOC P3 [get_ports ddram_ras_n]
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set_property SLEW FAST [get_ports ddram_ras_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n]
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## ddram:0.cas_n
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set_property LOC M4 [get_ports ddram_cas_n]
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set_property SLEW FAST [get_ports ddram_cas_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n]
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## ddram:0.we_n
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set_property LOC P5 [get_ports ddram_we_n]
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set_property SLEW FAST [get_ports ddram_we_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_we_n]
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## ddram:0.cs_n
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set_property LOC U8 [get_ports ddram_cs_n]
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set_property SLEW FAST [get_ports ddram_cs_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n]
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## ddram:0.dm
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set_property LOC L1 [get_ports ddram_dm[0]]
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set_property SLEW FAST [get_ports ddram_dm[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]]
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## ddram:0.dm
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set_property LOC U1 [get_ports ddram_dm[1]]
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set_property SLEW FAST [get_ports ddram_dm[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]]
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## ddram:0.dq
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set_property LOC K5 [get_ports ddram_dq[0]]
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set_property SLEW FAST [get_ports ddram_dq[0]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]]
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## ddram:0.dq
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set_property LOC L3 [get_ports ddram_dq[1]]
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set_property SLEW FAST [get_ports ddram_dq[1]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]]
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## ddram:0.dq
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set_property LOC K3 [get_ports ddram_dq[2]]
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set_property SLEW FAST [get_ports ddram_dq[2]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]]
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## ddram:0.dq
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set_property LOC L6 [get_ports ddram_dq[3]]
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set_property SLEW FAST [get_ports ddram_dq[3]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]]
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## ddram:0.dq
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set_property LOC M3 [get_ports ddram_dq[4]]
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set_property SLEW FAST [get_ports ddram_dq[4]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]]
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## ddram:0.dq
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set_property LOC M1 [get_ports ddram_dq[5]]
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set_property SLEW FAST [get_ports ddram_dq[5]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]]
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## ddram:0.dq
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set_property LOC L4 [get_ports ddram_dq[6]]
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set_property SLEW FAST [get_ports ddram_dq[6]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]]
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## ddram:0.dq
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set_property LOC M2 [get_ports ddram_dq[7]]
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set_property SLEW FAST [get_ports ddram_dq[7]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]]
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## ddram:0.dq
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set_property LOC V4 [get_ports ddram_dq[8]]
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set_property SLEW FAST [get_ports ddram_dq[8]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]]
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## ddram:0.dq
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set_property LOC T5 [get_ports ddram_dq[9]]
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set_property SLEW FAST [get_ports ddram_dq[9]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]]
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## ddram:0.dq
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set_property LOC U4 [get_ports ddram_dq[10]]
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set_property SLEW FAST [get_ports ddram_dq[10]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]]
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## ddram:0.dq
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set_property LOC V5 [get_ports ddram_dq[11]]
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set_property SLEW FAST [get_ports ddram_dq[11]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]]
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## ddram:0.dq
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set_property LOC V1 [get_ports ddram_dq[12]]
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set_property SLEW FAST [get_ports ddram_dq[12]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]]
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## ddram:0.dq
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set_property LOC T3 [get_ports ddram_dq[13]]
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set_property SLEW FAST [get_ports ddram_dq[13]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]]
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## ddram:0.dq
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set_property LOC U3 [get_ports ddram_dq[14]]
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set_property SLEW FAST [get_ports ddram_dq[14]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]]
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## ddram:0.dq
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set_property LOC R3 [get_ports ddram_dq[15]]
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set_property SLEW FAST [get_ports ddram_dq[15]]
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set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]]
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set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]]
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## ddram:0.dqs_p
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set_property LOC N2 [get_ports ddram_dqs_p[0]]
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set_property SLEW FAST [get_ports ddram_dqs_p[0]]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]]
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## ddram:0.dqs_p
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set_property LOC U2 [get_ports ddram_dqs_p[1]]
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set_property SLEW FAST [get_ports ddram_dqs_p[1]]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]]
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## ddram:0.dqs_n
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set_property LOC N1 [get_ports ddram_dqs_n[0]]
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set_property SLEW FAST [get_ports ddram_dqs_n[0]]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]]
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## ddram:0.dqs_n
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set_property LOC V2 [get_ports ddram_dqs_n[1]]
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set_property SLEW FAST [get_ports ddram_dqs_n[1]]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]]
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## ddram:0.clk_p
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set_property LOC U9 [get_ports ddram_clk_p]
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set_property SLEW FAST [get_ports ddram_clk_p]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p]
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## ddram:0.clk_n
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set_property LOC V9 [get_ports ddram_clk_n]
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set_property SLEW FAST [get_ports ddram_clk_n]
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set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n]
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## ddram:0.cke
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set_property LOC N5 [get_ports ddram_cke]
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set_property SLEW FAST [get_ports ddram_cke]
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set_property IOSTANDARD SSTL135 [get_ports ddram_cke]
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## ddram:0.odt
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set_property LOC R5 [get_ports ddram_odt]
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set_property SLEW FAST [get_ports ddram_odt]
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set_property IOSTANDARD SSTL135 [get_ports ddram_odt]
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## ddram:0.reset_n
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set_property LOC K6 [get_ports ddram_reset_n]
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set_property SLEW FAST [get_ports ddram_reset_n]
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set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n]
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## eth_clocks:0.tx
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set_property LOC H16 [get_ports eth_clocks_tx]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_clocks_tx]
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## eth_clocks:0.rx
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set_property LOC F15 [get_ports eth_clocks_rx]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_clocks_rx]
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## eth:0.rst_n
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set_property LOC C16 [get_ports eth_rst_n]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_rst_n]
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## eth:0.mdio
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set_property LOC K13 [get_ports eth_mdio]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_mdio]
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## eth:0.mdc
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set_property LOC F16 [get_ports eth_mdc]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_mdc]
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## eth:0.rx_dv
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set_property LOC G16 [get_ports eth_rx_dv]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_dv]
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## eth:0.rx_er
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set_property LOC C17 [get_ports eth_rx_er]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_er]
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## eth:0.rx_data
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set_property LOC D18 [get_ports eth_rx_data[0]]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[0]]
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## eth:0.rx_data
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set_property LOC E17 [get_ports eth_rx_data[1]]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[1]]
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## eth:0.rx_data
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set_property LOC E18 [get_ports eth_rx_data[2]]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[2]]
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## eth:0.rx_data
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set_property LOC G17 [get_ports eth_rx_data[3]]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[3]]
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## eth:0.tx_en
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set_property LOC H15 [get_ports eth_tx_en]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_en]
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## eth:0.tx_data
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set_property LOC H14 [get_ports eth_tx_data[0]]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[0]]
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## eth:0.tx_data
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set_property LOC J14 [get_ports eth_tx_data[1]]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[1]]
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## eth:0.tx_data
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set_property LOC J13 [get_ports eth_tx_data[2]]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[2]]
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## eth:0.tx_data
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set_property LOC H17 [get_ports eth_tx_data[3]]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[3]]
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## eth:0.col
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set_property LOC D17 [get_ports eth_col]
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set_property IOSTANDARD LVCMOS33 [get_ports eth_col]
|
||||
## eth:0.crs
|
||||
set_property LOC G14 [get_ports eth_crs]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_crs]
|
||||
|
||||
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
|
||||
|
||||
create_clock -name clk100 -period 10.0 [get_nets clk100]
|
||||
|
||||
create_clock -name eth_rx_clk -period 80.0 [get_nets eth_rx_clk]
|
||||
|
||||
create_clock -name eth_tx_clk -period 80.0 [get_nets eth_tx_clk]
|
||||
|
||||
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -asynchronous
|
||||
|
||||
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
|
||||
|
||||
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
|
||||
|
||||
set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
|
||||
|
||||
set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
|
||||
|
||||
set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
VIVADO = /opt/Xilinx/Vivado/2017.2/bin/vivado
|
||||
|
||||
all: top.bit
|
||||
|
||||
clean:
|
||||
@rm -f *.edif
|
||||
@rm -f *.bit
|
||||
@rm -f *.log
|
||||
@rm -rf build
|
||||
|
||||
.PHONY: all clean
|
||||
|
||||
top.edif: $(YOSYS)
|
||||
$(YOSYS) -s synth.ys -l yosys.log
|
||||
|
||||
top.bit: $(VIVADO) top.edif
|
||||
mkdir -p build
|
||||
cd build && $(VIVADO) -mode batch -source ../top.tcl -nojournal -tempDir build -log vivado.log -verbose
|
||||
cp build/*.bit ./
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,3 @@
|
|||
read_verilog top.v
|
||||
read_verilog VexRiscv.v
|
||||
synth_xilinx -edif top.edif
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
create_project -force -name top -part xc7a35ticsg324-1L
|
||||
read_xdc ../top.xdc
|
||||
read_edif ../top.edif
|
||||
link_design -top top -part xc7a35ticsg324-1L
|
||||
report_timing_summary -file top_timing_synth.rpt
|
||||
report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt
|
||||
report_utilization -file top_utilization_synth.rpt
|
||||
opt_design
|
||||
place_design
|
||||
report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt
|
||||
report_utilization -file top_utilization_place.rpt
|
||||
report_io -file top_io.rpt
|
||||
report_control_sets -verbose -file top_control_sets.rpt
|
||||
report_clock_utilization -file top_clock_utilization.rpt
|
||||
route_design
|
||||
phys_opt_design
|
||||
report_timing_summary -no_header -no_detailed_paths
|
||||
write_checkpoint -force top_route.dcp
|
||||
report_route_status -file top_route_status.rpt
|
||||
report_drc -file top_drc.rpt
|
||||
report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
|
||||
report_power -file top_power.rpt
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
write_bitstream -force top.bit
|
||||
write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
|
||||
quit
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,297 @@
|
|||
## serial:0.tx
|
||||
set_property LOC D10 [get_ports serial_tx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports serial_tx]
|
||||
## serial:0.rx
|
||||
set_property LOC A9 [get_ports serial_rx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports serial_rx]
|
||||
## cpu_reset:0
|
||||
set_property LOC C2 [get_ports cpu_reset]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset]
|
||||
## clk100:0
|
||||
set_property LOC E3 [get_ports clk100]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports clk100]
|
||||
## eth_ref_clk:0
|
||||
set_property LOC G18 [get_ports eth_ref_clk]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_ref_clk]
|
||||
## ddram:0.a
|
||||
set_property LOC R2 [get_ports ddram_a[0]]
|
||||
set_property SLEW FAST [get_ports ddram_a[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]]
|
||||
## ddram:0.a
|
||||
set_property LOC M6 [get_ports ddram_a[1]]
|
||||
set_property SLEW FAST [get_ports ddram_a[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]]
|
||||
## ddram:0.a
|
||||
set_property LOC N4 [get_ports ddram_a[2]]
|
||||
set_property SLEW FAST [get_ports ddram_a[2]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]]
|
||||
## ddram:0.a
|
||||
set_property LOC T1 [get_ports ddram_a[3]]
|
||||
set_property SLEW FAST [get_ports ddram_a[3]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]]
|
||||
## ddram:0.a
|
||||
set_property LOC N6 [get_ports ddram_a[4]]
|
||||
set_property SLEW FAST [get_ports ddram_a[4]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]]
|
||||
## ddram:0.a
|
||||
set_property LOC R7 [get_ports ddram_a[5]]
|
||||
set_property SLEW FAST [get_ports ddram_a[5]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]]
|
||||
## ddram:0.a
|
||||
set_property LOC V6 [get_ports ddram_a[6]]
|
||||
set_property SLEW FAST [get_ports ddram_a[6]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]]
|
||||
## ddram:0.a
|
||||
set_property LOC U7 [get_ports ddram_a[7]]
|
||||
set_property SLEW FAST [get_ports ddram_a[7]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]]
|
||||
## ddram:0.a
|
||||
set_property LOC R8 [get_ports ddram_a[8]]
|
||||
set_property SLEW FAST [get_ports ddram_a[8]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]]
|
||||
## ddram:0.a
|
||||
set_property LOC V7 [get_ports ddram_a[9]]
|
||||
set_property SLEW FAST [get_ports ddram_a[9]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]]
|
||||
## ddram:0.a
|
||||
set_property LOC R6 [get_ports ddram_a[10]]
|
||||
set_property SLEW FAST [get_ports ddram_a[10]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]]
|
||||
## ddram:0.a
|
||||
set_property LOC U6 [get_ports ddram_a[11]]
|
||||
set_property SLEW FAST [get_ports ddram_a[11]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]]
|
||||
## ddram:0.a
|
||||
set_property LOC T6 [get_ports ddram_a[12]]
|
||||
set_property SLEW FAST [get_ports ddram_a[12]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]]
|
||||
## ddram:0.a
|
||||
set_property LOC T8 [get_ports ddram_a[13]]
|
||||
set_property SLEW FAST [get_ports ddram_a[13]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]]
|
||||
## ddram:0.ba
|
||||
set_property LOC R1 [get_ports ddram_ba[0]]
|
||||
set_property SLEW FAST [get_ports ddram_ba[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]]
|
||||
## ddram:0.ba
|
||||
set_property LOC P4 [get_ports ddram_ba[1]]
|
||||
set_property SLEW FAST [get_ports ddram_ba[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]]
|
||||
## ddram:0.ba
|
||||
set_property LOC P2 [get_ports ddram_ba[2]]
|
||||
set_property SLEW FAST [get_ports ddram_ba[2]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]]
|
||||
## ddram:0.ras_n
|
||||
set_property LOC P3 [get_ports ddram_ras_n]
|
||||
set_property SLEW FAST [get_ports ddram_ras_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n]
|
||||
## ddram:0.cas_n
|
||||
set_property LOC M4 [get_ports ddram_cas_n]
|
||||
set_property SLEW FAST [get_ports ddram_cas_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n]
|
||||
## ddram:0.we_n
|
||||
set_property LOC P5 [get_ports ddram_we_n]
|
||||
set_property SLEW FAST [get_ports ddram_we_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_we_n]
|
||||
## ddram:0.cs_n
|
||||
set_property LOC U8 [get_ports ddram_cs_n]
|
||||
set_property SLEW FAST [get_ports ddram_cs_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n]
|
||||
## ddram:0.dm
|
||||
set_property LOC L1 [get_ports ddram_dm[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dm[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]]
|
||||
## ddram:0.dm
|
||||
set_property LOC U1 [get_ports ddram_dm[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dm[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]]
|
||||
## ddram:0.dq
|
||||
set_property LOC K5 [get_ports ddram_dq[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[0]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]]
|
||||
## ddram:0.dq
|
||||
set_property LOC L3 [get_ports ddram_dq[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[1]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]]
|
||||
## ddram:0.dq
|
||||
set_property LOC K3 [get_ports ddram_dq[2]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[2]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]]
|
||||
## ddram:0.dq
|
||||
set_property LOC L6 [get_ports ddram_dq[3]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[3]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]]
|
||||
## ddram:0.dq
|
||||
set_property LOC M3 [get_ports ddram_dq[4]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[4]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]]
|
||||
## ddram:0.dq
|
||||
set_property LOC M1 [get_ports ddram_dq[5]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[5]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]]
|
||||
## ddram:0.dq
|
||||
set_property LOC L4 [get_ports ddram_dq[6]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[6]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]]
|
||||
## ddram:0.dq
|
||||
set_property LOC M2 [get_ports ddram_dq[7]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[7]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]]
|
||||
## ddram:0.dq
|
||||
set_property LOC V4 [get_ports ddram_dq[8]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[8]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]]
|
||||
## ddram:0.dq
|
||||
set_property LOC T5 [get_ports ddram_dq[9]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[9]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]]
|
||||
## ddram:0.dq
|
||||
set_property LOC U4 [get_ports ddram_dq[10]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[10]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]]
|
||||
## ddram:0.dq
|
||||
set_property LOC V5 [get_ports ddram_dq[11]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[11]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]]
|
||||
## ddram:0.dq
|
||||
set_property LOC V1 [get_ports ddram_dq[12]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[12]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]]
|
||||
## ddram:0.dq
|
||||
set_property LOC T3 [get_ports ddram_dq[13]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[13]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]]
|
||||
## ddram:0.dq
|
||||
set_property LOC U3 [get_ports ddram_dq[14]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[14]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]]
|
||||
## ddram:0.dq
|
||||
set_property LOC R3 [get_ports ddram_dq[15]]
|
||||
set_property SLEW FAST [get_ports ddram_dq[15]]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]]
|
||||
set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]]
|
||||
## ddram:0.dqs_p
|
||||
set_property LOC N2 [get_ports ddram_dqs_p[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_p[0]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]]
|
||||
## ddram:0.dqs_p
|
||||
set_property LOC U2 [get_ports ddram_dqs_p[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_p[1]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]]
|
||||
## ddram:0.dqs_n
|
||||
set_property LOC N1 [get_ports ddram_dqs_n[0]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_n[0]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]]
|
||||
## ddram:0.dqs_n
|
||||
set_property LOC V2 [get_ports ddram_dqs_n[1]]
|
||||
set_property SLEW FAST [get_ports ddram_dqs_n[1]]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]]
|
||||
## ddram:0.clk_p
|
||||
set_property LOC U9 [get_ports ddram_clk_p]
|
||||
set_property SLEW FAST [get_ports ddram_clk_p]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p]
|
||||
## ddram:0.clk_n
|
||||
set_property LOC V9 [get_ports ddram_clk_n]
|
||||
set_property SLEW FAST [get_ports ddram_clk_n]
|
||||
set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n]
|
||||
## ddram:0.cke
|
||||
set_property LOC N5 [get_ports ddram_cke]
|
||||
set_property SLEW FAST [get_ports ddram_cke]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_cke]
|
||||
## ddram:0.odt
|
||||
set_property LOC R5 [get_ports ddram_odt]
|
||||
set_property SLEW FAST [get_ports ddram_odt]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_odt]
|
||||
## ddram:0.reset_n
|
||||
set_property LOC K6 [get_ports ddram_reset_n]
|
||||
set_property SLEW FAST [get_ports ddram_reset_n]
|
||||
set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n]
|
||||
## eth_clocks:0.tx
|
||||
set_property LOC H16 [get_ports eth_clocks_tx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_clocks_tx]
|
||||
## eth_clocks:0.rx
|
||||
set_property LOC F15 [get_ports eth_clocks_rx]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_clocks_rx]
|
||||
## eth:0.rst_n
|
||||
set_property LOC C16 [get_ports eth_rst_n]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_rst_n]
|
||||
## eth:0.mdio
|
||||
set_property LOC K13 [get_ports eth_mdio]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_mdio]
|
||||
## eth:0.mdc
|
||||
set_property LOC F16 [get_ports eth_mdc]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_mdc]
|
||||
## eth:0.rx_dv
|
||||
set_property LOC G16 [get_ports eth_rx_dv]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_dv]
|
||||
## eth:0.rx_er
|
||||
set_property LOC C17 [get_ports eth_rx_er]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_er]
|
||||
## eth:0.rx_data
|
||||
set_property LOC D18 [get_ports eth_rx_data[0]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[0]]
|
||||
## eth:0.rx_data
|
||||
set_property LOC E17 [get_ports eth_rx_data[1]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[1]]
|
||||
## eth:0.rx_data
|
||||
set_property LOC E18 [get_ports eth_rx_data[2]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[2]]
|
||||
## eth:0.rx_data
|
||||
set_property LOC G17 [get_ports eth_rx_data[3]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_rx_data[3]]
|
||||
## eth:0.tx_en
|
||||
set_property LOC H15 [get_ports eth_tx_en]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_en]
|
||||
## eth:0.tx_data
|
||||
set_property LOC H14 [get_ports eth_tx_data[0]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[0]]
|
||||
## eth:0.tx_data
|
||||
set_property LOC J14 [get_ports eth_tx_data[1]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[1]]
|
||||
## eth:0.tx_data
|
||||
set_property LOC J13 [get_ports eth_tx_data[2]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[2]]
|
||||
## eth:0.tx_data
|
||||
set_property LOC H17 [get_ports eth_tx_data[3]]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_tx_data[3]]
|
||||
## eth:0.col
|
||||
set_property LOC D17 [get_ports eth_col]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_col]
|
||||
## eth:0.crs
|
||||
set_property LOC G14 [get_ports eth_crs]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports eth_crs]
|
||||
|
||||
set_property INTERNAL_VREF 0.675 [get_iobanks 34]
|
||||
|
||||
create_clock -name clk100 -period 10.0 [get_nets clk100]
|
||||
|
||||
create_clock -name eth_rx_clk -period 80.0 [get_nets eth_rx_clk]
|
||||
|
||||
create_clock -name eth_tx_clk -period 80.0 [get_nets eth_tx_clk]
|
||||
|
||||
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -asynchronous
|
||||
|
||||
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets sys_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
|
||||
|
||||
set_clock_groups -group [get_clocks -include_generated_clocks -of [get_nets eth_rx_clk]] -group [get_clocks -include_generated_clocks -of [get_nets eth_tx_clk]] -asynchronous
|
||||
|
||||
set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}]
|
||||
|
||||
set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
|
||||
|
||||
set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]]
|
||||
Loading…
Reference in New Issue