roi_harness: added zybo support

Fixed also basys3 settings to produce a correct harness for the basys

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

minitests/roi_harness/arty.sh

@@ -11,4 +11,7 @@ export XRAY_PIN_04="D13"
 export XRAY_PIN_05="J17"
 export XRAY_PIN_06="U14"
 
+# HCLK Tile
+export XRAY_ROI_HCLK="CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0"
+
 source $XRAY_DIR/utils/environment.sh

minitests/roi_harness/basys3.sh

@@ -1,6 +1,8 @@
 # XC7A35T-1CPG236C
 export XRAY_PART=xc7a35tcpg236-1
 export XRAY_PINCFG=BASYS3-SWBUT
+export XRAY_DIN_N_LARGE=17
+export XRAY_DOUT_N_LARGE=17
 
 # For generating DB
 export XRAY_PIN_00="V17"
@@ -11,4 +13,10 @@ export XRAY_PIN_04="W15"
 export XRAY_PIN_05="V15"
 export XRAY_PIN_06="W14"
 
+# ROI is in the top left
+export XRAY_ROI_LARGE=SLICE_X0Y100:SLICE_X35Y149
+
+# HCLK Tile
+export XRAY_ROI_HCLK="CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0"
+
 source $XRAY_DIR/utils/environment.sh

minitests/roi_harness/runme.sh

@@ -26,19 +26,23 @@ stat ${XRAY_DIR}/database/${XRAY_DATABASE}/${XRAY_PART}.yaml >/dev/null
 # 6x by 18y CLBs (108)
 if [ "$SMALL" = Y ] ; then
     echo "Design: small"
-    export PITCH=1
+    export PITCH=${XRAY_PITCH:-1}
     export DIN_N=${XRAY_DIN_N_SMALL:-8}
     export DOUT_N=${XRAY_DOUT_N_SMALL:-8}
     export XRAY_ROI=${XRAY_ROI_SMALL:-SLICE_X12Y100:SLICE_X17Y117}
 # All of CMT X0Y2
 else
     echo "Design: large"
-    export PITCH=2
+    export PITCH=${XRAY_PITCH:-2}
     export DIN_N=${XRAY_DIN_N_LARGE:-8}
     export DOUT_N=${XRAY_DOUT_N_LARGE:-8}
     export XRAY_ROI=${XRAY_ROI_LARGE:-SLICE_X0Y100:SLICE_X35Y149}
 fi
 
+echo ${DIN_N}
+echo ${DOUT_N}
+echo ${XRAY_ROI}
+
 mkdir -p $BUILD_DIR
 pushd $BUILD_DIR
 

minitests/roi_harness/runme.tcl

@@ -18,6 +18,12 @@ if { [info exists ::env(PITCH) ] } {
     set PITCH "$::env(PITCH)"
 }
 
+if { [info exists ::env(XRAY_ROI_HCLK)] } {
+    set XRAY_ROI_HCLK "$::env(XRAY_ROI_HCLK)"
+} else {
+    puts "WARNING: No HCLK has been set"
+}
+
 # X12 in the ROI, X10 just to the left
 # Start at bottom left of ROI and work up
 # (IOs are to left)
@@ -423,7 +429,7 @@ if {$fixed_xdc eq ""} {
     # It will go to high level interconnect that goes everywhere
     # But we still need to record something, so lets force a route
     # FIXME: very ROI specific
-    set node "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0"
+    set node "$XRAY_ROI_HCLK"
     set wire [node2wire $node]
     route_via2 "clk_IBUF_BUFG" "$node"
     set net "clk"
@@ -441,7 +447,11 @@ if {$fixed_xdc eq ""} {
             route_via2 "din_IBUF[$i]" "$node"
             set y_left [expr {$y_left + $PITCH}]
         } else {
-            set node "INT_R_X25Y${y_right}/WW2BEG1"
+            if {$part eq "xc7z010clg400-1"} {
+                set node "INT_R_X31Y${y_right}/WW2BEG2"
+            } else {
+                set node "INT_R_X25Y${y_right}/WW2BEG1"
+            }
             route_via2 "din_IBUF[$i]" "$node"
             set y_right [expr {$y_right + $PITCH}]
         }
@@ -478,8 +488,13 @@ if {$fixed_xdc eq ""} {
             set y_left [expr {$y_left + $PITCH}]
             # XXX: only care about right ports on Arty
         } else {
-            set node "INT_R_X23Y${y_right}/LH12"
-            route_via2 "roi/dout[$i]" "$node"
+            if {$part eq "xc7z010clg400-1"} {
+                set node "INT_R_X29Y${y_right}/EE2BEG0"
+                route_via2 "roi/dout[$i]" "$node INT_R_X31Y${y_right}"
+            } else {
+                set node "INT_R_X23Y${y_right}/LH12"
+                route_via2 "roi/dout[$i]" "$node"
+            }
             set y_right [expr {$y_right + $PITCH}]
         }
         set net "dout[$i]"

minitests/roi_harness/zybo.sh

@@ -16,4 +16,10 @@ export XRAY_PIN_06="K19"
 # ROI is in top right
 export XRAY_ROI_LARGE="SLICE_X22Y50:SLICE_X43Y99"
 
+# HCLK Tile
+export XRAY_ROI_HCLK="CLK_HROW_TOP_R_X82Y78/CLK_HROW_CK_BUFHCLK_R0"
+
+# PITCH
+export XRAY_PITCH=3
+
 source $XRAY_DIR/utils/environment.sh