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Author SHA1 Message Date
Stephen Williams 94818c19a0 Update to 20080314 snapshot 2008-03-14 15:58:51 -07:00
Cary R ef9ee52e53 NetESignal::dup_expr() was not passing the word_ information.
The dup_expr() function for NetESignal was not copying the word_
expression. This would cause an individual array access to turn
into an entire array access. The file and line information was
also not being set correctly.

An assert() in tgt-vvp/eval_expr.c was also replaced with an
exit() since the appropriate information was already being
printed.
2008-03-12 20:55:12 -07:00
Cary R 377f5eaa23 Add \' as a string constant to block macro expansion.
This patch allows you to type "The \`define is `value" and not have
Icarus try to expand `define as a macro.
2008-03-11 20:14:32 -07:00
Cary R 234648231b Add bit/part select release for constants and add an error check.
This patch adds functionality to do a bit or part select release
when a constant value is forced to the net/register. It also adds an
error message when the user tries to force a signal to a bit/part
select. This is not currently handled by the run time, so is now
caught in the compiler (tgt-vvp). Where when this functionality is
needed, it will be easy to know what to do instead of trying to track
down some odd runtime functionality.

What this all means is that you can force a signal to an entire
signal or you can force a constant to any part of a signal (bit,
part or entire) and release any of the above. Technically the
release of a constant value does not have to match the force.
The runtime verifies that if you are releasing a signal driver
it is being done as a full release. I don't see an easy way to
check this in the compiler.

To fix the signal deficiencies we need to rework the force_link
code to allow multiple drivers and partial unlinking. Much of
this is in the runtime, but the %force/link operator may also
need to be changed like I did to the %release opcode.
2008-03-11 19:56:58 -07:00
Cary R cc28a9a734 Improve error message in tgt-vvp/eval_expr.c:draw_eval_expr_wid().
The IVL_EX_NONE type was not displaying any message and default did not
use the new ivl_expr_{file,lineno} functions to get the source location.
This patch remedies these problems.
2008-03-11 19:47:22 -07:00
Stephen Williams 6f1445ff9d Minor cleanup of vpi_put_value to wire
Comments to clarify the vpiForceFlag and vpiReleaseFlag behaviors.
2008-03-10 22:18:41 -07:00
Stephen Williams e0fbc15bd4 Support vpiForceFlag and vpiReleaseFlag for nets.
vpi_put_value can mimic force and release with vpiForceFlag and
vpiReleaseFlag flags to the vpi_put_value call. With this patch,
the infrastructure is added to allow the flags argument to be passed
to the dispatched put_value function, and for signals handle those
flags as force/release of a net.
2008-03-10 21:54:58 -07:00
Stephen Williams e141d2bb37 Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2008-03-10 19:24:40 -07:00
Cary R fe72d02cf6 Major rework of the ternary operator elaboration code.
This patch reworks much of the ternary code to short circuit when
possible and supports real values better. It adds a blend operator
for real values that returns 0.0 when the values differ and the value
when they match. This deviates slightly from the standard which
specifies that the value for reals is always 0.0 when the conditional
is 'bx. There are also a couple bug fixes.

These fixes have not been ported to continuous assignments yet.
Ternary operators used at compile time and in procedural assignments
should be complete (short circuit and support real values).
2008-03-08 19:45:13 -08:00
Cary R c2bae1ad6c Fix a small bug in the extra digits warning.
There were a couple places where a normal decimal number was
accidentally setting the base for an unsized number. This is
only a warning problem.
2008-03-06 20:42:07 -08:00
Stephen Williams 692caca9dc Connect module instance arrays MSB to MSB.
When a bit port of a module instance is connected to a vector
argument, the MSB module instance should be connected to the MSB
of the vector argument. This matters only in the rare case that
the %m is used. It also makes wave dumps come out right.
2008-03-06 20:37:08 -08:00
Michael Witten 8b45797ccf ivlpp: Fixed handling of absolute paths
The updates to the do_include code destroyed the
handling of absolute paths; all of the code that
handles buffer-switching was erroneously placed
in just the relative-path branch. Thanks go to
Cary R. for pointing out the problem.

Now the common code has been extracted yet again,
and the notorious goto statement has been used
in favor redundancy.

The test vvp_reg.pl produces the same output as
before, so hopefully nothing new is broken.

Signed-off-by: Michael Witten <[email protected]>
2008-03-05 08:42:57 -08:00
Stephen Williams 8d3febff2b Keep processes in proper lexical scope
Normally processes are found in the lexical scope of a module, but
there are special cases where processes (other then task/function
definitions) are in other lexical scopes. The most likely case is
initilizations that are in the lexical scope where the assigned
variable is declared.

In the process, the behaviors list is kept in the base PScope class
instead of the Module or any other derived lexical scope class.
2008-03-03 20:49:52 -08:00
Cary R 3221f70bcb Add vvp_fun_part_var::recv_vec4_pv().
Add missing vvp_fun_part_var::recv_vec4_pv() function. This is mostly
a duplicate of the _pv() routine from vvp_fun_part.
2008-03-02 21:20:56 -08:00
Stephen Williams cb920bd864 Merge branch 'master' of [email protected]:git/verilog 2008-03-02 21:04:46 -08:00
Stephen Williams 32a2e7aa39 Fix lexical scopes within case-generate alternatives.
Case-generate alternatives create sub-scopes that need to be scanned
by the scope scanner in order to get function definitions etc. that
are defined lexically within generated scopes.
2008-03-02 21:04:04 -08:00
Stephen Williams 52ac96ca15 elaborate_sig for generated case items
Handle elaborate_sig for scopes that are within a case-generated
scheme.
2008-02-27 20:54:47 -08:00
Cary R f8caebd076 Convert real array index to integer.
This patch converts a constant real index to an integer value when
defining an array. This can happen when using 2**8 which returns a
real value since the operands are signed.
2008-02-27 18:00:21 -08:00
Cary R 70c5c9fe14 Propagate file and line information in more places.
There where a few places that were not propagating the file and
line information.
2008-02-27 17:31:20 -08:00
Stephen Williams 75df8fb6bb Remove index register restrictions on ix/arith instructions.
The %ix/<arith> instructions are currently not in use, but even so
it is just plain wrong to restrict their register argument to 0-3.
2008-02-27 17:01:53 -08:00
Cary R ec87c7f6de Fix %ix/load to work with all index registers.
draw_number_bool64() in tgt-vvp/eval_bool.c was using %ix/load to
load immediate values into registers greater than three. The problem
was that of_IX_LOAD() in vvp/vthread.cc was masking off the upper
bits. This was putting the results in the wrong register. This patch
removes the bit masking from of_IX_LOAD() and updates the %ix/load
documentation.
2008-02-27 16:54:38 -08:00
Cary R b5ef6d7a37 Fix some problems in driver-vpi/main.c
Fixed a few problems in driver-vpi/main.c that were preventing
the Verilog-A math library from compiling.
2008-02-25 16:01:59 -08:00
Cary R 285ff2859f Add power operator synthesize().
This patch adds synthesize() for the power operator.
2008-02-25 15:57:56 -08:00
Michael Witten a01bc5e245 ivlpp: Cleanup: Formatting/Detabification
The file lexor.lex was beginning to suffer a catastrophic
increase in entropy due mainly to the mingling of spaces
and tabs--an age-old problem that often finds itself as
the subject of many a religious war.

The key rule: Make it consistent in as many editors as
possible; this was achieved by converting all hard tabs
into soft tabs (composed of spaces) of width 4.

I couldn't help but make modifications to the code as I
tabifified, but most of the changes are strictly style.

While maintainers generally treat large scale whitespace and
formatting changes with much caution, I believe that the code
is now much more maintainable; moreover, the test suite
produces the same results as before.

Signed-off-by: Michael Witten <[email protected]>
2008-02-25 15:52:41 -08:00
Michael Witten c6ce3f6f38 ivlpp: Error checking for macro names
Macro names cannot be compiler directive names.
Such trespasses are now recognized and reported:

    (1) Offending `define lines are skipped.

    (2) Offending macros meant to be expanded
        are replaced with nothing.

Signed-off-by: Michael Witten <[email protected]>
2008-02-25 15:51:34 -08:00
Cary R fac1cc5a1c Add user function synth and clean up expression code.
This patch adds synthesize() for user functions. It also cleans up a
number of inconsistencies and missing checks in the expression code.
2008-02-24 20:00:18 -08:00
Stephen Williams 11a33a0907 Merge branch 'pscope' 2008-02-24 19:45:21 -08:00
Stephen Williams 8e704cbf93 Rework handling of lexical scope
Move the storage of wires (signals) out of the Module class into
the PScope base class, and instead of putting the PWires all into
the Module object, distribute them into the various lexical scopes
(derived from PScope) so that the wire names do not need to carry
scope information.

This required some rewiring of elaboration of signals, and rewriting
of lexical scope handling.
2008-02-24 19:40:54 -08:00
Cary R 3716e972ec Add support for unary +/- in real parameter evaluation.
This patch adds support for unary + and - of real value constants
to the eval_tree() functionality.
2008-02-20 17:24:44 -08:00
Cary R 538d3d1f4d Print an error message if $fscanf() is called with a NULL fd.
If $fscanf() is called with a NULL file descriptor an appropriate
error message is printed and the program exits.
2008-02-20 17:16:52 -08:00
Cary R 528af27769 Fix a realloc size error and initialize enable_ in the dff.
The buffer reallocation in scan_format_string() was one character
too small. The enable_ pin to the dff primitive was not given an
initial value.
2008-02-19 10:06:44 -08:00
Michael Witten 2bd13964cd ivlpp: Slight rearrangement of do_include()
The ordering of the logic was a little strange before.
Also, there were unnecessary operations, like the assert
and the include_dir[0]=0 business.

Signed-off-by: Michael Witten <[email protected]>
2008-02-19 09:56:18 -08:00
Michael Witten 105885402f ivlpp: Fixed include_path inconsistency
Discussions online and "standards" documents are never
conclusive, but the code that was present suggests that
iverilog adopts the sane practice of resolving relative
paths against the directory of the file that is currently
being processed.

Unfortunately, when a relative path is made absolute, the
code forgot to update the necessary include_stack_t object.

This has now been fixed.

Signed-off-by: Michael Witten <[email protected]>
2008-02-19 09:56:18 -08:00
Michael Witten b512671643 ivlpp: Removed yywrap() to handle EOF more sanely
When the lexical analyzer encounters and EOF, the
analyzer invokes yywrap() to determine what to do
next. The function determines one of two paths of
execution:

	(1)	If yywrap() returns 0, then the analyzer
		assumes that yywrap() has setup a new input
		source, and so scanning continues.

	(2)	If yywrap() returns non-zero, then the analyzer
		assumes that yywrap() has not setup a new input
		source, and so the analyzer proceeds to run the
		matching EOF action (the default of which invokes
		yyterminate()).

	NOTE:	The analyzer does not touch the start condition.

The old implementation was using yywrap() to destroy the current
input source and setup the next one. However, this causes problems
when the analyzer is in the middle of parsing some directive:

	(1)	Because yywrap() is called before any EOF action,
		the include_stack_t structure is destroyed before
		being used in the EOF action; the result is a segfault.

	(2)	Because yywrap() does not change the start condition,
		any EOF action would occur completely out of context;
		however, because of (1), this problem never cropped
		up.

The new implementation simply:

	(1)	Employs "%option noyywrap", which effectively causes
		the analyzer to act as though yywrap() produces a non-zero.

	(2)	Renames yywrap "load_next_input".

	(3)	Calls load_next_input() explicitly in exhaustive EOF actions,
		so that control is more fine grained.

The added benefit is that the code that finishes parsing EOF terminated
directives now works properly; `include and `define directives previously
segfaulted in such situations.

Signed-off-by: Michael Witten <[email protected]>
2008-02-19 09:56:18 -08:00
Michael Witten c064451e15 ivlpp: Formatting/Simplification
Code is now shared among rules.

Signed-off-by: Michael Witten <[email protected]>
2008-02-19 09:31:02 -08:00
Michael Witten 73f8c2e68c ivlpp: Fixed incorrect lineno
Signed-off-by: Michael Witten <[email protected]>
2008-02-19 09:31:02 -08:00
Michael Witten 6103a72927 ivlpp: Removed delayed_close
This variable was used in yywrap purportedly to obviate
hidden access to a file that should be closable.

After investigating the code flex produces, it would
seem that these fears are unfounded.

Signed-off-by: Michael Witten <[email protected]>
2008-02-19 09:31:02 -08:00
Michael Witten 3bdf0a13d6 ivlpp: Clarification
A simple comment to clarify the use of standby for the inclusion stack.

Signed-off-by: Michael Witten <[email protected]>
2008-02-19 09:31:02 -08:00
Michael Witten 623073c722 ivlpp: Removed the unnecessary parser
The verilog preprocessing language is sufficiently simple
that the parser may be implemented by hand on top of the
lexical analyzer.

In fact, ivlpp was already implemented in this way; relevant
[bison] parser files specified no grammar, and the parser
entry-point (yyparse) was simply an indirect use of the lexical
analyzer (yylex).

Therefore, parse.y has been removed, invocations of yyparse()
have been replaced by yylex(), references to bison generated
files have been removed, and Makefile.in has been updated
accordingly.

Signed-off-by: Michael Witten <[email protected]>
2008-02-19 09:31:02 -08:00
Cary R e989f63192 Fix thread address check and wide vector unaligned copy.
This patch fixes two problems. The first is that thr_check_addr()
was being used inconsistently. It should be passed a real address,
but the resize of the vector should be at least one more than this
address. The extra and unneeded CPU_WORD_BITS was also removed
from the routine.

The second problem involved an invalid memory access in
vvp_vector4_t::set_vec() when the vector being copied was an integer
multiple of the machine word width. Under this condition there would
be no remaining bits that needed to be copied but the routine was always
trying to copying some remaining bits. This code is now only executed
when there is a remainder.

Neither of these appear to be causing runtime problems. The second one
was found with valgrind. The first were found while tracking down the
second problem.
2008-02-19 09:21:20 -08:00
Larry Doolittle 39dd22ace4 Adjust unusual spacing
minimal changes, nearly eliminates oddball/inconsistent
source code use of whitespace
2008-02-19 09:15:03 -08:00
Stephen Williams ceef77e15f Merge branch 'master' of [email protected]:git/verilog 2008-02-15 21:21:13 -08:00
Stephen Williams b0e4a6884a Objects of lexical scope use PScope base class.
All the pform objects that represent lexical scope now are derived
from the PScope class, and are kept in a lexical_scope table so that
the scope can be managed.
2008-02-15 21:20:24 -08:00
Cary R e7ea90c812 Explicitly initialize real values to 0.0.
This patch explicitly initializes real values to 0.0. Not doing
this was creating an intermittent time zero value problem.
2008-02-15 15:12:55 -08:00
Larry Doolittle f9bf502324 Correct format string
vvp_scope.c:1741: warning: format '%d' expects type 'int', but argument 5 has type 'long unsigned int'
introduced in commit
  331faa2217
2008-02-15 13:26:24 -08:00
Larry Doolittle d28fcb8941 Add missing consts
Fixes char usage introduced in commit
  331faa2217
2008-02-15 13:25:28 -08:00
Cary R 2b5560957a Force the L-value and R-value to match for real values.
Check that if either the L-value or the R-value are real then both
must be real. This prevents a runtime crash.
2008-02-13 20:44:16 -08:00
Cary R b6f26e62df Add support for delaying constants at T0.
This patch adds support for delaying constants at time zero. It also
cleans up the code in elab_net.cc to use this capability instead of
building it with an extra BUFZ to carry the delay information.
2008-02-13 20:10:55 -08:00
Stephen Williams 3f2fa29482 Factor compile-time scopes into PScope class
Modules, functions and tasks are named scopes so derive them all
from the PScope base class. These items all take scoped items, so
the eventual plan is to move these items into PScope.
2008-02-13 19:59:05 -08:00
Cary R 4d8db7b5bc Clean pulse events for real signals.
This patch cleans pulse events for real signals. Not doing this
can produce invalid results under some conditions.
2008-02-13 15:43:19 -08:00
Cary R 2bab415626 Add message for unsupported release of part/bit select.
This patch adds a real error message instead of an assert when
someone attempts to release a part or bit select. I plan to work
on the real functionality soon.
2008-02-13 15:37:53 -08:00
Stephen Williams 110bc2e6eb Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2008-02-13 15:27:39 -08:00
Cary R 331faa2217 Add signed bit based power to continuous assignments.
This patch adds the power operator for signed bit based values
in a continuous assignment. It also fixes a few other power
expression width problems. The expression width is still not
calculated correctly, since the correct method can produce huge
possible bit widths. The result is currently limited to the width
of the native long. This is because lround() is used to convert
from a double to an integer. A check in the code generator protects
the runtime from this limitation.
2008-02-11 20:06:41 -08:00
Stephen Williams f2ff25bfef Dump delays of constants. 2008-02-09 22:20:01 -08:00
Stephen Williams bc1d3eb7cd Add support for generate case
Generate case is a complex generate scheme where the items are
sub-schemes of the case generate itself. The parser handles them
something like nested generate statements, but storing the case
guards as the test expression. Then the elaborator notes the
case scheme and reaches into the case item schemes inside to make
up tests, select the generate item, and elaborate.
2008-02-09 22:19:42 -08:00
Larry Doolittle 63e2aa8d1a refine man page treatment of -d
also renames config file option from scope to scopes,
for consistency with the source code, and adds a
wiki reference to the man page.
2008-02-08 15:30:21 -08:00
Stephen Williams 0ac36dc5af Merge branch 'master' of [email protected]:git/verilog 2008-02-06 18:38:55 -08:00
Stephen Williams 3a300725de Output delays for part select nets.
Implement net delays for part select devices.
2008-02-06 18:37:42 -08:00
Cary R 85229a6cdc Add unsigned bit based power to continuous assignments.
This patch adds the power operator for unsigned bit based values
in a continuous assignment. It also refactors the power code for
normal expressions and continuous assignments.
2008-02-06 14:38:16 -08:00
Cary R 47d1d981d5 Mangle the scope for user functions in a continuous assignment.
User functions called in a continuous assignment were not getting
their scope mangled. This is needed to handle arrayed instances and
possibly other things.
2008-02-06 14:28:08 -08:00
Stephen Williams fb63bf7dba Compile portability issues. 2008-02-05 20:36:57 -08:00
Martin Whitaker 3d2e791e52 Fix for pr1887168.
This patch fixes some bugs in the implementation of signed integer
division with wide operands in constant expressions and adds support
for signed integer modulus with wide operands in constant expressions.
It also removes a few redundant lines of code.
2008-02-05 15:48:07 -08:00
Larry Doolittle aaf8908676 Document new -d flag to driver
followup to commit 6256dd8040
2008-02-05 15:44:14 -08:00
Cary R 4cf8920e48 Fix trimming of unsigned verinum values.
Incorrect trimming of unsigned verinum values was causing the
compilers unsigned constant verinum pow function to give
incorrect results. This patch restores the pow compile time
optimization and fixes the trimming to always leave a single
zero in the MSB.
2008-02-05 15:40:21 -08:00
Cary R e82293c981 Add unsigned bit based power support to normal expressions.
This patch adds bit based power support to normal expressions.
It also pushes the constant unsigned bit based calculation to
the runtime until the bit based method can be copied to the
compiler. Continuous assignments also need to use this type
of calculation.
2008-02-05 15:33:51 -08:00
Stephen Williams 1b410f0c7d Factor code for processing parameters and localparams
Replace some redundant code with a single function that handles the
elaboration and type management of parameters identically.
2008-02-05 13:37:33 -08:00
Martin Whitaker 51b1804660 Fix for pr1885847.
Currently, if a localparam declaration does not include a type or
range, the RHS expression is cast to an unsigned value. This patch
changes this to make the localparam inherit the type of the RHS
expression, as is done for parameter declarations and is specified
by the Verilog-2001 standard.
2008-02-05 13:06:42 -08:00
Cary R 40064b3181 Catch that we do not currently support unsigned bit based power.
This patch adds a check and prints a warning message when the power
operator is used with unsigned bit based values. It also fixes a couple
of typos and adds an asserts if the above power operator happens to
get to the tgt-vvp back end.
2008-02-04 13:35:44 -08:00
Larry Doolittle 0e6d6b7416 Fix typos in vpi/sys_display.c
Fallout from me trying to understand the origin of pr1780480
and pr1830834.  Too bad I don't understand c++ and vvp as
well as I understand English!

(Spelling and grammer fixes in comments. -ed.)
2008-02-04 13:33:24 -08:00
Larry Doolittle f4cf7b1799 Cleanup from yesterday's "Add more error checking" patch
Removes const char related compiler warnings,
tidies up mainline code by abstracting the human_readable_op() routine
2008-02-04 13:30:30 -08:00
Michael Witten 9c0d2c13c9 [PATCH] Removed #include asm/page.h on GNU/Linux
vvp/main.cc was including asm/page.h on GNU/Linux
systems, though that file does not often exist and
is not necessary.

Signed-off-by: Michael Witten <[email protected]>
2008-02-04 13:22:32 -08:00
Stephen Williams f1f2806e3c Get delays of signed extended continuous assignments right.
Padding and continuous assignment caused problems if the continuous
assignment includes a delay. The problem is that the padding was
not necessarily included in the delay. Rework the elaboration to
make sure the padding is indeed included in the delay.
2008-02-01 20:13:23 -08:00
Cary R db851c235f Add more error checking for operators that cannot use real values.
This patch adds some checks to verify that  shifts, the reduction
operators and the bit wise operators are not used with real values.
It also includes a few other cleanups.
2008-01-31 20:15:04 -08:00
Cary R 1595ae79fd Add support for real power (**) in normal expressions.
This patch adds support for the real power (**) operator in
normal expressions.
2008-01-31 19:54:37 -08:00
Cary R f049426f25 Add support for real % in a continuous assignment.
This patch adds conditional support (2001X) for the real modulus
operator in a continuous assignment.
2008-01-31 16:56:11 -08:00
Cary R 5e8a1bd8cc Add power operator (**) for real values in a continuous assignment.
This patch adds the power operator for real values in a continuous
assignment.
2008-01-31 16:48:52 -08:00
Cary R fa759c1802 Fix problem with delay at t0 when only some of the bits change.
This patch makes sure the delay is calculated correctly when only some
of the bits change and you are comparing against the initial (t0) value.
Basically you have to check the initial value against all the bits in
the new signal not just the first bit since the order that bits change
is not deterministic.
2008-01-31 16:42:51 -08:00
Cary R 4c5481f254 Add delays for shifts, concatenation and replication in a CA.
This patch add delays in continuous assignments for the shift operators,
concatenations and replications. It also reports an error if the user
attempts to take the modulus of a real value.

This patch uncovers a couple other problems in the system. I am trying
to fix one of them. I will report the other problem shortly.
2008-01-31 16:39:12 -08:00
Cary R 1609de6ed9 Fix some bit based delays in continuous assignments.
This patch fixes some of the delays in bit based continuous
assignments (unary -, unary +constants, string constants,
reduction operators and user functions).

Use draw_lpm_output_delay() in all functions that need it.
2008-01-29 20:27:53 -08:00
Larry Doolittle d9ac146b8f Spelling fixes
only comments and documentation
some punctuation and capitalization for good measure
Changelogs are purposefully untouched
2008-01-29 20:24:24 -08:00
Larry Doolittle 31afec57b1 Fix for pr1879226, large constant shift values
Addresses pr1879226 on a couple of levels.  Analysis:

NetNet* PEBinary::elaborate_net_shift_() didn't flag dist==lwidth
as a case where all bits of the input are shifted away, which made
it create a real concatenator for this case.  It attempted to create
NetNet*tmp with zero width, which doesn't work; (lsb,msb) ends up
as (0,-1), which is later interpreted as a 2-bit wide net.

Added an assert to the NetNet constructor to catch any other lurking
attempts to create zero-width nets.

Added short-circuit code to handle the case where all bits of the input
are shifted away.  This case used to be "handled" by an assert failure.
2008-01-29 09:31:16 -08:00
Stephen Williams 76039cf595 Merge branch 'master' of [email protected]:git/verilog 2008-01-28 21:33:14 -08:00
Stephen Williams 685095b229 Support delay of user function output
When used in continuous assignments, user defined functions may have
delayed output. Handle that by generating the proper .delay node when
needed to delay the output of a .ufunc node.
2008-01-28 21:29:03 -08:00
Stephen Williams abfccb65e9 User defined functions take real arguments
Allow user defined functions to take real value arguments and return
real value results in net contexts. Use the data type of the nets
attached to the ports to define the data types of the arguments and
return value.
2008-01-28 18:57:55 -08:00
Larry Doolittle 388bb93beb Spelling fixes
only comments and documentation
2008-01-28 09:15:39 -08:00
Stephen Williams 1eb581ab37 Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2008-01-28 09:13:33 -08:00
Stephen Williams 2f9ad47890 Merge branch 'master' of [email protected]:git/verilog 2008-01-27 18:25:11 -08:00
Larry Doolittle 47d65034db Spelling fixes
mostly comments, but includes some identifiers and message text
2008-01-27 18:18:13 -08:00
Stephen Williams b297a0a9fe Remove support for vvp32 build
Remove configure and Makefile support for the vvp32 build. Remove
also the libdir64 support.
2008-01-25 17:33:32 -08:00
Larry Doolittle 6256dd8040 Add support for ivl debug flags. 2008-01-25 11:16:44 -08:00
Stephen Williams 5ec91ec914 Add datarootdir to makefiles
It seems that later versions of autoconf expect datarootdir to be
use and set.
2008-01-24 12:10:31 -08:00
Stephen Williams 76164d7711 Rework compile-time evaluation of LT and GT
There was much redundant code in the compile-tile handling of the
less-then and greater-then of constant expressions, and much of it
was buggy. Unify much of the code and squeeze out the bugs so that
compile-time evaluations come out correctly.
2008-01-23 20:43:13 -08:00
Stephen Williams 89bf16b21e Signed-ness of parameters
Propagate the signedness of named parameters when they are evaluated.
2008-01-22 20:16:43 -08:00
Stephen Williams 5b17f2039a Fix bug in eval of <= compare
The compiler attempts to precalculate the results of <= comparisons.
Fix a few corner cases where the arguments are signed. Also fix the
important test of constant against non-constant where we try to test
if the non-constant value can possibly make the test fail.
2008-01-21 22:05:50 -08:00
Stephen Williams db25bba0d0 Fix assertion fail handling certain conditional delays
When conditional delays are in use, it is sometimes possible for there
to be no delays available for a given input event. In that case, skip
the delay processing for that case instead of crashing.
2008-01-21 19:57:17 -08:00
Cary R 10d25d2b88 Support delays for all operators in a continuous assignments.
Previously only the logical operators (~, &, |, ^, etc.) supported a
delayed value in a continuous assignment. This patch should extend this
to all operators. An extensive check of real values was done. The same
will be done shortly for bit based nets.

Checks for constructs currently unsupported in continuous assignments
provide a more explicit message (** operator, real user functions,
{!, && and ||} operators with a real argument).
2008-01-21 18:21:31 -08:00
Stephen Williams 3ea72109f8 Read and include sign of scanned decimal.
Fix simple bug where negative values read from the source file were
not getting their sign. The fix was proposed in pr1876738.
2008-01-21 18:11:28 -08:00
Stephen Williams b6b7d704b2 Clean up lexing of net literals.
The matching of net literals (i.e. Cx<> and T<> symbols) should not get
in the way of properly matching other symbols.
2008-01-21 17:52:40 -08:00
Stephen Williams 32d3e5ac46 Better formatting of Cr<> label for real valued drivers.
Rework the encoding of a real value in the Cr<> label to be similar to
the format used by the %loadi/wr instruction. This mantissa-expoment
format better carries all the bits of the desired real value with
plenty of fidelity and range.
2008-01-19 16:27:09 -08:00
Cary R ea1f448300 Real multiply in a cont. assign. is always 1 bit wide.
The continuous assignment multiply expands vectors to the sum
of the two widths. This is correct for bit based vectors, but
for real variables it should always be one bit wide.
2008-01-17 12:52:30 -08:00
Stephen Williams d992ec4bd4 Declare $rtoi in system.sft instead of the sys_funcs table.
The sys_funcs table should be left to those functions that are handled
internally by the compiler. Really, the internal sys_funcs table is a
legacy from the days before the compiler supported system function
tables in the .sft format.
2008-01-17 12:48:02 -08:00
Cary R 592a303ce5 Add $rtoi to system func. table and add check for NULL name.
System functions used in a continuous assignment must be defined
in the system function table since the name of the system functions
is kept in this definition. The default name is NULL which causes
problems. This patch add $rtoi to the system table and adds a check
for a NULL name.
2008-01-17 12:42:05 -08:00
Cary R 52a346ab38 Print real constant value comment with %g
The comment that shows the intended value for real constants was
being printed with a %f. This is wrong for large or small values.
This patch changes the %f to a %g to get more consistent results.
2008-01-17 12:31:08 -08:00
Cary R 0fa223434e Add check target to tgt-verilog/Makefile.in
Add the missing check target to Makefile.in.
2008-01-17 12:29:15 -08:00
Stephen Williams e1bf2ec019 Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2008-01-16 16:55:26 -08:00
Cary R ded0fbe5ef Fix user functions with right shift argument.
A right shift may generate extra bits to preserve the proper shift
characteristic. This patch replaces the assert that was forcing the
input vector to not be greater than the input port width with code
to only select the required lower bits from the vector if it is
larger than the input port.
2008-01-15 21:01:16 -08:00
Cary R 0370f30b20 Support variable delay of a variable selected assignment.
This patch adds support for the following statement:

<vector>[<i>] <= #<delay> <value>.

It is a copy with slight modification of code from the next
else/if clause.
2008-01-15 20:33:36 -08:00
Cary R eac6333d6c Add missing deletes for patch "Add real compar..."
Add two deletes that I missed in the previous patch.
2008-01-15 19:48:49 -08:00
Cary R 1ff31db2cc Add real comparisons in continuous assignments.
This patch adds real comparisons in continuous assignments.
It also converts bit based constants to real values when needed
by the comparisons.
2008-01-15 19:48:26 -08:00
Stephen Williams 59ee700634 Net arrays that are addressed are not dangling
The nodangle functor tries to delete NetNet objects that are not used.
But NetNet objects that are addressed by a NetArrayDq should never be
dangling. So make sure the NetArrayDq marks the target NetNet correctly.
2008-01-15 19:39:53 -08:00
Cary R e46f8220f3 Evaluate non-immediate signal selection.
This patch adds code to treat non-immediate signal selection the
same as the default logic evaluation
2008-01-14 19:55:14 -08:00
Cary R 7ff342f4da Fix type warning in tgt-vvp/eval_expr.c
In a previous patch I missed this type inconsistency.
2008-01-14 19:51:38 -08:00
Stephen Williams 190aefcf89 Use inttypes.h to get uint64_t print format string
Code generators should not include _pli_types.h to get standard int
types and strings. Use the inttypes.h header file instead.
2008-01-14 09:53:20 -08:00
Stephen Williams cdfe3a8289 Use inttypes.h to get uint64_t print format string
Code generators should not include _pli_types.h to get standard int
types and strings. Use the inttypes.h header file instead.
2008-01-14 09:47:48 -08:00
Cary R c899a6a52e Add %load/avp0 opcode and fix %load/vp0.
This patch adds a new opcode %load/avp0 that is used to load a
word from an array and add a value to it. %load/vp0 was
changed/fixed to do the summation at the result width not the
vector width. This allows small vectors to index large arrays with
an offset. A few errors in the opcodes.txt file were also fixed.
2008-01-13 19:47:49 -08:00
Cary R e18b64768e Add missing check target in some Makefile.in files.
This patch adds a check target to the Makefile.in files in the
tgt-null, tgt-stub and vpi directories.
2008-01-11 21:52:51 -08:00
Cary R 7157a68d08 Edge-control does not require conditional event
This patch allows the edge control to be used without a
conditional event.
2008-01-11 14:24:52 -08:00
Larry Doolittle e03fd9e6f2 fix leftover signed/unsigned comparisons
triggers warnings in gcc-3.3.5 and gcc-3.4.6 vintage compilers
2008-01-11 14:16:21 -08:00
Stephen Williams 731f1df70b Hook up input port part select properly.
The input part select that is used to match a module port to a short
vector connected to it was wired incorrectly.
2008-01-10 20:47:06 -08:00
Stephen Williams 9d0cdc8ae9 Hook up output port part select properly.
The output part select that is used to match a module port to a long
vector connected to it was wired incorrectly.
2008-01-10 18:20:21 -08:00
Stephen Williams f944d31353 Improved assertion on signal arrays.
Use ivl_expr_file() information to improve a signal assert message.
2008-01-09 14:24:30 -08:00
Stephen Williams 6cc8d0e536 Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2008-01-09 11:03:40 -08:00
Stephen Williams 3b89c1767c Merge branch 'pr1864110' 2008-01-08 18:56:12 -08:00
Stephen Williams 1f7957c612 Fix type handling of real-value system functions in nets
In nets, if system functions return a real value the function lookup
was getting the correct width, but was also setting the width to 0,
which confused down-stream net handling. Real-value system fuctions
have a width of 1. (1 real-valued scalar.)
2008-01-08 18:54:55 -08:00
Larry Doolittle eb5e7b792b Spelling fixes
Sorry, I can't help myself.  :-p
2008-01-08 17:26:55 -08:00
Stephen Williams 1db3c75ce6 Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2008-01-08 17:16:38 -08:00
Cary R c9e1e1b5cc Add missing include to sdf_lexor.lex
sdf_lexor.lex was missing the <string.h> include file which defines
strdup and strlen.
2008-01-07 19:07:11 -08:00
Cary R 61b6b8358d Speed up the conversion functions and add file/line info.
This patch modifies the conversion functions $rtoi, $itor,
$realtobits and $bitstoreal calltf routines to be more efficient.
This is done by caching the vpiHandle to the argument in the userdata
pointer. This eliminated the need to get the argument iterator, scan
and free the iterator.

It also updates the error messages to use the new file and line
number information that is available for system functions. It also
adds a check that verifies the functions are only called with one
argument and makes the errors fatal.
2008-01-07 18:59:52 -08:00
Cary R 4263f29044 Schedule sfunc invocations to avoid recursion and clean up.
This patch schedules the input value change to .sfuns calls to avoid
potential recursion problems. It also cleans up two put_value calls
that did unneeded loops when putting VectorVals and the width was
greaten than 32 bits.
2008-01-07 18:51:27 -08:00
Larry Doolittle d85683965d fix buggy SDF error message 2008-01-07 18:48:40 -08:00
Larry Doolittle f8d410e2d4 remove lint flagged by gcc-4.3
watch for possible behavior changes in
 elaborate.cc:3409
 vvp/vvp_net.cc:600
2008-01-07 18:39:10 -08:00
Cary R a16f5bc709 Update driver-vpi/* to match iverilog-vpi.sh
This patch updates the MinGW C version of iverilog-vpi to match the
shell version. This allows the vpi tests in the test suite to be run.
2008-01-07 18:36:48 -08:00
Cary R d95c77a58a Add vvp flag that allows $stop to act like $finish.
This patch adds a new flag to vvp "-n" that can be used to make
$stop and hence <Control-C> act like $finish. This may be desired
when using vvp in a non-interactive environment.
2008-01-07 18:23:18 -08:00
Stephen Williams ca50991eeb Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2008-01-07 16:26:17 -08:00
Stephen Williams 36bbf6ef5a Handle real-valued unary in general
Handle the unary minus with general sub-expressions.
2008-01-06 20:54:33 -08:00
Stephen Williams 9d55597b26 Elaborate net of real-value constant
Handle the special case of a unary minus net with the operand
that is a real-valued constant.
2008-01-06 19:59:31 -08:00
Stephen Williams bafd705478 Allow negative values for realtime net constants.
The lexor didn't allow for negative values for realtime net
constants. The minus sign was not accepted as a character in
the identifier string.
2008-01-06 18:57:16 -08:00
Larry Doolittle 8ea3b6b0b8 header includes for gcc-4.3 compatibility
minimal changes required to build without error
tested with gcc-4.3 (Debian 4.3-20071130-1) 4.3.0 20071130 (experimental)
2008-01-04 16:14:44 -08:00
Larry Doolittle e6ea5cd409 More lint removal
tgt-vvp/eval_expr.c  uninitialized variables
vpi/sys_display.c  uninitialized variables
vvp/vpi_priv.cc  deprecated string constant usage
vvp/vpi_vthr_vector.cc  deprecated string constant usage

the last entry invokes vpip_name_string() and uses const char *
in the same way as the other 9 callers in vvp/*.cc, the only
difference is that the argument is static instead of computed.
2008-01-04 16:12:33 -08:00
Larry Doolittle 6c5773c0e3 Synchronize lxt_write.c and lxt2_write.c with Tony Bybell
cvs -z3 -d:pserver:[email protected]:/cvsroot/gtkwave co -P gtkwave3
delete CVS logs embedded in files
had to add #define wave_alloca alloca to lxt2_write.h

differences remain relative to upstream .h files:
 whitespace
 value chosen for LXT*_WR_SYMPRIME

Regarding the latter, Tony writes "Don't worry about the .h file.
The only difference is a considerably larger initial hash size.
If this isn't a problem with Icarus now, it certainly doesn't
need to be bumped up."
2008-01-04 16:04:18 -08:00
Larry Doolittle 25ad1c174a Clean up compiler warnings
stupid changes to shut up the compiler
tested with gcc-4.2.2
2008-01-04 15:57:09 -08:00
Larry Doolittle 17cc661336 Squelch useless flex-induced warning messages
tested in a gcc-4.2.2 flex-2.5.33 environment
2008-01-04 15:54:03 -08:00
Cary R e01e7b1280 Add arith/mult.r and arith/sum.r
This patch adds the missing real multiplication and summation operators
and the code to generate them when needed.
2008-01-04 15:41:01 -08:00
Stephen Williams 4100ff71ef Data type handling of module ports.
Fix data type handling of module ports. When ports are declared
as ports and given data types in different statements, the parser
incorrectly (and silently) dropped the intended data type for the
default LOGIC type.
2008-01-03 20:13:56 -08:00
Larry Doolittle 59b2d23c64 chip away at compile-time warnings
1 x format string (real bug)
2 x uninitialized variable (potential bugs),
1 x parentheses around assignment used as truth value (shut up compiler)
2008-01-03 14:44:48 -08:00
Cary R 21730ab228 Fix definition missing in include file and missing UINT64_FMT.
This fixes the missing include file definitions and fixes three
cases that needed to us UINT64_FMT.
2008-01-03 14:14:54 -08:00
Cary R 07c6e51a58 Rework ivl_file_table_* interface and fix most vvp/examples.
Rework the ivl_file_table_* interface to be more generic and easier
to use. Also all the vvp examples except for memory.vvp have been
fixed to run correctly with the current vvp. Someone with a bit more
experience will need to fix memory.vvp.
2008-01-03 14:13:22 -08:00
Cary R c866be421e Add vpiFile and vpiLineNo to .sfunc (system function in cont. assign)
This patch add the vpiFile and vpiLineNo properties to system
functions that are called from continuous assignments.
2008-01-01 17:33:08 -08:00
Cary R 77061faa5c Add vpiFile and vpiLineNo for system functions.
Add the vpiFile and vpiLineNo properties to system functions.
Most other objects have stubs that return "N/A"/0. Interactive
functions (called from the debugger) use <interactive> for the
file name.
2008-01-01 17:27:03 -08:00
Cary R 9fd7c008f3 Create/remove default include directory.
The default include directory is created at install time and removed
if possible when uninstalling.
2008-01-01 17:16:08 -08:00
Stephen Williams 6476be462e Pass defines into library files.
Use the precompiled defines file support of the ivlpp preprocessor
to pass defines made in the main program to processed library modules.
In other words, a `define in the Verilog source will be visible to
library modules.
2007-12-30 21:26:25 -08:00
Stephen Williams a3c1fb8c8a Supoprt precompiled defines
Core preprocessor support for writing out and reading precompiled
defines. The preprocessor can read initial precompiled defines from
any number of specified source files, and can write all the defines
into a specified output file.
2007-12-30 18:47:32 -08:00
Cary R ef1739dbec Add better error reporting for port declarations.
Add an error message for NULL port declarations and for a ';'
that could be left over from building a port declaration from
an old style declaration.
2007-12-29 17:55:53 -08:00
Stephen Williams fea1febf54 Generate explicit locals in the vvp target.
With this change, local symbols are not emitted in the vvp target,
but are marked as local. When thus marked, the vvp run time does not
offfer any VPI access and the signals (net or var) are effectively
invisible.
2007-12-27 18:34:12 -07:00
Stephen Williams 931d08a9fc Add local_flag syntax to .net and .var statements. 2007-12-27 17:56:32 -07:00
Stephen Williams 58d3d2f265 Better track signals marked local. 2007-12-27 16:47:01 -07:00
Stephen Williams 9235ec665b Correct bit widths and pad of certain part selects
Zero-based part selects are a special case that is handled with
optimized code. Properly handle the part select width to get the
desired padding.

Signed-off-by: Stephen Williams <[email protected]>
2007-12-26 11:22:33 -05:00
Cary R 1e2d8bc55a Fix real function PLI 1 code.
The code to handle real functions using the PLI 1 interface was
missing some functionality. This patch fixes that and fixes a
bug in the veriuser.h include file.
2007-12-23 19:29:33 -05:00
Cary R 77f8d3225c Fix core dump in recent vpi_get_str code changes.
The recent changes to vpi_get_str had a minor problem that was
causing a core dump when trying to get the vpiFullName of an
arrayed signal. Basically vpi_get_str is not reentrant so the
name must be duplicated. It must also be duplicated to work with
the free in the code (do not free a result_buf).
2007-12-23 19:26:37 -05:00
Stephen Williams 8a6626dcaa Standard implicit include directory
Add support for a default, standard, implicit include directory
in the base directory for the ivl installation, where standardized
Verilog header files may be placed.
2007-12-23 19:20:45 -05:00
Stephen Williams 08752453b4 File line information for expressions
Add ivl_target support for file and line numbers of expressions.
2007-12-22 17:19:45 -05:00
Stephen Williams 1db19b8703 Make statement file lineno available to targets.
Make the Verilog file/lineno of statements available to loadable
code generators. Make sure the information is properly set for
system task calls.
2007-12-22 09:31:24 -05:00
Stephen Williams 7975e14b5c LineInfo uses perm_string for path.
Rework the handling of file names to use a perm_string heap to hold
the file names, instead of the custom file name heap in the lexor.
Also rename the get_line to get_fileline to reflect its real duties.
This latter chage touched a lot of files.
2007-12-20 12:31:01 -05:00
Stephen Williams dff59f8ad8 Merge branch 'master' of [email protected]:git/verilog 2007-12-18 16:48:11 -08:00
Larry Doolittle 9772068bbc vpi_get_str improvements
Gets rid of a few warning: deprecated conversion from string
constant to 'char*', follows IEEE 1364-2001C 27.10 in more cases,
and fixes at least one real bug (look at the previous use of
strdup/strcat in real_var_get_str() and signal_get_str()).
2007-12-18 15:11:50 -08:00
Stephen Williams 4c8a7b221c Proper padding of constant bitwise operands
When evaluating bitwise binary expressions at compile time, get the
signed/unsigned padding correct. Pay special attention to the case
of $signed/$unsigned  changing the signedness of the operand.
2007-12-17 21:00:18 -08:00
Larry Doolittle 752cf21790 Warnings and spelling fixes.
Correct a variety of spelling errors, and eliminate
a variety of compile time warnings.
2007-12-17 17:42:09 -08:00
Gyorgy Jeney e67b6d2b4b Fix command line handling of warning flags.
Prevent an overflow of command line flags if the -Wall argument
is used multiple times, and fix processing of individual flags
that may be in the beginning of the warnings flag buffer.
2007-12-16 21:15:55 -08:00
Stephen Williams 1506a0bf8c Pad type-punned user functions properly
When user defined function calls are withing a $signed, the result
needs to be properly padded. To make this work, handle padding of
a function result exactly type the padding of a signal vector. this
is natural in that the function return value *is* in a signal vector.

This fixes pr1841300.
2007-12-15 22:05:56 -08:00
Martin Whitaker fa2712a3ee Fix for pr1851310.
This patch fixes a bug in the compiler which prevented array words
from being correctly selected when used in the RHS of a continuous
assignment.
2007-12-15 15:56:54 -08:00
Stephen Williams f28dfb6178 Better SDF error handling
Handle basic errors like incorrect or missing SDF files.
2007-12-15 15:25:25 -08:00
Stephen Williams 97f7a97db7 NoEdge IOPATHS may match multiple specify paths.
An IOPATH in the SDF file may match all specify paths no matter
the conditions or edge specifications.
2007-12-14 21:04:20 -08:00
Cary R ff4cba6a96 Add full argument type checking to $dumpvars.
This patch adds argument type checking for $dumpvars module and
variable arguments.
2007-12-14 20:23:50 -08:00
Cary R f53f042553 Fix scope type calculation error in draw_scope (all dumpers).
This patch fixes the calculation of the scope type in draw_scope.
This code is really only used in the VCD dumper so I commented it
out in the other two. The problem was that the lower scope was
used to calculate the scope type. It is also now an error to try
to draw an invalid scope type.
2007-12-14 20:18:13 -08:00
Stephen Williams a83d6bb02c Merge branch 'sdf' 2007-12-13 20:57:39 -08:00
Cary R d3880d02c7 Cleanup dumper code (VCD/LXT/LXT2/none)
This patch fixes a number of problems associated with the various dumpers.

1. It catches the problem uncovered in pr1809904 and prevents the core
   dumps from happening. It prints a warning message if you try to change
   the file after the program has started dumping data to the file.

2. It makes all the dumpers work in the same manner. Before the VCD
   $dumpfile was processed at compile time, but the LXT/LXT2 versions
   did this at run time. The correct place for this is the run time so
   that you can pass the task a calculated name.

3. All the dumpers use common compiletf routines located in vcd_priv.c

4. Make the LXT/LXT2 $dumpfile commands only get the file name and
   let $dumpvars actually open the file. This matches the VCD code.

5. Fix the $dumpfile code to allow calculated file names.

6. Make dumpvars without a scope/variable match all toplevel modules
   not just the toplevel module the $dumpvars was located in. This
   now matches the standard (2001).

7. Simplify the no dumper code (vcdoff.c) and add missing functions.

8. Cleanup the code and messages.

9. vvp can take -none for no dumper.
2007-12-13 20:48:16 -08:00
Cary R f245dc8d96 Do not run the first time step if the compilation failed.
This patch fixes another minor problem introduced by the process
end of simulation events. Specifically if the compilation has
indicated we should not run do not even start the main event loop.
2007-12-13 20:43:57 -08:00
Stephen Williams a14d836be3 Support annotation of edge paths
Parse SDF file annotations of edge sensitive delay paths.
Add vpi support for getting the specified edge sensitivity of
an edge sensitive path, and annotate paths with proper attention
to the edge that is specified for the path.
2007-12-13 20:42:06 -08:00
Stephen Williams 8d9998c44e Minor optimization of partial load/v
When loading a part select from the least significant bits, it is
OK to use the %load/v instruction to strip the high bits off. This
allows the zero-based part select to work in one step, without
loading excess bits.
2007-12-09 17:28:49 -08:00
Stephen Williams bee4772ac8 Fix optimization of base==0 part select
Some patch caused a variable that held the constant base of a part
select to become unassigned. This led to unexplained failures to part
select a signal. Fix by properly detecting the case of a constant base
of 0 for the part select.
2007-12-09 17:00:32 -08:00
Stephen Williams 0fbdcbeb02 Minor cleanup.
Minor cleanup of some commented out code, and some minor simplification
of the subarray code.
2007-12-08 21:10:58 -08:00
Cary R 088b4e2fb8 Fix function/task scope searching.
When looking for a function or task (scope) do not compare the final path
component with the current module name since it cannot be an up reference.
2007-12-07 17:57:26 -08:00
Stephen Williams b60dd0b18f Opcode table order is important.
The %ix/get/s instrution disappeared because the code to search the
table expects that the table is sorted. So fix the sort.
2007-12-07 17:28:58 -08:00
Stephen Williams 64936d07e5 Add %ix/getv instruction
The %ix/getv instruction loads an integer register directly from
a signal vector. This is an optimization that an index register
is loaded from an expression is only a signal. It avoids the thread
vector space.
2007-12-07 13:12:19 -08:00
Cary R 937397b24c Do not use the error token to get file/line number information.
Using the parser supplied error token to get file and line number
information appears to give incorrect results at best and core dump
at worst. This patch uses the closest real token that makes sense
to alleviate this problem.
2007-12-05 18:50:54 -08:00
Cary R 78b2eb5026 Generate array word names with new array VPI functionality
Use the new array VPI functionality (vpiIndex, vpiParent, vpiArray)
to dynamically generate array word names. The old patch to implement
was mostly reverted.
2007-12-05 18:38:28 -08:00
Cary R 1782175c52 Add vpiArray, vpiParent, vpiIndex to VPI
Add the array related VPI calls. These will be used to generate
the array word name only as needed to conserve space. This patch
also makes scanmem3 from the vpi test work correctly after a
slight gold file update.
2007-12-05 18:37:58 -08:00
Stephen Williams 73a7fb09fc Merge branch 'performance' 2007-12-05 17:50:57 -08:00
Stephen Williams 19e8c05788 Optimize X check in vector subarray
Optimize check for X bits while doing vector4 subarray. In particular,
do X checks a word at a time so that individual bits need not be tested.
2007-12-04 22:16:31 -08:00
Stephen Williams 3b90a827e5 Fix simple compile warnings. 2007-12-04 22:14:26 -08:00
Stephen Williams 8f519531f3 Optimize load-add with load/add instruction
Where and expression is an immediate value added to a signal value,
it is possible to optimize them to a single instruction that combines
the load with an add at the same time.
2007-12-04 19:15:15 -08:00
Stephen Williams 68a9526fec Minor performance tweak of vector_to_array function. 2007-12-02 19:00:12 -08:00
Martic Whitaker 577da5c0d3 Fix for assertion error when expanding macro.
The patch for adding support for macros with arguments contained
a leftover debugging aid. This patch corrects the code. It also
should eliminate some compilation warnings.
2007-12-02 09:09:53 -08:00
Stephen Williams e5381feb85 Clean up functor counters
The functor counters were left over from the v0.8 release. Rework
the counters to be relevent to the current state of vvp.

Signed-off-by: Stephen Williams <[email protected]>
2007-12-02 08:47:06 -08:00
Martin Whitaker 680196953b Add support for text macros with arguments.
This patch modifies the preprocessor to handle text macros with
arguments. It also fixes a bug that prevented a `line directive
being issued after a multi-line text macro had been instantiated.
2007-12-01 19:32:42 -08:00
Larry Doolittle 103138cf4b Fix compile time warnings
These warnings actually look a lot like errors.
2007-12-01 18:04:43 -08:00
Stephen Williams f602687187 Support second argument of sdf_annotate
The second argument of $sdf_annotate is the scope that is to be
annotated. The argument is optional, and the default is to annotate
the current scope, where the $sdf_annotate is invoked.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-30 21:57:38 -08:00
Stephen Williams 25a24e748f Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2007-11-30 21:11:44 -08:00
Stephen Williams 26aee6cbae Clean up warnings for round() function declaration. 2007-11-30 21:11:27 -08:00
Stephen Williams 47bffa24a7 Include stdlib.h to remove compile warnings. 2007-11-30 10:20:30 -08:00
Cary R bf49400fb2 Add vpiIterator and vpiMemory to string version of vpiType
This patch adds both vpiIterate and vpiMemory to the list of
types that can be displayed as strings.
2007-11-29 22:41:47 -08:00
Cary R eeb669c1c9 LD should be based on $CC and not hardcoded to gcc
Fix the default loader so it will be whatever the default C
compiler is ($CC).
2007-11-29 22:38:33 -08:00
Cary R 6a5ec481c8 Add -D to iverilog-vpi and update documentation.
This patch adds a -D option to iverilog-vpi and updates the manual
page to document this option and some others that were missing.

From c7347239335558b26c873ea5e64d278d1feff38a Mon Sep 17 00:00:00 2001
From: Cary R <[email protected]>
Date: Thu, 29 Nov 2007 10:31:25 -0800
Subject: [PATCH] LD should be based on $CC and not hardcoded to gcc

Fix the default loader so it will be whatever the default C
compiler is ($CC).
---
 iverilog-vpi.sh |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/iverilog-vpi.sh b/iverilog-vpi.sh
index fbccedb..d2512cc 100644
--- a/iverilog-vpi.sh
+++ b/iverilog-vpi.sh
@@ -25,7 +25,7 @@ CXX=@IVCXX@
 CFLAGS="@PIC@ @IVCFLAGS@ -I@INCLUDEDIR@"
 
 # These are used for linking...
-LD=gcc
+LD=$CC
 LDFLAGS32="@SHARED@ -L@LIBDIR@"
 LDFLAGS64="@SHARED@ -L@LIBDIR64@"
 LDFLAGS="$LDFLAGS64"
-- 
1.5.3.4
2007-11-29 22:36:59 -08:00
Stephen Williams fde334a5d2 Handle empty INSTANCE name
Handle the special case that the SDF CELL instance is empty. In this
case, the SDF file is requesting the current scope instead of an
instance within the scope.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-28 18:17:01 -08:00
Stephen Williams 6416a799c9 Identifers include _ and $ characters. 2007-11-28 18:05:32 -08:00
Stephen Williams d92e7d904f Handle hierarchical instances
Iterate through hierarchical names created by the SDF
parser, and follow the scopes to the cell.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-27 21:44:25 -08:00
Stephen Williams 26f1d50248 Fix parsing of hierarchical identifiers
the lexor didn't allow numbers in the IDENTIFIER name,
and the parser wasn't very nice with IDENTIFIER errors.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-27 21:42:20 -08:00
Stephen Williams 2a269f1bb7 Parse TIMINGCHECK syntax
Parse and ignore the TIMINGCHECK rules, and also parse
and ignore INTERCONNECT delays.
2007-11-27 20:53:48 -08:00
Cary R 2851b9bd9a Add the ability to dump array words
This patch adds the ability to dump array words. The words are only
dumped if they appear in a $dumpvars() statement (they are not dumped
by default). The name used for the word is <array_name>[<index>], so
you can get unexpected name conflicts.

There is also a slight increase in the memory requirements since each
array word now keeps its own name information. In the future we would
like to change this, but that is a much larger rewrite of the array
code in vvp.

This patch also needs the "Prefix escaped identifier ..." patch to
work correctly (the array word name is an escaped identifier).
2007-11-26 18:08:04 -08:00
Cary R fd252d1e27 Fix Makefile to correctly work with new sdf code.
Fix the Makefile dependencies so the new sdf code will compile
correctly and remove the appropriate files with make clean.
2007-11-26 18:02:26 -08:00
Stephen Williams ca10a6867a Handle comments
Ignore C/C++ style comments, and also handle a few error
cases a slight bit more elegently.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-26 17:59:53 -08:00
Stephen Williams 79232f46d8 Proper signedness of comparison operands
Comparison operands are signed only of both operands are signed.
If one is unsigned, then they both are unsigned. This does not
affect the signedness of the comparison itself, which is unsigned.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-24 20:32:35 -08:00
Stephen Williams ea70ae00aa Merge branch 'sdf' 2007-11-22 19:01:20 -08:00
Stephen Williams 5af8fff980 Command line control of warnings
Implement extended vvp command line options to control the amount
of detail that the sdf annotator emits while parsing the source
file.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-22 18:22:46 -08:00
Stephen Williams 4986e550b1 Pass SDF delays into simulation
Pass parsed SDF delays into the vvp run time as vpiScaledRealTime
variables, and handling the mapping of 2-values to 12-delays.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-22 17:34:51 -08:00
Cary R 5bd3dd5fb6 Suppress duplicate variable definitions in VCD header.
The LXT and LXT2 formats ignore/work with duplicate variables in
$dumpvars() commands, but VCD output includes extra definitions that
may cause some confusion. This patch checks for duplicates and prints
a warning when they are being suppressed.

It also corrects some error messages in the LXT and LXT2 files to not
reference VCD and some other message cleanup.
2007-11-21 19:54:24 -08:00
Cary R 82b1fcbef4 Make min/typ/max default warning message universal.
The min/typ/max default warning was not being produced in all
locations a min/typ/max expression could be used. This patch
adds the default warning code to all locations. It also
modifies the manual page to explicitly state that only the
first ten warnings are printed.
2007-11-21 19:33:42 -08:00
Cary R 5d80c4856d Prefix escaped identifiers in VCD and LXT(2) output with a back slash.
GTKWave needs to have escaped identifiers properly escaped (preceded
with a back slash) in its VCD input. Without this the name may not
display correctly. Even though it is not required, to keep things
consistent LXT and LXT2 formats also prefix escaped identifiers with
a back slash.
2007-11-21 19:25:55 -08:00
Stephen Williams 73e60f4b81 Match parsed IOPATH to cell and modpath to be annotated. 2007-11-20 22:20:22 -08:00
Cary R 870aa417ba Add vpi_get_delays and vpi_put_delays in vvp.def
Add vpi_get_delays and vpi_put_delays to vvp.def so they are
available in Cygwin.
2007-11-19 19:53:31 -08:00
Martin Whitaker fbebcccaed Fix for pr1833776.
This patch fixes a bug which caused a generate loop with a non-zero
initial value to generate the wrong number of block instances.
2007-11-18 22:06:46 -08:00
Martin Whitaker d240d33558 Fix for pr1833754.
This patch adds checks for duplicated scope names during scope elaboration.
2007-11-18 22:00:40 -08:00
Martin Whitaker dd56dd1635 Correct naming of unnamed generate blocks.
This patch causes unnamed generate blocks to be automatically named
using the naming scheme defined in the Verilog-2005 standard. This
is a fix for the problem discussed in pr1821610.
2007-11-18 21:01:35 -08:00
Cary R b80ce9230a Some synthesis errors were not incrementing the error count
This patch cleans up some of the crashes in the synthesis
code by incrementing the error count as appropriate. This
also removes the three false positives in the test suite
(Sorry-Ran-PASSED). A few other messages will change in
the test suite as well (blocksynth? and basiclatch).
2007-11-18 19:41:02 -08:00
Cary R 35382b5801 At EOS only save the simulation time if it is asked for.
This was causing a core dump for a number of the vpi test cases.
The problem was that they did not need the simulation time, so it
was being set to NULL. The problem was the EndOfSimulation callback
was always setting cb_data.time to the current time. A big problem
when the pointer was NULL. The solution is to only set the time
when the pointer is not NULL
2007-11-18 19:37:35 -08:00
Cary R 3765f5f421 Do not MSB extend constants that already have a defined width.
During elaboration certain constants were getting extended with
the MSB. This patch makes that happen only if the constant does
not have a length. At this point most should have a length so
effectively every unsigned value is extended with 0.
2007-11-18 19:29:09 -08:00
Cary R ca49d7efa4 Some indexed array selections need to be evaluated.
Array selections that are not constant need to be evaluated for
task/function calls.
2007-11-18 19:12:39 -08:00
Stephen Williams c5950e3aa6 Add stub $sdf_annotate function.
Add the $sdf_annotate function infrastructure, and a stub parser
that can parse miniman SDF files.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-18 17:36:03 -08:00
Cary R b921a56ad1 A leading underscore is valid for macro substitutions.
For text macro substitutions the lexor did not allow leading underscores.
This patch fixes that omission. All other places that text macros may be
used appear to be correct.
2007-11-14 20:21:20 -08:00
Cary R 5a88cb5c01 Remove shift/reduce problems from dimensions patch.
This patch needs to be applied after the dimensions checking patch
to remove the shift/reduce errors it created.
2007-11-14 19:42:47 -08:00
Cary R 0d5808dd92 Display an error for currently invalid number of array dimensions.
Most types in Icarus support a single array dimension (reals do
not support arrays at all). If you try to use an invalid number
of dimensions the parser will now display an error message.
2007-11-14 19:42:25 -08:00
Stephen Williams 0456a1b339 Use movi to load string values.
String values are known to be 2-value bits, so they are natural
candidates for using the movi instruction to load the value in
far fewer instructions. With this patch, up to 16bits (two bytes)
at a time can be loaded per instruction.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-13 21:14:07 -08:00
Cary R 4356f9c478 Process expression strings with octal constants correctly (tgt-vvp)
tgt-vvp was taking strings and processing them as is, but the strings
could contain octal constants. These constants needed to be converted
to binary form before they could be turned into a bit pattern.
2007-11-13 20:20:16 -08:00
Cary R 9c8b63110d CMOS is strength aware
CMOS gates like NMOS and PMOS have a strength aware output.
They were missed when the NMOS and PMOS were fixed. "cmos.v"
will now pass in the test suite.
2007-11-13 19:57:02 -08:00
Cary R 4b755deea0 Fix the debugger to finish correctly.
A previous patch I submitted to try and keep the $finish time
events missed the case of an infinite loop that did not advance
the micro time step which then prevents the debugger from
generating a finish (you can interrupt an infinite loop, but you
could not finish out of it). This patch adds a check for a
finish after each debugger call to fix this problem.
2007-11-13 19:47:06 -08:00
Stephen Williams 9759c19734 Implement release of linked force nodes
When nets are forced by non-constant expressions, the value is linked
to the destination net through a force_link. This patch adds the code
needed to unlink a force/link so that release and new force/links can
work. This fixes pr1735836.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-13 19:35:44 -08:00
Stephen Williams d7a0f48944 VPI put and get of delays to module path
Add support for access to delays via scaled real times.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-10 19:54:21 -08:00
Cary R 17960013e5 Add a mark at simulation end for vcd/lxt/lxt2 files.
This patch adds marks at simulation end if needed and enabled (on
and not over the limit) for vcd/lxt/lxt2 files. End of simulation
callbacks also now have the correct simulation time. The default
file names for lxt and lxt2 now match the vcd file except for the
extension. lx2 is also an alias for lxt2 and the default lxt2 file
extension is lx2. This matches what GTKWave expects. Any lxt2
diagnostic output print LXT2 instead of LXT to make it clear which
dumper you are using.
2007-11-10 16:27:45 -08:00
Martin Whitaker d6f6df829e Fix for pr1828642.
This patch fixes a compiler bug that causes it to reject memory declarations
inside a generate statement.
2007-11-10 16:09:20 -08:00
Cary R 77ed103682 Add vpiTopModule
This patch adds functionality for vpiTopModule.
2007-11-10 12:09:00 -08:00
Cary R 83a1ee8cf5 Add vpi_mcd_flush to vvp.def for cygwin
In the recent changes to $fflush() I missed adding this for cygwin.
2007-11-10 12:05:26 -08:00
Stephen Williams bab9c7adba Proper compile time processing of arithmetic right shift
Handle arithmetic right shift during compile time. This comes
up with both the operands are constant expressions. the compiler
is able to evaluate this down to a constant to replace the
expression.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-08 21:52:38 -08:00
Martin Whitaker 05a6e69d2d Support nested generate schemes.
This patch adds support for nested loops and if-else decisions in generate
statements.
2007-11-07 21:27:00 -08:00
Cary R e26b9e72a2 More array fixes and down indexed part selects can be a lval.
Here are some more array fixes. They are mostly better error messages
instead of just asserting and some code cleanup. The one new thing
that probably should have been a separate submission is that down
indexed part select [base -: width] can now be a lvalue.
2007-11-07 20:53:27 -08:00
Cary R 51293b6e91 Fix/enhance array part select code.
This patch fixes/enhances the array part select code. It also
verifies that any lval array index in a continuous assignment
is a constant value. Also, %set/av now uses index register 1 as
described in the documentation (as a bit offset).
2007-11-07 20:52:56 -08:00
Cary R e39b3fea1f Display a warning for a part select of an array.
It is illegal to perform a part select on an array. This patch
adds an error message instead of failing an assert.
2007-11-07 20:28:46 -08:00
Cary R 2ea6692833 Make patch for pr1792108 synth aware.
This patch makes the behavior selection fro pr1792108 depend on the
synth* functors.
2007-11-07 20:00:51 -08:00
Cary R 221c99c5f4 Only remove output nets for synthesis backends.
During elaboration only remove output nets for synthesis backends.
2007-11-07 20:00:33 -08:00
Cary R dbce0cb05a Fix @* to correctly handle non-input nets.
@* was only expanding to input nets. nex_input() for blocks was removing
any output net that was also an input. There was also a bug in how output
nets were removed. Only outputs currently defined were removed from the
input list.

always @(*) begin
  y = a;
  z = y;
end

would report "a" as an input. While

always @(*) begin
  z = y;
  y = a;
end

would report both "a" and "y" as inputs.

To fix this all nex_inputs now take a flag that when true (the default)
correctly removes any output from the input list. Both the above cases
will now return "a". If the flag is false outputs which are also inputs
will be included in the input list. This is what the @* elaboration code
uses to get the correct sensitivity list.
2007-11-07 20:00:05 -08:00
Cary R 9a96d80a9e Error message for duplicate declare of arrays.
Replace an assertion with an error message for duplicate
declartion of arrays.
2007-11-07 19:48:47 -08:00
Stephen Williams 5352a0cc40 introduce vpi access to modpath objects
Add/rework VPI access to modpaths. This allows VPI code access to
paths described in specify blocks. In the process, the VPI structure
has been reworked to conform to the IEEE1364 standard.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-06 21:01:13 -08:00
Stephen Williams 859d8b3502 Rework vpi_get_delay of modpaths
Cleanup klunky implementation of vpi_get/put_delays for modpath
objects. Remove some useless members.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-06 20:26:03 -08:00
Cary R 7e59186f1e Fixes for wide division/modulus.
Wide division/modulus (more bits than unsigned long) gave incorrect
results when both the divisor and dividend where the same. They also
did not produce an error message when dividing by zero.
2007-11-05 20:24:33 -08:00
Cary R d5d6aca972 Enhance $fflush() to support a mcd/fd argument.
This patch enhances the current fflush implementation to flush a mcd or an
individual fd. Before it always flushed everything. A compiletf routine was
also added.
2007-11-05 20:07:55 -08:00
Stephen Williams 2fac019d9d modpath nodes need vpi expression handles
Generate the code that attaches the VPI handle of the source and
destination to the modpath object.
2007-11-05 19:59:27 -08:00
Stephen Williams 5bcbd09ed9 Make the modpath source define the VPI modpath object.
The modpath source node defines the modpath object, and carries the
nodes for the source expression. The modpath outputs are references
by pointers to the vpiModPath that is not in itself a vpi object
any more. This makes the VPI view of a module path look like the
source-destinaiton pair that is the IEEE1364 description of the
modpath.
2007-11-05 19:58:20 -08:00
Stephen Williams 80fad3df32 Clean up excess debug print from modpath patch
Clean up excess debug print from modpath patch.

Signed-off-by: Stephen Williams <[email protected]>
2007-11-02 20:52:06 -07:00
Cary R 63ca4e6d41 Implement $ftell, $fseek and $rewind system functions.
This patch implements the $ftell, $fseek and $rewind system function.
2007-11-02 20:32:46 -07:00
Cary R 965374acf9 Implement $feof() from 1364-2005.
This patch implements the $feof() function from 1364-2005. It also
comments out a debugging line in the scanf code.
2007-11-02 20:27:48 -07:00
Stephen Williams 68cf5baba5 Out path term for modpaths
Add vvp support for modpath path term outputs. This also introduces
the concept of path terms and moves towards the path term in general
for getting at the endpoits of a modpath.
2007-11-02 19:59:08 -07:00
Stephen Williams 5c69e243ac Put modpaths in correct scope.
Modpaths need to be in the proper scope in order to be available to
vpi functions. The code generator manages that by writing the modpath
records with scope switch functions. Batch the modpath records at the
end of the structural stuff so that the scope switching doesn't cause
trouble.

Also seperate the modpath code into its own source file.

Signed-off-by: Stephen Williams <[email protected]>
2007-10-31 21:45:34 -07:00
Stephen Williams 0d9ed65e8c Give delay paths scope.
Delay paths need a scope. This helps the code generators bind the
modpaths to the correct scope. This patch doesn't actually make use
of the information, it just makes it available to code generators.

Signed-off-by: Stephen Williams <[email protected]>
2007-10-31 21:39:29 -07:00
Stephen Williams 148e6768f6 Clean up modpath vpi interface
Clean up rather poorly written modpath vpi support, fixing the
parse of the modpath syntax element to not use pointless globals.
Collect the modpath code into the delay.cc file instead of the
inapropriate vpi_signal.cc source file.

Signed-off-by: Stephen Williams <[email protected]>
2007-10-30 20:14:40 -07:00
Cary R 54aae2c1c2 Fix number to real mask generation
The << operator may not be defined when the RHS is greater than or
equal to the LHS width. To work around the problem the mask is
incrementally generated.
2007-10-19 17:10:34 -07:00
Cary R 3543c0605c Disable lxt support if libbzip2 is not found.
Configure was checking for libbzip2, but it was not doing anything with
the result. This patch disables lxt support if libbzip2 is not found.
2007-10-18 21:17:50 -07:00
Stephen Williams 230d0f24de Reformulate number-to-real on vvp code generator
There have been reports in the field of number-to-real conversions
doing bad things with the calculated mantissa. This patch eliminates
a opssible portability problem by reworking the negating of negative
mantissa values.

Signed-off-by: Stephen Williams <[email protected]>
2007-10-18 21:09:12 -07:00
Cary R 676695c78f Check for extra digits in sized binary, octal and hex constants.
Print out a warning if extra digits are given for sized binary, octal
or hex constants. Decimal constants are very hard since we never
calculate the true number of bits the digits represent, so for now
decimal constants are not checked.
2007-10-18 10:12:20 -07:00
Cary R 58e4c562cb Add $dumplimit task.
The attached patch add an implementation for $dumplimit(). It does
not do a hard limit to the file size, but for VCD files it completes
the current time step and puts a comment in the file. For lxt and
lxt2 files the functionality is in place, but because of buffering
the file can be slightly larger than expected.
2007-10-16 14:11:51 -07:00
Stephen Williams 6e6392f2d7 Merge branch 'master' of [email protected]:git/verilog 2007-10-15 20:24:08 -07:00
Stephen Williams 27b704b054 Regularize padding of signed constants
Factor common code for processing signed constants to be padded.
In the process, fix some minor bugs in the padding decisions.

Signed-off-by: Stephen Williams <[email protected]>
2007-10-15 20:17:06 -07:00
Stephen Williams e1dbe7eede Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2007-10-11 14:50:00 -07:00
Cary R 5410f0f998 Implement $fopenr(), $fopenw() and $fopena().
Implements $fopenr(), $fopenw() and $fopena() from Chris Spear's File I/O
for Verilog.
2007-10-11 14:39:33 -07:00
Cary R 7bba276a79 Propagate sign for constant numbers inside $signed()/$unsigned().
The sign information from $signed() or $unsigned() was not being
propagated correctly for constant numbers.
2007-10-10 20:27:30 -07:00
Stephen Williams e97bdf8b21 Support for wide modulus operations.
Compile time support for wide modulus.

Signed-off-by: Stephen Williams <[email protected]>
2007-10-09 21:40:08 -07:00
Stephen Williams a0b1272a62 Fix signed/unsigned warnings
Fixed some signed/unsigned warnings, including one that caused an
actual runtime error if not dealt with safely.

Signed-off-by: Stephen Williams <[email protected]>
2007-10-09 21:19:38 -07:00
Stephen Williams 1086c480af Merge branch 'master' of [email protected]:git/verilog 2007-10-09 21:06:19 -07:00
Stephen Williams ae16eacec9 Argument to $unsigned is self-determined.
The argument to $unsigned is self-determined no matter what the
context the $unsigned itself is in. This is important only where
the result can be negative but the result width is context-determined.
Do ocntext fitting manually to prevent the context fitting it and
affecting the expression argument.

Signed-off-by: Stephen Williams <[email protected]>
2007-10-09 20:46:17 -07:00
Stephen Williams c08e547d1d Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2007-10-09 10:12:55 -07:00
Cary R 38a88014cb [PATCH] Implement System Verilog $urandom and $urandom_range functions.
This patch implements the System Verilog $urandom() and $urandom_range()
functions. There are no check to verify that $urandom_range is only given
unsigned arguments. If you give it a negative value the bit pattern will
be interpreted as a unsigned number.
2007-10-09 10:08:57 -07:00
Stephen Williams c7edace243 Unsized integers have minimum size
Fix the handling of expressions that have unsized integers and are
in self determined context. Unsized integers are generally assumed
to have at least 32bits.

Signed-off-by: Stephen Williams <[email protected]>
2007-10-08 19:58:49 -07:00
Stephen Williams 08028177fe Correct elaboration of network constants.
Constant propagation incorrectly elided an entire constant net node
if only the LSB of the driven vector was HiZ. This caused the entire
vector to look like HiZ. Also, the code generator for writing the
constant values missed bits.

Signed-off-by: Stephen Williams <[email protected]>
2007-10-05 20:31:51 -07:00
Stephen Williams 9ed8614131 Merge branch 'master' of [email protected]:git/verilog 2007-10-03 22:30:37 -07:00
Stephen Williams acdbe274f9 Fix signed ocmpare of negative numbers.
signed compare in proceedural code was comparing the absolute
value if both operands were negative. Wrong!

Signed-off-by: Stephen Williams <[email protected]>
2007-10-03 22:26:42 -07:00
Stephen Williams 5d750b7779 Optomize runtime using immediate compare
Implement compare-immediate instructions and generate code to use
these new instructions to improve runtime performance.

Signed-off-by: Stephen Williams <[email protected]>
2007-10-03 20:58:40 -07:00
Cary R d5fe5689e1 Command files can nest, -f is an alias for -c and better error messages.
This patch adds the ability to call command files from other command
files. There is currently a limit of 16 total levels deep (15 stored
plus the current file). -f is now an alias for -c for both the command
line and command files. The parser also reports errors when they occur
along with the file name and line number to aid in debugging problems.
2007-10-02 19:40:45 -07:00
Stephen Williams d587499276 test_width method for functions in expressions
In expressions, user defined functions have a clearly defined
width and the test_width expression needs to express that. Note
that the $signed/$unsigned functions are special and magical.

Signed-off-by: Stephen Williams <[email protected]>
2007-10-01 20:38:20 -07:00
Stephen Williams bbf3116945 Merge branch 'master' of [email protected]:git/verilog 2007-09-28 18:22:44 -07:00
Stephen Williams 5bb936a226 Fix addressing of variable words.
Variable word addresses are not to be adjusted by the bit select
of the vector direction. That is a holdover from when arrays were
stored as bit vectors.

Signed-off-by: Stephen Williams <[email protected]>
2007-09-28 18:22:17 -07:00
Cary R 3258b7726b Pass local scope precision from compiler to vvp/etc.
This patch adds ivl_scope_time_precision() to the compiler which can
be used to extract the local scope precision. tgt-stub and tgt-vvp
have been modified to use this new function and output a value that
is appropriate. The vvp runtime has been altered to use this new
data which is accessed with the vpip_time_precision_from_handle()
function. vpiTimePrecision uses this function to return the correct
precision.
2007-09-28 15:08:02 -07:00
Cary R d186f2da04 Ambiguous resolution needs to preserve the MSB for StL/etc. signals.
The MSB was not being preserved for L strength signals. This caused
undefined signals (x) to become defined (0).
2007-09-24 17:20:01 -07:00
Stephen Williams 14c0cfd3b1 bufif and nmos/pmos are strength aware
The outputs to bufif and nmos/pmos devices are always strength-aware,
so should have their outputs connected to a net8 device.

Signed-off-by: Stephen Williams <[email protected]>
2007-09-22 21:53:55 -07:00
Larry Doolittle a0cbd235d6 Fix gcc warnings
Fix gcc warnings in ivl_dlfcn.h.
2007-09-20 17:24:14 -07:00
Larry Doolittle bcc034f634 Compile time warnings
Fix compile time warnings detected by gccc 4.2.
2007-09-20 17:20:48 -07:00
Cary R 954579f250 Add min_typ_max to expressions.
This patch adds min_typ_max to expressions. Remember when using a
min_typ_max triplet in an expression they must be enclosed with
parenthesis (1364-2001 section 4.3 page 58).
2007-09-17 10:53:05 -07:00
Cary R 2e12dee658 Decimal constants can be undefined or high-z.
Add the ability for decimal constants to undefined or high-z.
2007-09-17 10:28:52 -07:00
Stephen Williams 3cbe4f076e Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2007-09-10 15:30:51 -07:00
yang yun ju 9d39b3a514 Access to modpaths via VPI
Add support for accessing the modpath nodes via PLI,
and add support for the vpi_set_delays and vpi_put_delays
functions to set the delays on those paths.

- GSoC 2007
2007-09-10 15:30:00 -07:00
Stephen Williams 9c99b002ba Resize vectors to mismatched ports
It is legal in Verilog to bind expressions to ports that do not
match the port width. Icarus Verilog needs to create the necessary
part selects to get the connections right.

Signed-off-by: Stephen Williams <[email protected]>
2007-09-09 21:14:52 -07:00
Cary R 8fe3cc5318 Add missing primitives and fix time units error in tgt-stub.
Add code to handle all the primitives currently defined and
fixed a power of ten error in the time units display (it is
either 10^{units} or 1e{units}, but not 10e{units}).
2007-09-06 18:53:05 -07:00
Cary R d43cda3def Add port checks for primitives.
This patch adds functionality to verify that primitives are given
an appropriate number of ports. For multiple output gates (but,
not, pulldown, pullup) it also reports that Icarus currently does
not support multiple outputs when more than one is given.
2007-09-06 18:50:02 -07:00
Cary R 7c852aa075 Add cmos/rcmos primitives.
This patch adds the cmos and rcmos primitives.
2007-09-06 18:46:22 -07:00
Stephen Williams 203cb0f730 Merge branch 'master' of [email protected]:git/verilog 2007-09-04 16:42:45 -07:00
Cary R b55e3c11dc mingw needs fseeko/ftello redefinitions in lxt_write.h
These redefinitions were in lxt2_write.h, but missing in lxt_write.h.
This patch adds them to lxt_write.h.
2007-09-04 16:32:52 -07:00
Stephen Williams 7290489e1a Merge branch 'master' of ssh://[email protected]/home/u/icarus/steve/git/verilog 2007-09-04 16:24:19 -07:00
Cary R 7bf4b64c0a Check that logic gates are not given null ports.
Logic gates do not handle null ports so check for this and
issue an error message when it happens.
2007-09-04 16:13:46 -07:00
Stephen Williams 083b9b6ee6 Handle repeat concatenation in continuous assign
When a repeat concatenation expression is translated to a netlist,
get the repeat expression right. This comes up when an elab_and_eval
elaboration contains a repeat concationation, and the expression is
ultimately turned into a netlist by expr_synth.

Signed-off-by: Stephen Williams <[email protected]>
2007-09-01 17:36:57 -07:00
Martin Whitaker 963b26283a Generate scopes are more like begin-end scopes
Apparently making generate scopes look like module instances
confuses some 3rd party tools that see this information in the
VCD dump.
2007-09-01 15:06:53 -07:00
Martin Whitaker 59af5d08b7 More portable encoding of vectors
Slight modification to the description of a vector vareable in the
declarations section for the convenience of 3rd party VCD viewers.
2007-09-01 15:00:53 -07:00
Stephen Williams 4af28c7526 Signed divide of 32bit values
Signed divide of 32bit values can overflow if done in a 32bit long
due to the truncation of sign bits. So use the large value algorithm
if the values are >= 31 bits (63 bits on 64bit machines).

Signed-off-by: Stephen Williams <[email protected]>
2007-09-01 14:38:57 -07:00
Cary R 4f6b47b345 Check that functions do not call invalid statements.
This patch adds checks to verify that functions do not invoke
statements that are invalid for them (#, @, wait, enable/call
tasks and non blocking assignment). For reference see section
10.3.4 of 1364-2001.
2007-08-30 20:41:45 -07:00
Cary R 3f6ea1d587 Make C style comments work in false/suppressed ifdef/etc. blocks.
C style comments were not recognized as comments in false or
suppressed sections of ifdef/etc. blocks. This prohibited an
unneeded endif/else/etc. from being commented out with this
style of comment.
2007-08-30 19:01:10 -07:00
Cary R 347ba8bc29 Comment out routines that pr1779647 made obsolete.
I decided not to delete these since we may at some point in time want
this functionality back. For now they are commented out with an
explanation so we know what is going on.
2007-08-30 19:00:07 -07:00
Cary R c7538386fc Start of simulation event needed to be run after initialization events.
This patch splits the end of compile and the start of simulation call
backs code into two different procedures. The end of compile events are
still executed at the same time they alway were. The start of simulation
events are now run after initialization.
2007-08-29 20:20:03 -07:00
Cary R fa1c0ae2a2 $finish() now stops at the end of the time step not immediately.
The event loop used to check for $finish at every iteration. This patch
alters this behavior to only check just before you advance to the next
time step. This allows events for the current time step to complete.
2007-08-29 20:07:55 -07:00
Cary R 81a45cdc5f Make vpi_put_value to a real accept an integer value and add diagnostic code.
Modified the code that deals with real variables to accept an integer
value when using vpi_put_value(). Also added some type of diagnostic
message for all switch defaults that have an assert(0) to indicate an
error condition, removed CVS comments and removed a small section of
unreachable code.
2007-08-29 20:02:12 -07:00
Cary R 23ce6c39ab Make vpi_put_value to a real accept an integer value and add diagnostic code.
Modified the code that deals with real variables to accept an integer
value when using vpi_put_value(). Also added some type of diagnostic
message for all switch defaults that have an assert(0) to indicate an
error condition, removed CVS comments and removed a small section of
unreachable code.
2007-08-29 19:50:07 -07:00
Cary R 3fda7e323a Relax the requirement on list of port declarations for implicit ports.
Previously list of port declarations were considered a complete
definition of the port. This caused problems for some, so this patch
allows implicitly defined ports (no wire/reg/etc.) to have net
declarations in the body.
2007-08-29 18:38:36 -07:00
Cary R 35df445db1 Initialize all range variables in the constructor to avoid false asserts.
This would have never been a problem with the actual circuit generated.
The problem was that the assert was checking values that had never been
set. The constructor now explicitly sets these values to zero and while
I was at it I added a couple more asserts.
2007-08-29 18:12:29 -07:00
Cary R b69c4c9a2c Fix range handling/checking and add a flag to allow deprecated port syntax.
This patch is rather large and fixes a couple of problems. The major
change is that instead of keeping all the range specifications in
a list that is later processed the information is now kept as
individual entries for the port and net definitions. This allows
easier checking for multiple definitions (pr1660028), more
detailed error messages and the ability to pass the now deprecated
style of a scalar I/O definition used with a vectored net definition.
These changes did require extra code to prevent a single definition
from setting the range values in more than on place.

When using the new ANSI-C style of port declarations (1364-2001 12.3.4
list_of_port_declarations) the compiler ensures that you do not
redeclare the port in the body (it is already completely defined).
This caught a few errors in the test suite (pr859 and sqrt32*).

The flag to disable the normal port checking and allow the deprecated
port syntax is -gno-io-range-error. This will print a warning for the
case of a scalar port with a vectored definition in the body. All
other cases are still considered an error.
2007-08-29 18:10:18 -07:00
Cary R d08817aec1 [PATCH] Search for include files relative to the current files path first.
This patch add the current files path to the start of the list used
when search for include files.
2007-08-29 17:45:55 -07:00
Cary R ca924639a8 [PATCH] Better error message when an endmodule is missing (nested modules).
This patch adds better checking for a missing endmodule or an attempt
to nest modules. A more descriptive message is printed and the location
of the original module definition is printed.
2007-08-28 17:49:34 -07:00
Stephen Williams 76b7346ee0 forgot to check it initialization calls
Signed-off-by: Stephen Williams <[email protected]>
2007-08-28 17:32:04 -07:00
Stephen Williams bef55d4426 Nets initialize with z value.
At time zero, nets (not variables) need to be initialized with z
instead of x.

Signed-off-by: Stephen Williams <[email protected]>
2007-08-28 16:56:01 -07:00
Stephen Williams 11ec505697 Logic gates can take part select inputs
It is possible for the compiler to generate logic gates that have
inputs from part select nodes. This implements the part select
input methods.

Signed-off-by: Stephen Williams <[email protected]>
2007-08-28 16:52:44 -07:00
Cary R 86e6817505 Fix missing warning when port is unsized.
This patch fixes an incorrect optimization that was skipping a
call to set the port width when there was no width (a scalar).
The problem with this is that since a (0,0) pair was not added
to the list, later when the width was define to (1,0) the checking
code did not have the (0,0) to tell that there was a mismatch in
the port size. Section 12.3.3 States that the two sizes shall be
identical, so yes this is an error even though it is very minor.
2007-08-17 11:48:47 -07:00
Cary R 15058a31b9 vpiFullName for real variables will now return the correct value.
This patch makes vpiFullName for real variables return the correct
value. A Scope reference was added to the base structure along with
the relevant code to support generating the full name. A couple of
memory leaks were plugged and some formatting fixed as well.
2007-08-17 11:40:01 -07:00
Cary R 6653202e91 Enhance vpi_handle_by_name to accept either a scope or a module.
It appears that other simulators allow the second argument to
vpi_handle_by_name to be either a scope or a module. Allowing
a module in addition to a scope significantly increases the
usability of this function.
2007-08-16 14:36:06 -07:00
Cary R 951f9f2bbf Add vpiType to the vpi_get_str() function.
vpi_get_str() can now return a reasonable value for most of the
types used in vvp. I'm not certain I got all of them, but they
are easy to add if any are missing. I also fixed a couple of
typos that I found while looking for all the different types.
2007-08-16 10:48:28 -07:00
Stephen Williams 30273a1172 Real value constants have width 1
Real value constants have width 1 in Icarus Verilog. This is not
the same as the output from $bitstoreal, which is *not* a real
valued expression but a logic vector that losslessly carries the
real value.

Also remove unused CVS markings.

Signed-off-by: Stephen Williams <[email protected]>
2007-08-15 22:01:59 -07:00
Cary R c71b9797ca Make %t with real values use specified width if given.
The %t format did not use the width specified when displaying
real values. It should now work the same as the integer version.
2007-08-15 13:39:28 -07:00
Cary R dd6a441312 [PATCH] Fixed the display of real values with the %t format.
Add a calculation to compute the required width for real values
when displayed with the %t formet.
2007-08-15 13:31:29 -07:00
Cary R 06c15862e8 Add the vpiFullName property to binary and string parameters.
This patch adds the missing vpiFullName property to binary and
string parameters (FYI real parameters are not currently supported
by the VPI interface).
2007-08-15 10:06:41 -07:00
Cary R 35e19ccbd3 Add a cast to remove a warning.
This patch adds a cast to get around the warning produced when the tf
size call back (int *) is placed into the vpi structure (PLI_INT32 *).
2007-08-15 10:04:50 -07:00
Cary R 239523b3c7 Implement the swrite* and sformat system tasks plus a few other fixes.
This patch implements the swrite* and sformat system tasks. It also
makes $simtime distinguishable from the other integer time tasks.
This was needed to get the correct time units when $simtime was given
as an argument to $swrite*. The string constant code was also modified
to allow a string to be returned as a vector (0/1 bit pattern).

Here are some more specifics about the swrite* changes.
1. They do not share formatting code with the other display functions,
   so they may/will produce different results.
2. All %{alpha} codes allow a width and justification. Others have been
   enhanced (%t allows the default width and precision to be overridden,
   time functions print with time formatting, better error checking and
   messages, etc.).
3. %u and %z formatting codes have been added. It is important to note
   that these two formats can produce embedded NULLs, since these
   functions are returning a string anything after the first NULL will
   not be reachable! memcpy is used instead of regular string processing
   where needed so that the original string will contain the total
   result. The size returned when the string is created is the true
   length.  A warning will be printed if a string with embedded NULLs is
   produced (strlen() does not match the true length).
4. Real numbers are printed with %g instead of %f.

Once this new formatting code has been evaluated we should incorporate
the changes/fixes into the formatting code for the other functions or
the other functions could be modified to use this new code. The true
string length is available so we should be able to work around the
embedded NULL problem.
2007-08-13 20:07:12 -07:00
Stephen Williams 268e2df011 Merge branch 'master' of [email protected]:git/verilog 2007-08-13 19:58:56 -07:00
Cary R 632685d830 Check that $timeformat is not given more than four arguments.
Add a check that $timeformat is not given more than four arguments.
2007-08-13 19:52:38 -07:00
Stephen Williams 9b807c78d3 Prepare for 20070812 snapshot 2007-08-12 20:27:38 -07:00
Stephen Williams 1942899a3f Fix return of net strength value.
The calculated return value for the calculated strength value of
a net was left dangling. This patch fixes that. See pr1770199 in
the regression test suite.

Signed-off-by: Stephen Williams <[email protected]>
2007-08-10 21:51:13 -07:00
Stephen Williams 5e385e901d Fix missing endif 2007-08-10 10:14:00 -07:00
Stephen Williams 3b94c122b7 Constant concat operands are self determined
distinguish between self-determined and value-preserving when
evaluating constants that are arguments to concatenations.

Signed-off-by: Stephen Williams <[email protected]>
2007-08-09 22:08:54 -07:00
Stephen Williams f46be09914 Initialize assignments of reals
Support initialization assignments of real value variables. In the
process, clean up the processing of real variable declarations in
the parser.

Signed-off-by: Stephen Williams <[email protected]>
2007-08-04 21:50:06 -07:00
Cary R 1aa4394d75 Check the random function seed type and a fix to handle time variables.
The standard states that the seed for the random functions should be
an integer/time variable or a register. This patch fixes the compiletf
routines to check for this. There is also a small patch to
vvp/vpi_signal.cc that removes an assert that was failing and replaces
it with appropriate code. The assert was verifying that the source was
not bigger than an integer. The problem with this is that a time
variable or register may be bigger than an integer. I altered the code
to remove the assert and copy only the lower (8 * sizeof integer) bits.
The potential overflow/loss of precision is not checked. This passes
the regression tests.
2007-07-25 21:36:06 -07:00
Stephen Williams 8dc23dad59 Delay compiletf until bindings are complete
Delat the compiletf calls until after all the label references
are resolved and link bindings are complete. Otherwise, there may
be dangling references.

Signed-off-by: Stephen Williams <[email protected]>
2007-07-24 18:24:24 -07:00
Cary R b23eb1b917 [PATCH] Add compiletf routine for deposit system task and fix string constants.
This patch adds a compiletf routine to the $deposit system task and
simplifies the calltf routine. It also patches the constant string code
to return an appropriate integer value when needed. A number of compiletf
routines that check for this can now be simplified since this (string
constants) no longer causes an assert in an integer environment.
2007-07-23 21:23:55 -07:00
Stephen Williams 824f29a7d2 Better errors for invalid scope path
Better handle cases where the scope part of a heirarchical name does
not match any existing scope, or where scope index expressions are
not correct.

Signed-off-by: Stephen Williams <[email protected]>
2007-07-22 21:55:35 -07:00
Stephen Williams a6bd1ff3ce Vector parts into reduction nets
In rare cases, the reduction logic nodes may get vector part inputs.
This patch adds support for vector parts entering a reduction node.

Signed-off-by: Stephen Williams <[email protected]>
2007-07-22 21:52:28 -07:00
Stephen Williams fa05344738 Parameter names in generate blocks from containing scopes.
Parameter names used in generate blocks can look in containing
scopes (but not past the containing module) for their definitions.
2007-07-21 17:47:37 -07:00
Martin Whitaker 42fe46a7db Elaborate memory references with non-zero bases.
This fixes r-value type references to memory words for memories
that have a non-zero base address. Elaborate the expression
needed to get the canonical word index.
2007-07-21 17:19:24 -07:00
Stephen Williams 3d51810f01 Merge branch 'master' of [email protected]:git/verilog 2007-07-20 19:35:22 -07:00
Stephen Williams dd5e34dc90 Invalid assertion on udp port count
The port input count assertion was triggering incorrectly. It was
comparing the count with the bytes instead of bits in a word.

Signed-off-by: Stephen Williams <[email protected]>
2007-07-20 19:31:27 -07:00
Cary R a359ec45f7 Pass the finish and stop system task argument correctly.
The argument passed to $finish and $stop is not currently used, but it
is now passed down to the functions that may someday do something
useful with it (schedule_finish() and schedule_stop() in vvp/schedule.cc).
2007-07-20 14:01:35 -07:00
Cary R a024eaead2 Add missing probabilistic functions and compiletf routines.
Add the missing probabilistic functions and add compiletf routines
for all the functions. The original calltf routines have been
modified as appropriate. The base functions are straight copies
from the standard. I have visually verified the curves with 5,000
points and they look correct.
2007-07-20 13:54:49 -07:00
Cary R 1aa6fc3f7a [PATCH] Update vpiFinish arguments to be in correct range.
Even though vpiFinish does not currently do anything with it's
argument I thought it would be best to have them all be in the
correct range [0, 1, 2], so they have been updated as appropriate.
2007-07-19 17:35:40 -07:00
Cary R e546a9d5c8 Update the files to use vpi_control vs vpi_sim_control.
vpi_sim_control is no longer part of the standard, so update the code to
use the standard function (vpi_control).
2007-07-19 17:29:05 -07:00
Stephen Williams 58cb5a668b Real value constants in vector declaration
Handle real valued expressions in vector declarations. Also clean
up the handling of vector declaration expressions.

Signed-off-by: Stephen Williams <[email protected]>
2007-07-17 18:07:34 -07:00
Stephen Williams 6b0c62c9c4 Minor improvements to $bits implementation
Signed-off-by: Stephen Williams <[email protected]>
2007-07-17 18:05:48 -07:00
Stephen Williams 7aa323bcbf Handle nil parameter overrides
Nil parameter overrides can turn up in positional paramter override
lists, where items are intentionally skipped.

Signed-off-by: Stephen Williams <[email protected]>
2007-07-14 17:11:14 -07:00
Stephen Williams b327b86e4a Propagate real values properly
Be careful to include bitwise differences in double values, because
it is the bit pattern we are passing aroung, not the arithmetic value.

Signed-off-by: Stephen Williams <[email protected]>
2007-07-13 18:42:35 -07:00
Cary R acddb99305 Document the predefined __ICARUS__ macro 2007-07-12 19:05:09 -07:00
Stephen Williams 32ecd260f0 Merge branch 'master' of [email protected]:git/verilog 2007-07-11 21:43:33 -07:00
Stephen Williams 7132b8ff6b Start runtime trace aids
The runtime is a vvp runtime engine debug aid that allows for
detailed dump into a debug log. The trace is enabled by setting
the VVP_DEBUG variable and activating specific debug messages
in the vvp source.

Signed-off-by: Stephen Williams <[email protected]>
2007-07-11 21:38:56 -07:00
Stephen Williams b54ef4f585 Variable drivers propogate initial values.
Make varable drivers (reg vectors and real) propagate their initial
values using a special init scheduler queue. This causes the net to
be loaded with reasonable initial values.

Signed-off-by: Stephen Williams <[email protected]>
2007-07-11 21:31:09 -07:00
Larry Doolittle 371c5d932d Correct wrong or misleading comments. 2007-07-06 12:46:32 -07:00
Stephen Williams a72977a7ed Bit select of array word
fix support for bit select of array word in behavioral expressions.
2007-07-03 20:17:43 -07:00
Stephen Williams e75e7131ac Fix signed compare with minus values
If the operands were negative, and not equal, the lt flag
would be set incorrectly.

Signed-off-by: Stephen Williams <[email protected]>
2007-07-02 21:33:05 -07:00
Stephen Williams 018f1a6e7f Handle indexed part select in continuous assign.
Non-constant indexed part select in continuous assignment generates
a select node with the correct width. In the process factor out and
share some of the part select calculations with expr part select
handling methods.

Signed-off-by: Stephen Williams <[email protected]>
2007-07-02 20:53:02 -07:00
Stephen Williams 88dea0c318 Remove restriction on size of constants
Constant strings are now formed in dynamically allocated memory
instead of a fixed array.

Signed-off-by: Stephen Williams <[email protected]>
2007-06-30 20:27:08 -07:00
Stephen Williams 21d6fb6bc6 Fix runtime crash dumping VCD
Words of net arrays were incorrectly added to the scope. They should
only be attached to the array, and accessed as a word of the array.


Signed-off-by: Stephen Williams <[email protected]>
2007-06-30 09:34:02 -07:00
Stephen Williams d7c3a32b06 Fix code generation for real expressions
Real value are vector width of 1, fix real literal to reflect this.
fix leaking real registers in code generation for function arguments.
Load of signal should handle conversion from real to vector. Function
arguments, type vector passed a real value, are an example where this
comes up.

Signed-off-by: Stephen Williams <[email protected]>
2007-06-29 21:10:37 -07:00
Stephen Williams b525a63f50 Do not process back-slash escapes twice.
Backslash-escapes are processed early, during elaboration, so that
escaped characters show up in all places with the calculated value.
This means the $display formatting will get processed strings and
should not process back-slashes again.

Signed-off-by: Stephen Williams <[email protected]>
2007-06-28 18:07:22 -07:00
Stephen Williams 4cf9447ad9 Merge branch 'master' of [email protected]:git/verilog 2007-06-27 22:17:46 -07:00
Stephen Williams 845e74c30e Evaluate parameter expressions losslessly
Make sure parameter expressions are evaluated losslessly, as if
the l-value is unsigned and thus virtually infinite.
2007-06-27 22:05:36 -07:00
Stephen Williams a6f898a702 Careful not to lose bits parameter add expression
Parameter expressions that do not otherwise have a size should
evaluate expressions losslessly, expanding as necessary to prevent
overflow of data.

Signed-off-by: Stephen Williams <[email protected]>
2007-06-27 21:51:31 -07:00
Stephen Williams 59a43ab2ce Do not match scopes in ident expressions
Identifiers in expressions cannot be scope names, even
though the special case of a simple system task argument
expression allows it.
2007-06-25 20:33:40 -07:00
Stephen Williams ed698deeaa Add support for collapsed/aliased arrays.
Arrays of nets that have all their words collapsed together can become
a collapsed array as a whole. Add support for this case in the vvp code
generator and runtime.
2007-06-24 18:17:37 -07:00
Stephen Williams 396ffd1cdd Add support for conditional generate. In the process, fix bugs
related to generate used multiple times by multiple scopes causing
spurious generation results.


Signed-off-by: Stephen Williams <[email protected]>
2007-06-21 19:04:48 -07:00
Stephen Williams 9d2dd782c0 Get offsets right for non-zero and reversed part selects.
Signed-off-by: Stephen Williams <[email protected]>
2007-06-15 16:59:24 -07:00
254 changed files with 17271 additions and 19095 deletions
+2 -2
View File
@@ -72,11 +72,11 @@ reporting problems with. However, if you clearly explain what is right
and wrong about the generated netlist, I will probably be able to fix
the problem. It may take a few iterations.
In this case, if possible include not only the sample verilog program,
In this case, if possible include not only the sample Verilog program,
but the generated netlist file(s) and a clear indication of what went
wrong. If it is not clear to me, I will ask for clarification.
* The Output is Correct, But Less Then Ideal
* The Output is Correct, But Less Than Ideal
If the output is strictly correct, but just not good enough for
practical use, I would like to know. These sorts of problems are
+3 -2
View File
@@ -23,8 +23,9 @@
# include "config.h"
# include "HName.h"
# include <iostream>
# include <string.h>
# include <stdlib.h>
# include <cstring>
# include <cstdlib>
# include <climits>
#ifdef HAVE_MALLOC_H
# include <malloc.h>
#endif
+1 -1
View File
@@ -32,7 +32,7 @@ using namespace std;
/*
* This class represents a component of a Verilog hierarchical name. A
* hierarchical component contains a name string (prepresented here
* hierarchical component contains a name string (represented here
* with a perm_string) and an optional signed number. This signed
* number is used if the scope is part of an array, for example an
* array of module instances or a loop generated scope.
+4 -25
View File
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: LineInfo.cc,v 1.4 2003/01/17 05:49:03 steve Exp $"
#endif
# include "config.h"
@@ -26,7 +23,7 @@
# include <sstream>
LineInfo::LineInfo()
: file_(0), lineno_(0)
: lineno_(0)
{
}
@@ -34,10 +31,10 @@ LineInfo::~LineInfo()
{
}
string LineInfo::get_line() const
string LineInfo::get_fileline() const
{
ostringstream buf;
buf << (file_? file_ : "") << ":" << lineno_;
buf << (file_.str()? file_.str() : "") << ":" << lineno_;
string res = buf.str();
return res;
@@ -49,7 +46,7 @@ void LineInfo::set_line(const LineInfo&that)
lineno_ = that.lineno_;
}
void LineInfo::set_file(const char*f)
void LineInfo::set_file(perm_string f)
{
file_ = f;
}
@@ -58,21 +55,3 @@ void LineInfo::set_lineno(unsigned n)
{
lineno_ = n;
}
/*
* $Log: LineInfo.cc,v $
* Revision 1.4 2003/01/17 05:49:03 steve
* Use stringstream in place of sprintf.
*
* Revision 1.3 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.2 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.1 2000/11/30 17:31:42 steve
* Change LineInfo to store const C strings.
*
*/
+9 -27
View File
@@ -18,10 +18,8 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: LineInfo.h,v 1.8 2005/06/14 19:13:43 steve Exp $"
#endif
# include "StringHeap.h"
# include <string>
using namespace std;
@@ -40,36 +38,20 @@ class LineInfo {
LineInfo();
~LineInfo();
string get_line() const;
// Get a fully formatted file/lineno
string get_fileline() const;
// Set the file/line fro another LineInfo object.
void set_line(const LineInfo&that);
void set_file(const char*f);
// Access parts of LineInfo data
void set_file(perm_string f);
void set_lineno(unsigned n);
perm_string get_file() const { return file_; }
unsigned get_lineno() const { return lineno_; }
private:
const char* file_;
perm_string file_;
unsigned lineno_;
};
/*
* $Log: LineInfo.h,v $
* Revision 1.8 2005/06/14 19:13:43 steve
* gcc3/4 compile errors.
*
* Revision 1.7 2003/01/17 05:49:03 steve
* Use stringstream in place of sprintf.
*
* Revision 1.6 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.5 2000/11/30 17:31:42 steve
* Change LineInfo to store const C strings.
*
* Revision 1.4 2000/02/23 02:56:53 steve
* Macintosh compilers do not support ident.
*
* Revision 1.3 1999/02/15 02:06:15 steve
* Elaborate gate ranges.
*/
#endif
+4 -6
View File
@@ -30,6 +30,7 @@ VERSION = 0.9.devel
prefix = @prefix@
exec_prefix = @exec_prefix@
srcdir = @srcdir@
datarootdir = @datarootdir@
SUBDIRS = @subdirs@
@@ -40,8 +41,6 @@ libdir = @libdir@
includedir = @includedir@
mandir = @mandir@
libdir64 = @libdir64@
dllib=@DLLIB@
CC = @CC@
@@ -112,7 +111,7 @@ parse.o parse_misc.o pform.o pform_dump.o pform_types.o \
set_width.o symbol_search.o sync.o sys_funcs.o \
verinum.o verireal.o target.o targets.o \
Attrib.o HName.o LineInfo.o Module.o PDelays.o PEvent.o \
PExpr.o PGate.o PGenerate.o PSpec.o \
PExpr.o PGate.o PGenerate.o PScope.o PSpec.o \
PTask.o PUdp.o PFunction.o PWire.o Statement.o StringHeap.o \
$(FF) $(TT)
@@ -146,8 +145,6 @@ iverilog-vpi: iverilog-vpi.sh
-e 's;@IVCXX@;$(CXX);' \
-e 's;@IVCFLAGS@;$(CXXFLAGS);' \
-e 's;@INCLUDEDIR@;@includedir@;' \
-e 's;@LIBDIR64@;@libdir64@;' \
-e 's;@VPIDIR1@;@vpidir1@;' -e 's;@VPIDIR2@;@vpidir2@;' \
-e 's;@LIBDIR@;@libdir@;' $< > $@
chmod +x $@
endif
@@ -262,7 +259,7 @@ endif
installdirs: mkinstalldirs
$(srcdir)/mkinstalldirs $(bindir) $(includedir) $(libdir)/ivl \
$(mandir) $(mandir)/man1
$(libdir)/ivl/include $(mandir) $(mandir)/man1
uninstall:
for dir in $(SUBDIRS); do (cd $$dir ; $(MAKE) $@); done
@@ -270,6 +267,7 @@ uninstall:
do (cd $$dir ; $(MAKE) $@); done
for f in xnf.conf xnf-s.conf ivl@EXEEXT@; \
do rm -f $(libdir)/ivl/$$f; done
-rmdir $(libdir)/ivl/include
-rmdir $(libdir)/ivl
for f in verilog iverilog-vpi gverilog@EXEEXT@; \
do rm -f $(bindir)/$$f; done
+3 -129
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
* Copyright (c) 1998-2008 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: Module.cc,v 1.27 2007/05/24 04:07:11 steve Exp $"
#endif
# include "config.h"
@@ -29,7 +26,7 @@
/* n is a permallocated string. */
Module::Module(perm_string n)
: name_(n)
: PScope(n, 0)
{
library_flag = false;
default_nettype = NetNet::NONE;
@@ -54,21 +51,6 @@ void Module::add_function(perm_string name, PFunction *func)
funcs_[name] = func;
}
PWire* Module::add_wire(PWire*wire)
{
PWire*&ep = wires_[wire->path()];
if (ep) return ep;
assert(ep == 0);
ep = wire;
return wire;
}
void Module::add_behavior(PProcess*b)
{
behaviors_.push_back(b);
}
unsigned Module::port_count() const
{
return ports.count();
@@ -92,7 +74,7 @@ const svector<PEIdent*>& Module::get_port(unsigned idx) const
unsigned Module::find_port(const char*name) const
{
assert(name != "");
assert(name != 0);
for (unsigned idx = 0 ; idx < ports.count() ; idx += 1) {
if (ports[idx] == 0) {
/* It is possible to have undeclared ports. These
@@ -111,15 +93,6 @@ unsigned Module::find_port(const char*name) const
}
PWire* Module::get_wire(const pform_name_t&name) const
{
map<pform_name_t,PWire*>::const_iterator obj = wires_.find(name);
if (obj == wires_.end())
return 0;
else
return (*obj).second;
}
PGate* Module::get_gate(perm_string name)
{
for (list<PGate*>::iterator cur = gates_.begin()
@@ -138,102 +111,3 @@ const list<PGate*>& Module::get_gates() const
return gates_;
}
const list<PProcess*>& Module::get_behaviors() const
{
return behaviors_;
}
/*
* $Log: Module.cc,v $
* Revision 1.27 2007/05/24 04:07:11 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.26 2007/04/19 02:52:53 steve
* Add support for -v flag in command file.
*
* Revision 1.25 2004/10/04 01:10:51 steve
* Clean up spurious trailing white space.
*
* Revision 1.24 2004/06/13 04:56:53 steve
* Add support for the default_nettype directive.
*
* Revision 1.23 2004/02/20 06:22:56 steve
* parameter keys are per_strings.
*
* Revision 1.22 2004/02/18 17:11:54 steve
* Use perm_strings for named langiage items.
*
* Revision 1.21 2003/04/02 03:00:14 steve
* Cope with empty module ports while binding by name.
*
* Revision 1.20 2003/03/06 04:37:12 steve
* lex_strings.add module names earlier.
*
* Revision 1.19 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.18 2002/05/19 23:37:28 steve
* Parse port_declaration_lists from the 2001 Standard.
*
* Revision 1.17 2001/12/03 04:47:14 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
* Revision 1.16 2001/10/20 05:21:51 steve
* Scope/module names are char* instead of string.
*
* Revision 1.15 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.14 2000/11/15 20:31:05 steve
* Fix warning about temporaries.
*
* Revision 1.13 2000/11/05 06:05:59 steve
* Handle connectsion to internally unconnected modules (PR#38)
*
* Revision 1.12 2000/05/16 04:05:15 steve
* Module ports are really special PEIdent
* expressions, because a name can be used
* many places in the port list.
*
* Revision 1.11 2000/03/12 17:09:40 steve
* Support localparam.
*
* Revision 1.10 2000/02/23 02:56:53 steve
* Macintosh compilers do not support ident.
*
* Revision 1.9 2000/01/09 20:37:57 steve
* Careful with wires connected to multiple ports.
*
* Revision 1.8 1999/12/11 05:45:41 steve
* Fix support for attaching attributes to primitive gates.
*
* Revision 1.7 1999/09/17 02:06:25 steve
* Handle unconnected module ports.
*
* Revision 1.6 1999/08/04 02:13:02 steve
* Elaborate module ports that are concatenations of
* module signals.
*
* Revision 1.5 1999/08/03 04:14:49 steve
* Parse into pform arbitrarily complex module
* port declarations.
*
* Revision 1.4 1999/07/31 19:14:47 steve
* Add functions up to elaboration (Ed Carter)
*
* Revision 1.3 1999/07/03 02:12:51 steve
* Elaborate user defined tasks.
*
* Revision 1.2 1999/06/17 05:34:42 steve
* Clean up interface of the PWire class,
* Properly match wire ranges.
*
* Revision 1.1 1998/11/03 23:28:51 steve
* Introduce verilog to CVS.
*
*/
+9 -47
View File
@@ -1,7 +1,7 @@
#ifndef __Module_H
#define __Module_H
/*
* Copyright (c) 1998-2004 Stephen Williams ([email protected])
* Copyright (c) 1998-2008 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: Module.h,v 1.43 2007/05/24 04:07:11 steve Exp $"
#endif
# include <list>
# include <map>
@@ -28,10 +26,10 @@
# include "StringHeap.h"
# include "HName.h"
# include "named.h"
# include "PScope.h"
# include "LineInfo.h"
# include "netlist.h"
# include "pform_types.h"
class PEvent;
class PExpr;
class PEIdent;
class PGate;
@@ -50,7 +48,7 @@ class NetScope;
* therefore the handle for grasping the described circuit.
*/
class Module : public LineInfo {
class Module : public PScope, public LineInfo {
/* The module ports are in general a vector of port_t
objects. Each port has a name and an ordered list of
@@ -113,9 +111,6 @@ class Module : public LineInfo {
named array of PEident pointers. */
svector<port_t*> ports;
/* Keep a table of named events declared in the module. */
map<perm_string,PEvent*>events;
map<perm_string,PExpr*> attributes;
/* These are the timescale for this module. The default is
@@ -132,16 +127,10 @@ class Module : public LineInfo {
list<PSpecPath*> specify_paths;
perm_string mod_name() const { return name_; }
// The mod_name() is the name of the module type.
perm_string mod_name() const { return pscope_name(); }
void add_gate(PGate*gate);
// The add_wire method adds a wire by name, but only if the
// wire name doesn't already exist. Either way, the result is
// the existing wire or the pointer passed in.
PWire* add_wire(PWire*wire);
void add_behavior(PProcess*behave);
void add_task(perm_string name, PTask*def);
void add_function(perm_string name, PFunction*def);
@@ -149,13 +138,9 @@ class Module : public LineInfo {
const svector<PEIdent*>& get_port(unsigned idx) const;
unsigned find_port(const char*name) const;
// Find a wire by name. This is used for connecting gates to
// existing wires, etc.
PWire* get_wire(const pform_name_t&name) const;
PGate* get_gate(perm_string name);
const list<PGate*>& get_gates() const;
const list<PProcess*>& get_behaviors() const;
void dump(ostream&out) const;
bool elaborate(Design*, NetScope*scope) const;
@@ -166,39 +151,16 @@ class Module : public LineInfo {
bool elaborate_sig(Design*, NetScope*scope) const;
private:
perm_string name_;
map<pform_name_t,PWire*> wires_;
list<PGate*> gates_;
list<PProcess*> behaviors_;
map<perm_string,PTask*> tasks_;
map<perm_string,PFunction*> funcs_;
static void elaborate_parm_item_(perm_string name, const param_expr_t&cur,
Design*des, NetScope*scope);
private: // Not implemented
Module(const Module&);
Module& operator= (const Module&);
};
/*
* $Log: Module.h,v $
* Revision 1.43 2007/05/24 04:07:11 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.42 2007/04/19 02:52:53 steve
* Add support for -v flag in command file.
*
* Revision 1.41 2006/09/23 04:57:19 steve
* Basic support for specify timing.
*
* Revision 1.40 2006/04/10 00:37:42 steve
* Add support for generate loops w/ wires and gates.
*
* Revision 1.39 2006/03/30 01:49:07 steve
* Fix instance arrays indexed by overridden parameters.
*
* Revision 1.38 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*/
#endif
+4 -69
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1999 Stephen Williams ([email protected])
* Copyright (c) 1999-2008 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PDelays.cc,v 1.15 2006/07/08 21:48:46 steve Exp $"
#endif
# include "config.h"
@@ -27,6 +24,7 @@
# include "PDelays.h"
# include "PExpr.h"
# include "verinum.h"
# include "netmisc.h"
PDelays::PDelays()
{
@@ -66,10 +64,7 @@ static NetExpr*calculate_val(Design*des, NetScope*scope, const PExpr*expr)
{
NetExpr*dex = expr->elaborate_expr(des, scope, -1, false);
if (NetExpr*tmp = dex->eval_tree()) {
delete dex;
dex = tmp;
}
eval_expr(dex);
/* If the delay expression is a real constant or vector
constant, then evaluate it, scale it to the local time
@@ -116,7 +111,7 @@ static NetExpr* make_delay_nets(Design*des, NetExpr*expr)
NetNet*sig = expr->synthesize(des);
if (sig == 0) {
cerr << expr->get_line() << ": error: Expression " << *expr
cerr << expr->get_fileline() << ": error: Expression " << *expr
<< " is not suitable for delay expression." << endl;
return 0;
}
@@ -166,63 +161,3 @@ void PDelays::eval_delays(Design*des, NetScope*scope,
decay_time = 0;
}
}
/*
* $Log: PDelays.cc,v $
* Revision 1.15 2006/07/08 21:48:46 steve
* Handle real valued literals in net contexts.
*
* Revision 1.14 2006/06/02 04:48:49 steve
* Make elaborate_expr methods aware of the width that the context
* requires of it. In the process, fix sizing of the width of unary
* minus is context determined sizes.
*
* Revision 1.13 2006/01/03 05:22:14 steve
* Handle complex net node delays.
*
* Revision 1.12 2006/01/02 05:33:19 steve
* Node delays can be more general expressions in structural contexts.
*
* Revision 1.11 2003/06/21 01:21:42 steve
* Harmless fixup of warnings.
*
* Revision 1.10 2003/02/08 19:49:21 steve
* Calculate delay statement delays using elaborated
* expressions instead of pre-elaborated expression
* trees.
*
* Remove the eval_pexpr methods from PExpr.
*
* Revision 1.9 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.8 2001/12/29 20:19:31 steve
* Do not delete delay expressions of UDP instances.
*
* Revision 1.7 2001/11/22 06:20:59 steve
* Use NetScope instead of string for scope path.
*
* Revision 1.6 2001/11/07 04:01:59 steve
* eval_const uses scope instead of a string path.
*
* Revision 1.5 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.4 2001/01/20 02:15:50 steve
* apologize for not supporting non-constant delays.
*
* Revision 1.3 2001/01/14 23:04:55 steve
* Generalize the evaluation of floating point delays, and
* get it working with delay assignment statements.
*
* Allow parameters to be referenced by hierarchical name.
*
* Revision 1.2 2000/02/23 02:56:53 steve
* Macintosh compilers do not support ident.
*
* Revision 1.1 1999/09/04 19:11:46 steve
* Add support for delayed non-blocking assignments.
*
*/
+3 -158
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1998-1999 Stephen Williams <[email protected]>
* Copyright (c) 1998-2007 Stephen Williams <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PExpr.cc,v 1.39 2007/05/24 04:07:11 steve Exp $"
#endif
# include "config.h"
@@ -48,14 +45,14 @@ bool PExpr::is_constant(Module*) const
NetNet* PExpr::elaborate_lnet(Design*des, NetScope*, bool) const
{
cerr << get_line() << ": error: expression not valid in assign l-value: "
cerr << get_fileline() << ": error: expression not valid in assign l-value: "
<< *this << endl;
return 0;
}
NetNet* PExpr::elaborate_bi_net(Design*des, NetScope*) const
{
cerr << get_line() << ": error: "
cerr << get_fileline() << ": error: "
<< "expression not valid as argument to inout port: "
<< *this << endl;
return 0;
@@ -298,155 +295,3 @@ bool PEUnary::is_constant(Module*m) const
return expr_->is_constant(m);
}
/*
* $Log: PExpr.cc,v $
* Revision 1.39 2007/05/24 04:07:11 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.38 2006/10/30 05:44:49 steve
* Expression widths with unsized literals are pseudo-infinite width.
*
* Revision 1.37 2005/10/04 04:09:25 steve
* Add support for indexed select attached to parameters.
*
* Revision 1.36 2005/08/06 17:58:16 steve
* Implement bi-directional part selects.
*
* Revision 1.35 2004/10/04 01:10:51 steve
* Clean up spurious trailing white space.
*
* Revision 1.34 2004/02/20 06:22:56 steve
* parameter keys are per_strings.
*
* Revision 1.33 2003/01/27 05:09:17 steve
* Spelling fixes.
*
* Revision 1.32 2002/11/09 19:20:48 steve
* Port expressions for output ports are lnets, not nets.
*
* Revision 1.31 2002/08/19 02:39:16 steve
* Support parameters with defined ranges.
*
* Revision 1.30 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.29 2001/12/30 21:32:03 steve
* Support elaborate_net for PEString objects.
*
* Revision 1.28 2001/12/03 04:47:14 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
* Revision 1.27 2001/11/08 05:15:50 steve
* Remove string paths from PExpr elaboration.
*
* Revision 1.26 2001/11/07 04:26:46 steve
* elaborate_lnet uses scope instead of string path.
*
* Revision 1.25 2001/11/06 06:11:55 steve
* Support more real arithmetic in delay constants.
*
* Revision 1.24 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.23 2001/01/14 23:04:55 steve
* Generalize the evaluation of floating point delays, and
* get it working with delay assignment statements.
*
* Allow parameters to be referenced by hierarchical name.
*
* Revision 1.22 2001/01/12 04:31:27 steve
* Handle error idents in constants not in any scope (PR#97)
*
* Revision 1.21 2000/12/16 19:03:30 steve
* Evaluate <= and ?: in parameter expressions (PR#81)
*
* Revision 1.20 2000/12/10 22:01:35 steve
* Support decimal constants in behavioral delays.
*
* Revision 1.19 2000/06/30 15:50:20 steve
* Allow unary operators in constant expressions.
*
* Revision 1.18 2000/05/07 04:37:55 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.17 2000/05/04 03:37:58 steve
* Add infrastructure for system functions, move
* $time to that structure and add $random.
*
* Revision 1.16 2000/04/12 04:23:57 steve
* Named events really should be expressed with PEIdent
* objects in the pform,
*
* Handle named events within the mix of net events
* and edges. As a unified lot they get caught together.
* wait statements are broken into more complex statements
* that include a conditional.
*
* Do not generate NetPEvent or NetNEvent objects in
* elaboration. NetEvent, NetEvWait and NetEvProbe
* take over those functions in the netlist.
*
* Revision 1.15 2000/04/01 19:31:57 steve
* Named events as far as the pform.
*
* Revision 1.14 2000/03/12 18:22:11 steve
* Binary and unary operators in parameter expressions.
*
* Revision 1.13 2000/02/23 02:56:53 steve
* Macintosh compilers do not support ident.
*
* Revision 1.12 1999/12/31 17:38:37 steve
* Standardize some of the error messages.
*
* Revision 1.11 1999/10/31 04:11:27 steve
* Add to netlist links pin name and instance number,
* and arrange in vvm for pin connections by name
* and instance number.
*
* Revision 1.10 1999/09/25 02:57:29 steve
* Parse system function calls.
*
* Revision 1.9 1999/09/16 04:18:15 steve
* elaborate concatenation repeats.
*
* Revision 1.8 1999/09/15 04:17:52 steve
* separate assign lval elaboration for error checking.
*
* Revision 1.7 1999/07/22 02:05:20 steve
* is_constant method for PEConcat.
*
* Revision 1.6 1999/07/17 19:50:59 steve
* netlist support for ternary operator.
*
* Revision 1.5 1999/06/16 03:13:29 steve
* More syntax parse with sorry stubs.
*
* Revision 1.4 1999/06/10 04:03:52 steve
* Add support for the Ternary operator,
* Add support for repeat concatenation,
* Correct some seg faults cause by elaboration
* errors,
* Parse the casex anc casez statements.
*
* Revision 1.3 1999/05/16 05:08:42 steve
* Redo constant expression detection to happen
* after parsing.
*
* Parse more operators and expressions.
*
* Revision 1.2 1998/11/11 00:01:51 steve
* Check net ranges in declarations.
*
* Revision 1.1 1998/11/03 23:28:53 steve
* Introduce verilog to CVS.
*
*/
+71 -168
View File
@@ -1,7 +1,7 @@
#ifndef __PExpr_H
#define __PExpr_H
/*
* Copyright (c) 1998-2000 Stephen Williams <[email protected]>
* Copyright (c) 1998-2008 Stephen Williams <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PExpr.h,v 1.90 2007/06/04 19:14:06 steve Exp $"
#endif
# include <string>
# include <vector>
@@ -79,9 +76,15 @@ class PExpr : public LineInfo {
// Procedural elaboration of the expression. The expr_width is
// the width of the context of the expression (i.e. the
// l-value width of an assignment) or -1 if the expression is
// self-determinted. The sys_task_arg flag is true if
// expressions are allowed to be incomplete.
// l-value width of an assignment),
//
// ... or -1 if the expression is self-determined. or
// ... or -2 if the expression is losslessly
// self-determined. This can happen in situations where the
// result is going to a pseudo-infinitely wide context.
//
// The sys_task_arg flag is true if expressions are allowed to
// be incomplete.
virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
int expr_width, bool sys_task_arg) const;
@@ -116,7 +119,7 @@ class PExpr : public LineInfo {
// Expressions that can be in the l-value of procedural
// assignments can be elaborated with this method. If the
// is_force flag is true, then the set of valid l-value types
// is slightly modified to accomodate the Verilog force
// is slightly modified to accommodate the Verilog force
// statement
virtual NetAssign_* elaborate_lval(Design*des,
NetScope*scope,
@@ -252,7 +255,7 @@ class PEIdent : public PExpr {
explicit PEIdent(const pform_name_t&);
~PEIdent();
// Add another name to the string of heirarchy that is the
// Add another name to the string of hierarchy that is the
// current identifier.
void append_name(perm_string);
@@ -305,8 +308,8 @@ class PEIdent : public PExpr {
private:
NetAssign_*elaborate_lval_net_word_(Design*, NetScope*, NetNet*) const;
bool elaborate_lval_net_part_(Design*, NetScope*, NetAssign_*) const;
bool elaborate_lval_net_idx_up_(Design*, NetScope*, NetAssign_*) const;
bool elaborate_lval_net_idx_do_(Design*, NetScope*, NetAssign_*) const;
bool elaborate_lval_net_idx_(Design*, NetScope*, NetAssign_*,
index_component_t::ctype_t) const;
private:
NetExpr*elaborate_expr_param(Design*des,
@@ -352,6 +355,20 @@ class PEIdent : public PExpr {
Link::strength_t drive0,
Link::strength_t drive1) const;
NetNet* elaborate_net_net_(Design*des, NetScope*scope,
NetNet*sig, unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
NetNet* elaborate_net_net_idx_up_(Design*des, NetScope*scope,
NetNet*sig, unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
NetNet* elaborate_net_bitmux_(Design*des, NetScope*scope,
NetNet*sig,
const NetExpr* rise,
@@ -469,6 +486,32 @@ class PEUnary : public PExpr {
virtual bool is_constant(Module*) const;
private:
NetNet* elab_net_uminus_const_logic_(Design*des, NetScope*scope,
NetEConst*expr,
unsigned width,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
NetNet* elab_net_uminus_const_real_(Design*des, NetScope*scope,
NetECReal*expr,
unsigned width,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
NetNet* elab_net_unary_real_(Design*des, NetScope*scope,
NetExpr*expr,
unsigned width,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
private:
char op_;
PExpr*expr_;
@@ -508,6 +551,8 @@ class PEBinary : public PExpr {
NetEBinary*elaborate_expr_base_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;
NetEBinary*elaborate_eval_expr_base_(Design*, NetExpr*lp, NetExpr*rp, int use_wid) const;
static void suppress_operand_sign_if_needed_(NetExpr*lp, NetExpr*rp);
private:
NetNet* elaborate_net_add_(Design*des, NetScope*scope,
unsigned lwidth,
@@ -544,6 +589,11 @@ class PEBinary : public PExpr {
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay) const;
NetNet* elaborate_net_pow_(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
const NetExpr* fall,
const NetExpr* decay) const;
NetNet* elaborate_net_shift_(Design*des, NetScope*scope,
unsigned lwidth,
const NetExpr* rise,
@@ -552,7 +602,7 @@ class PEBinary : public PExpr {
};
/*
* Here are a few specilized classes for handling specific binary
* Here are a few specialized classes for handling specific binary
* operators.
*/
class PEBComp : public PEBinary {
@@ -622,7 +672,7 @@ class PETernary : public PExpr {
class PECallFunction : public PExpr {
public:
explicit PECallFunction(const pform_name_t&n, const svector<PExpr *> &parms);
// Call of system function (name is not heirarchical)
// Call of system function (name is not hierarchical)
explicit PECallFunction(perm_string n, const svector<PExpr *> &parms);
explicit PECallFunction(perm_string n);
~PECallFunction();
@@ -639,13 +689,17 @@ class PECallFunction : public PExpr {
virtual NetExpr*elaborate_expr(Design*des, NetScope*scope,
int expr_wid, bool sys_task_arg) const;
virtual unsigned test_width(Design*des, NetScope*scope,
unsigned min, unsigned lval,
bool&unsized_flag) const;
private:
pform_name_t path_;
svector<PExpr *> parms_;
bool check_call_matches_definition_(Design*des, NetScope*dscope) const;
NetExpr* elaborate_sfunc_(Design*des, NetScope*scope) const;
NetExpr* elaborate_sfunc_(Design*des, NetScope*scope, int expr_wid) const;
NetNet* elaborate_net_sfunc_(Design*des, NetScope*scope,
unsigned width,
const NetExpr* rise,
@@ -653,160 +707,9 @@ class PECallFunction : public PExpr {
const NetExpr* decay,
Link::strength_t drive0,
Link::strength_t drive1) const;
unsigned test_width_sfunc_(Design*des, NetScope*scope,
unsigned min, unsigned lval,
bool&unsized_flag) const;
};
/*
* $Log: PExpr.h,v $
* Revision 1.90 2007/06/04 19:14:06 steve
* Build errors in picky GCC compilers.
*
* Revision 1.89 2007/06/04 02:19:07 steve
* Handle bit/part select of array words in nets.
*
* Revision 1.88 2007/05/24 04:07:11 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.87 2007/01/16 05:44:14 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.86 2006/11/10 04:54:26 steve
* Add test_width methods for PETernary and PEString.
*
* Revision 1.85 2006/11/04 06:19:24 steve
* Remove last bits of relax_width methods, and use test_width
* to calculate the width of an r-value expression that may
* contain unsized numbers.
*
* Revision 1.84 2006/10/30 05:44:49 steve
* Expression widths with unsized literals are pseudo-infinite width.
*
* Revision 1.83 2006/06/18 04:15:50 steve
* Add support for system functions in continuous assignments.
*
* Revision 1.82 2006/06/02 04:48:49 steve
* Make elaborate_expr methods aware of the width that the context
* requires of it. In the process, fix sizing of the width of unary
* minus is context determined sizes.
*
* Revision 1.81 2006/04/28 04:28:35 steve
* Allow concatenations as arguments to inout ports.
*
* Revision 1.80 2006/04/16 00:54:04 steve
* Cleanup lval part select handling.
*
* Revision 1.79 2006/04/16 00:15:43 steve
* Fix part selects in l-values.
*
* Revision 1.78 2006/03/25 02:36:26 steve
* Get rid of excess PESTring:: prefix within class declaration.
*
* Revision 1.77 2006/02/02 02:43:57 steve
* Allow part selects of memory words in l-values.
*
* Revision 1.76 2006/01/02 05:33:19 steve
* Node delays can be more general expressions in structural contexts.
*
* Revision 1.75 2005/12/07 04:04:23 steve
* Allow constant concat expressions.
*
* Revision 1.74 2005/11/27 17:01:56 steve
* Fix for stubborn compiler.
*
* Revision 1.73 2005/11/27 05:56:20 steve
* Handle bit select of parameter with ranges.
*
* Revision 1.72 2005/11/10 13:28:11 steve
* Reorganize signal part select handling, and add support for
* indexed part selects.
*
* Expand expression constant propagation to eliminate extra
* sums in certain cases.
*
* Revision 1.71 2005/10/04 04:09:25 steve
* Add support for indexed select attached to parameters.
*
* Revision 1.70 2005/08/06 17:58:16 steve
* Implement bi-directional part selects.
*
* Revision 1.69 2005/07/07 16:22:49 steve
* Generalize signals to carry types.
*
* Revision 1.68 2005/01/09 20:16:00 steve
* Use PartSelect/PV and VP to handle part selects through ports.
*
* Revision 1.67 2004/12/29 23:55:43 steve
* Unify elaboration of l-values for all proceedural assignments,
* including assing, cassign and force.
*
* Generate NetConcat devices for gate outputs that feed into a
* vector results. Use this to hande gate arrays. Also let gate
* arrays handle vectors of gates when the outputs allow for it.
*
* Revision 1.66 2004/10/04 01:10:51 steve
* Clean up spurious trailing white space.
*
* Revision 1.65 2003/02/08 19:49:21 steve
* Calculate delay statement delays using elaborated
* expressions instead of pre-elaborated expression
* trees.
*
* Remove the eval_pexpr methods from PExpr.
*
* Revision 1.64 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.63 2002/11/09 19:20:48 steve
* Port expressions for output ports are lnets, not nets.
*
* Revision 1.62 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.61 2002/06/04 05:38:43 steve
* Add support for memory words in l-value of
* blocking assignments, and remove the special
* NetAssignMem class.
*
* Revision 1.60 2002/05/23 03:08:51 steve
* Add language support for Verilog-2001 attribute
* syntax. Hook this support into existing $attribute
* handling, and add number and void value types.
*
* Add to the ivl_target API new functions for access
* of complex attributes attached to gates.
*
* Revision 1.59 2002/04/23 03:53:59 steve
* Add support for non-constant bit select.
*
* Revision 1.58 2002/04/14 03:55:25 steve
* Precalculate unary - if possible.
*
* Revision 1.57 2002/04/13 02:33:17 steve
* Detect missing indices to memories (PR#421)
*
* Revision 1.56 2002/03/09 04:02:26 steve
* Constant expressions are not l-values for task ports.
*
* Revision 1.55 2002/03/09 02:10:22 steve
* Add the NetUserFunc netlist node.
*
* Revision 1.54 2001/12/30 21:32:03 steve
* Support elaborate_net for PEString objects.
*
* Revision 1.53 2001/12/03 04:47:14 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
* Revision 1.52 2001/11/08 05:15:50 steve
* Remove string paths from PExpr elaboration.
*
* Revision 1.51 2001/11/07 04:26:46 steve
* elaborate_lnet uses scope instead of string path.
*
* Revision 1.50 2001/11/07 04:01:59 steve
* eval_const uses scope instead of a string path.
*/
#endif
+3 -31
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1999 Stephen Williams ([email protected])
* Copyright (c) 1999-2008 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,16 +16,13 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PFunction.cc,v 1.7 2004/05/31 23:34:36 steve Exp $"
#endif
# include "config.h"
#include "PTask.h"
PFunction::PFunction(perm_string name)
: name_(name), ports_(0), statement_(0)
PFunction::PFunction(perm_string name, PScope*parent)
: PScope(name, parent), ports_(0), statement_(0)
{
return_type_.type = PTF_NONE;
}
@@ -51,28 +48,3 @@ void PFunction::set_return(PTaskFuncArg t)
{
return_type_ = t;
}
/*
* $Log: PFunction.cc,v $
* Revision 1.7 2004/05/31 23:34:36 steve
* Rewire/generalize parsing an elaboration of
* function return values to allow for better
* speed and more type support.
*
* Revision 1.6 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.5 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.4 2001/01/13 22:20:08 steve
* Parse parameters within nested scopes.
*
* Revision 1.3 2000/02/23 02:56:53 steve
* Macintosh compilers do not support ident.
*
* Revision 1.2 1999/08/25 22:22:41 steve
* elaborate some aspects of functions.
*
*/
+7 -75
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1999-2004 Stephen Williams ([email protected])
* Copyright (c) 1999-2007 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PGate.cc,v 1.18 2006/01/03 05:22:14 steve Exp $"
#endif
# include "config.h"
@@ -120,9 +117,9 @@ void PGate::eval_delays(Design*des, NetScope*scope,
rise_time = tmp->value().as_ulong();
} else {
cerr << get_line() << ": error: Delay expressions must be "
cerr << get_fileline() << ": error: Delay expressions must be "
<< "constant here." << endl;
cerr << get_line() << ": : Cannot calculate "
cerr << get_fileline() << ": : Cannot calculate "
<< *rise_expr << endl;
des->errors += 1;
rise_time = 0;
@@ -133,9 +130,9 @@ void PGate::eval_delays(Design*des, NetScope*scope,
} else {
if (fall_expr != rise_expr) {
cerr << get_line() << ": error: Delay expressions must be "
cerr << get_fileline() << ": error: Delay expressions must be "
<< "constant here." << endl;
cerr << get_line() << ": : Cannot calculate "
cerr << get_fileline() << ": : Cannot calculate "
<< *rise_expr << endl;
}
des->errors += 1;
@@ -146,9 +143,9 @@ void PGate::eval_delays(Design*des, NetScope*scope,
decay_time = tmp->value().as_ulong();
} else {
cerr << get_line() << ": error: Delay expressions must be "
cerr << get_fileline() << ": error: Delay expressions must be "
<< "constant here." << endl;
cerr << get_line() << ": : Cannot calculate "
cerr << get_fileline() << ": : Cannot calculate "
<< *rise_expr << endl;
des->errors += 1;
decay_time = 0;
@@ -246,68 +243,3 @@ perm_string PGModule::get_type()
return type_;
}
/*
* $Log: PGate.cc,v $
* Revision 1.18 2006/01/03 05:22:14 steve
* Handle complex net node delays.
*
* Revision 1.17 2006/01/02 05:33:19 steve
* Node delays can be more general expressions in structural contexts.
*
* Revision 1.16 2004/02/18 17:11:54 steve
* Use perm_strings for named langiage items.
*
* Revision 1.15 2003/03/06 04:37:12 steve
* lex_strings.add module names earlier.
*
* Revision 1.14 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.13 2001/11/22 06:20:59 steve
* Use NetScope instead of string for scope path.
*
* Revision 1.12 2001/10/21 00:42:47 steve
* Module types in pform are char* instead of string.
*
* Revision 1.11 2001/10/19 01:55:32 steve
* Method to get the type_ member
*
* Revision 1.10 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.9 2000/05/06 15:41:56 steve
* Carry assignment strength to pform.
*
* Revision 1.8 2000/03/08 04:36:53 steve
* Redesign the implementation of scopes and parameters.
* I now generate the scopes and notice the parameters
* in a separate pass over the pform. Once the scopes
* are generated, I can process overrides and evalutate
* paremeters before elaboration begins.
*
* Revision 1.7 2000/02/23 02:56:53 steve
* Macintosh compilers do not support ident.
*
* Revision 1.6 2000/02/18 05:15:02 steve
* Catch module instantiation arrays.
*
* Revision 1.5 1999/09/14 01:50:35 steve
* Handle gates without delays.
*
* Revision 1.4 1999/09/04 19:11:46 steve
* Add support for delayed non-blocking assignments.
*
* Revision 1.3 1999/08/01 21:18:55 steve
* elaborate rise/fall/decay for continuous assign.
*
* Revision 1.2 1999/08/01 16:34:50 steve
* Parse and elaborate rise/fall/decay times
* for gates, and handle the rules for partial
* lists of times.
*
* Revision 1.1 1999/02/15 02:06:15 steve
* Elaborate gate ranges.
*
*/
+5 -133
View File
@@ -27,12 +27,11 @@
# include "named.h"
# include "LineInfo.h"
# include "PDelays.h"
# include "netlist.h"
# include <map>
# include <string>
class PExpr;
class PUdp;
class Design;
class NetScope;
class Module;
/*
@@ -235,137 +234,10 @@ class PGModule : public PGate {
void elaborate_udp_(Design*, PUdp *udp, NetScope*scope) const;
void elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const;
bool elaborate_sig_mod_(Design*des, NetScope*scope, Module*mod) const;
NetNet*resize_net_to_port_(Design*des, NetScope*scope,
NetNet*sig, unsigned port_wid,
NetNet::PortType dir) const;
};
/*
* $Log: PGate.h,v $
* Revision 1.32 2006/04/10 00:37:42 steve
* Add support for generate loops w/ wires and gates.
*
* Revision 1.31 2006/01/03 05:22:14 steve
* Handle complex net node delays.
*
* Revision 1.30 2006/01/02 05:33:19 steve
* Node delays can be more general expressions in structural contexts.
*
* Revision 1.29 2004/10/04 01:10:52 steve
* Clean up spurious trailing white space.
*
* Revision 1.28 2004/03/08 00:47:44 steve
* primitive ports can bind bi name.
*
* Revision 1.27 2004/02/20 18:53:33 steve
* Addtrbute keys are perm_strings.
*
* Revision 1.26 2004/02/18 17:11:54 steve
* Use perm_strings for named langiage items.
*
* Revision 1.25 2003/03/06 04:37:12 steve
* lex_strings.add module names earlier.
*
* Revision 1.24 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.23 2002/05/23 03:08:51 steve
* Add language support for Verilog-2001 attribute
* syntax. Hook this support into existing $attribute
* handling, and add number and void value types.
*
* Add to the ivl_target API new functions for access
* of complex attributes attached to gates.
*
* Revision 1.22 2001/11/22 06:20:59 steve
* Use NetScope instead of string for scope path.
*
* Revision 1.21 2001/10/21 00:42:47 steve
* Module types in pform are char* instead of string.
*
* Revision 1.20 2001/10/19 01:55:32 steve
* Method to get the type_ member
*
* Revision 1.19 2001/04/22 23:09:45 steve
* More UDP consolidation from Stephan Boettcher.
*
* Revision 1.18 2000/05/06 15:41:56 steve
* Carry assignment strength to pform.
*
* Revision 1.17 2000/05/02 16:27:38 steve
* Move signal elaboration to a seperate pass.
*
* Revision 1.16 2000/03/29 04:37:10 steve
* New and improved combinational primitives.
*
* Revision 1.15 2000/03/08 04:36:53 steve
* Redesign the implementation of scopes and parameters.
* I now generate the scopes and notice the parameters
* in a separate pass over the pform. Once the scopes
* are generated, I can process overrides and evalutate
* paremeters before elaboration begins.
*
* Revision 1.14 2000/02/23 02:56:53 steve
* Macintosh compilers do not support ident.
*
* Revision 1.13 2000/02/18 05:15:02 steve
* Catch module instantiation arrays.
*
* Revision 1.12 2000/01/09 05:50:48 steve
* Support named parameter override lists.
*
* Revision 1.11 1999/12/11 05:45:41 steve
* Fix support for attaching attributes to primitive gates.
*
* Revision 1.10 1999/09/04 19:11:46 steve
* Add support for delayed non-blocking assignments.
*
* Revision 1.9 1999/08/23 16:48:39 steve
* Parameter overrides support from Peter Monta
* AND and XOR support wide expressions.
*
* Revision 1.8 1999/08/01 21:18:55 steve
* elaborate rise/fall/decay for continuous assign.
*
* Revision 1.7 1999/08/01 16:34:50 steve
* Parse and elaborate rise/fall/decay times
* for gates, and handle the rules for partial
* lists of times.
*
* Revision 1.6 1999/05/29 02:36:17 steve
* module parameter bind by name.
*
* Revision 1.5 1999/05/10 00:16:58 steve
* Parse and elaborate the concatenate operator
* in structural contexts, Replace vector<PExpr*>
* and list<PExpr*> with svector<PExpr*>, evaluate
* constant expressions with parameters, handle
* memories as lvalues.
*
* Parse task declarations, integer types.
*
* Revision 1.4 1999/02/15 02:06:15 steve
* Elaborate gate ranges.
*
* Revision 1.3 1999/01/25 05:45:56 steve
* Add the LineInfo class to carry the source file
* location of things. PGate, Statement and PProcess.
*
* elaborate handles module parameter mismatches,
* missing or incorrect lvalues for procedural
* assignment, and errors are propogated to the
* top of the elaboration call tree.
*
* Attach line numbers to processes, gates and
* assignment statements.
*
* Revision 1.2 1998/12/01 00:42:13 steve
* Elaborate UDP devices,
* Support UDP type attributes, and
* pass those attributes to nodes that
* are instantiated by elaboration,
* Put modules into a map instead of
* a simple list.
*
* Revision 1.1 1998/11/03 23:28:54 steve
* Introduce verilog to CVS.
*
*/
#endif
+2 -12
View File
@@ -33,19 +33,9 @@ PGenerate::~PGenerate()
{
}
PWire* PGenerate::add_wire(PWire*wire)
PWire* PGenerate::get_wire(perm_string name) const
{
PWire*&ep = wires[wire->path()];
if (ep) return ep;
assert(ep == 0);
ep = wire;
return wire;
}
PWire* PGenerate::get_wire(const pform_name_t&name) const
{
map<pform_name_t,PWire*>::const_iterator obj = wires.find(name);
map<perm_string,PWire*>::const_iterator obj = wires.find(name);
if (obj == wires.end())
return 0;
else
+24 -7
View File
@@ -37,7 +37,17 @@ class PGate;
class PWire;
/*
* This represents a generate scheme.
* This represents a generate scheme. The interpretation of the
* members depends on the scheme_type.
*
* GS_LOOP
*
* GS_CASE
* loop_test is the expression to be compared.
* generates contains only GS_CASE_ITEM schemes.
* GS_CASE_ITEM
* The parent points to the GS_CASE that contains this item.
* the loop_test is compared with the parent->loop_test expression.
*/
class PGenerate : public LineInfo {
@@ -50,7 +60,8 @@ class PGenerate : public LineInfo {
const unsigned id_number;
perm_string scope_name;
enum scheme_t {GS_NONE, GS_LOOP, GS_CONDIT};
enum scheme_t {GS_NONE, GS_LOOP, GS_CONDIT, GS_ELSE,
GS_CASE, GS_CASE_ITEM};
scheme_t scheme_type;
// generate loops have an index variable and three
@@ -60,9 +71,8 @@ class PGenerate : public LineInfo {
PExpr*loop_test;
PExpr*loop_step;
map<pform_name_t,PWire*>wires;
PWire* add_wire(PWire*);
PWire* get_wire(const pform_name_t&name) const;
map<perm_string,PWire*>wires;
PWire* get_wire(perm_string name) const;
list<PGate*> gates;
void add_gate(PGate*);
@@ -78,13 +88,20 @@ class PGenerate : public LineInfo {
// contain the generated scope.
bool generate_scope(Design*des, NetScope*container);
bool elaborate_sig(Design*des) const;
bool elaborate(Design*des) const;
// Elaborate signals within any of the generated scopes that
// were made by this generate block within the given container scope.
bool elaborate_sig(Design*des, NetScope*container) const;
bool elaborate(Design*des, NetScope*container) const;
void dump(ostream&out, unsigned indent) const;
private:
bool generate_scope_loop_(Design*des, NetScope*container);
bool generate_scope_condit_(Design*des, NetScope*container, bool else_flag);
bool generate_scope_case_(Design*des, NetScope*container);
// Elaborate_scope within a generated scope.
void elaborate_subscope_(Design*des, NetScope*scope);
// These are the scopes created by generate_scope.
list<NetScope*>scope_list_;
+17 -19
View File
@@ -1,7 +1,5 @@
%{
/*
* Copyright (c) 1999 Stephen Williams (steve@icarus.com)
* Copyright (c) 2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,23 +16,23 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: parse.y,v 1.4 2003/08/26 16:26:02 steve Exp $"
#endif
# include <stdio.h>
# include "PScope.h"
static void yyerror(const char*msg);
%}
%%
file : ;
%%
void yyerror(const char*msg)
PScope::PScope(perm_string n, PScope*p)
: name_(n), parent_(p)
{
fprintf(stderr, "ivlpp error: %s\n", msg);
}
PScope::~PScope()
{
}
PWire* PScope::wires_find(perm_string name)
{
map<perm_string,PWire*>::const_iterator cur = wires.find(name);
if (cur == wires.end())
return 0;
else
return (*cur).second;
}
+80
View File
@@ -0,0 +1,80 @@
#ifndef __PScope_H
#define __PScope_H
/*
* Copyright (c) 2008 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
# include "StringHeap.h"
# include "pform_types.h"
# include <map>
class PEvent;
class PProcess;
class PWire;
class Design;
class NetScope;
/*
* The PScope class is a base representation of an object that
* represents lexical scope. For example, a module, a function/task, a
* named block is derived from a PScope.
*
* NOTE: This is note the same concept as the "scope" of an elaborated
* hierarchy. That is represented by NetScope objects after elaboration.
*/
class PScope {
public:
// When created, a scope has a name and a parent. The name is
// the name of the definition. For example, if this is a
// module declaration, the name is the name after the "module"
// keyword, and if this is a task scope, the name is the task
// name. The parent is the lexical parent of this scope. Since
// modules do not nest in Verilog, the parent must be nil for
// modules. Scopes for tasks and functions point to their
// containing module.
PScope(perm_string name, PScope*parent);
virtual ~PScope();
perm_string pscope_name() const { return name_; }
PScope* pscope_parent() { return parent_; }
// Nets an variables (wires) in the scope
map<perm_string,PWire*>wires;
PWire* wires_find(perm_string name);
// Named events in the scope.
map<perm_string,PEvent*>events;
// Behaviors (processes) in this scope
list<PProcess*> behaviors;
protected:
void dump_wires_(ostream&out, unsigned indent) const;
bool elaborate_sig_wires_(Design*des, NetScope*scope) const;
bool elaborate_behaviors_(Design*des, NetScope*scope) const;
private:
perm_string name_;
PScope*parent_;
};
#endif
+3 -6
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1999 Stephen Williams ([email protected])
* Copyright (c) 1999-2008 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,16 +16,13 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PTask.cc,v 1.7 2002/08/12 01:34:58 steve Exp $"
#endif
# include "config.h"
# include "PTask.h"
PTask::PTask()
: ports_(0), statement_(0)
PTask::PTask(perm_string name, PScope*parent)
: PScope(name, parent), ports_(0), statement_(0)
{
}
+6 -67
View File
@@ -1,7 +1,7 @@
#ifndef __PTask_H
#define __PTask_H
/*
* Copyright (c) 1999-2000 Stephen Williams ([email protected])
* Copyright (c) 1999-2008 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,11 +18,9 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PTask.h,v 1.14 2007/03/06 05:22:49 steve Exp $"
#endif
# include "LineInfo.h"
# include "PScope.h"
# include "svector.h"
# include "StringHeap.h"
# include <string>
@@ -50,10 +48,10 @@ struct PTaskFuncArg {
/*
* The PTask holds the parsed definitions of a task.
*/
class PTask : public LineInfo {
class PTask : public PScope, public LineInfo {
public:
explicit PTask();
explicit PTask(perm_string name, PScope*parent);
~PTask();
void set_ports(svector<PWire *>*p);
@@ -89,10 +87,10 @@ class PTask : public LineInfo {
*
* The output value is not elaborated until elaborate_sig.
*/
class PFunction : public LineInfo {
class PFunction : public PScope, public LineInfo {
public:
explicit PFunction(perm_string name);
explicit PFunction(perm_string name, PScope*parent);
~PFunction();
void set_ports(svector<PWire *>*p);
@@ -110,68 +108,9 @@ class PFunction : public LineInfo {
void dump(ostream&, unsigned) const;
private:
perm_string name_;
PTaskFuncArg return_type_;
svector<PWire *> *ports_;
Statement *statement_;
};
/*
* $Log: PTask.h,v $
* Revision 1.14 2007/03/06 05:22:49 steve
* Support signed function return values.
*
* Revision 1.13 2004/05/31 23:34:36 steve
* Rewire/generalize parsing an elaboration of
* function return values to allow for better
* speed and more type support.
*
* Revision 1.12 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.11 2001/11/22 06:20:59 steve
* Use NetScope instead of string for scope path.
*
* Revision 1.10 2001/01/13 22:20:08 steve
* Parse parameters within nested scopes.
*
* Revision 1.9 2000/07/30 18:25:43 steve
* Rearrange task and function elaboration so that the
* NetTaskDef and NetFuncDef functions are created during
* signal enaboration, and carry these objects in the
* NetScope class instead of the extra, useless map in
* the Design class.
*
* Revision 1.8 2000/03/08 04:36:53 steve
* Redesign the implementation of scopes and parameters.
* I now generate the scopes and notice the parameters
* in a separate pass over the pform. Once the scopes
* are generated, I can process overrides and evalutate
* paremeters before elaboration begins.
*
* Revision 1.7 2000/02/23 02:56:53 steve
* Macintosh compilers do not support ident.
*
* Revision 1.6 1999/09/30 21:28:34 steve
* Handle mutual reference of tasks by elaborating
* task definitions in two passes, like functions.
*
* Revision 1.5 1999/09/01 20:46:19 steve
* Handle recursive functions and arbitrary function
* references to other functions, properly pass
* function parameters and save function results.
*
* Revision 1.4 1999/08/25 22:22:41 steve
* elaborate some aspects of functions.
*
* Revision 1.3 1999/07/31 19:14:47 steve
* Add functions up to elaboration (Ed Carter)
*
* Revision 1.2 1999/07/24 02:11:19 steve
* Elaborate task input ports.
*
* Revision 1.1 1999/07/03 02:12:51 steve
* Elaborate user defined tasks.
*
*/
#endif
+84 -70
View File
@@ -16,21 +16,21 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: PWire.cc,v 1.14 2007/05/24 04:07:11 steve Exp $"
#endif
# include "config.h"
# include "PWire.h"
# include "PExpr.h"
# include <assert.h>
PWire::PWire(const pform_name_t&n,
PWire::PWire(perm_string n,
NetNet::Type t,
NetNet::PortType pt,
ivl_variable_type_t dt)
: hname_(n), type_(t), port_type_(pt), data_type_(dt),
: name_(n), type_(t), port_type_(pt), data_type_(dt),
signed_(false), isint_(false),
lidx_(0), ridx_(0)
port_msb_(0), port_lsb_(0), port_set_(false),
net_msb_(0), net_lsb_(0), net_set_(false), error_cnt_(0),
lidx_(0), ridx_(0)
{
if (t == NetNet::INTEGER) {
type_ = NetNet::REG;
@@ -44,9 +44,9 @@ NetNet::Type PWire::get_wire_type() const
return type_;
}
const pform_name_t& PWire::path() const
perm_string PWire::basename() const
{
return hname_;
return name_;
}
bool PWire::set_wire_type(NetNet::Type t)
@@ -103,17 +103,23 @@ bool PWire::set_port_type(NetNet::PortType pt)
bool PWire::set_data_type(ivl_variable_type_t dt)
{
if (data_type_ != IVL_VT_NO_TYPE)
if (data_type_ != IVL_VT_NO_TYPE) {
if (data_type_ != dt)
return false;
else
return true;
}
assert(data_type_ == IVL_VT_NO_TYPE);
data_type_ = dt;
return true;
}
ivl_variable_type_t PWire::get_data_type() const
{
return data_type_;
}
void PWire::set_signed(bool flag)
{
signed_ = flag;
@@ -129,71 +135,79 @@ bool PWire::get_isint() const
return isint_;
}
void PWire::set_range(PExpr*m, PExpr*l)
/*
* Since implicitly defined list of port declarations are no longer
* considered fully defined we no longer need this routine to force
* them to be fully defined.
*
void PWire::set_net_range()
{
msb_ = svector<PExpr*>(msb_,m);
lsb_ = svector<PExpr*>(lsb_,l);
net_msb_ = port_msb_;
net_lsb_ = port_lsb_;
net_set_ = true;
}
*/
void PWire::set_range(PExpr*m, PExpr*l, PWSRType type)
{
switch (type) {
case SR_PORT:
if (port_set_) {
cerr << get_fileline() << ": error: Port ``" << name_
<< "'' has already been declared a port." << endl;
error_cnt_ += 1;
} else {
port_msb_ = m;
port_lsb_ = l;
port_set_ = true;
}
return;
case SR_NET:
if (net_set_) {
cerr << get_fileline() << ": error: Net ``" << name_
<< "'' has already been declared." << endl;
error_cnt_ += 1;
} else {
net_msb_ = m;
net_lsb_ = l;
net_set_ = true;
}
return;
case SR_BOTH:
if (port_set_ || net_set_) {
if (port_set_) {
cerr << get_fileline() << ": error: Port ``" << name_
<< "'' has already been declared a port." << endl;
error_cnt_ += 1;
}
if (net_set_) {
cerr << get_fileline() << ": error: Net ``" << name_
<< "'' has already been declared." << endl;
error_cnt_ += 1;
}
} else {
port_msb_ = m;
port_lsb_ = l;
port_set_ = true;
net_msb_ = m;
net_lsb_ = l;
net_set_ = true;
}
return;
}
}
void PWire::set_memory_idx(PExpr*ldx, PExpr*rdx)
{
assert(lidx_ == 0);
assert(ridx_ == 0);
lidx_ = ldx;
ridx_ = rdx;
if (lidx_ != 0 || ridx_ != 0) {
cerr << get_fileline() << ": error: Array ``" << name_
<< "'' has already been declared." << endl;
error_cnt_ += 1;
} else {
lidx_ = ldx;
ridx_ = rdx;
}
}
/*
* $Log: PWire.cc,v $
* Revision 1.14 2007/05/24 04:07:11 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.13 2007/04/26 03:06:21 steve
* Rework hname_t to use perm_strings.
*
* Revision 1.12 2007/01/16 05:44:14 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.11 2005/07/07 16:22:49 steve
* Generalize signals to carry types.
*
* Revision 1.10 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.9 2002/06/21 04:59:35 steve
* Carry integerness throughout the compilation.
*
* Revision 1.8 2002/01/26 05:28:28 steve
* Detect scalar/vector declarion mismatch.
*
* Revision 1.7 2001/12/03 04:47:14 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
* Revision 1.6 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.5 2001/01/06 02:29:35 steve
* Support arrays of integers.
*
* Revision 1.4 2000/12/11 00:31:43 steve
* Add support for signed reg variables,
* simulate in t-vvm signed comparisons.
*
* Revision 1.3 2000/02/23 02:56:54 steve
* Macintosh compilers do not support ident.
*
* Revision 1.2 1999/09/10 05:02:09 steve
* Handle integers at task parameters.
*
* Revision 1.1 1999/06/17 05:34:42 steve
* Clean up interface of the PWire class,
* Properly match wire ranges.
*
*/
+17 -52
View File
@@ -37,6 +37,11 @@ class ostream;
class PExpr;
class Design;
/*
* The different type of PWire::set_range() calls.
*/
enum PWSRType {SR_PORT, SR_NET, SR_BOTH};
/*
* Wires include nets, registers and ports. A net or register becomes
* a port by declaration, so ports are not separate. The module
@@ -51,13 +56,13 @@ class Design;
class PWire : public LineInfo {
public:
PWire(const pform_name_t&hname,
PWire(perm_string name,
NetNet::Type t,
NetNet::PortType pt,
ivl_variable_type_t dt);
// Return a hierarchical name.
const pform_name_t&path() const;
perm_string basename() const;
NetNet::Type get_wire_type() const;
bool set_wire_type(NetNet::Type);
@@ -72,7 +77,8 @@ class PWire : public LineInfo {
bool set_data_type(ivl_variable_type_t dt);
ivl_variable_type_t get_data_type() const;
void set_range(PExpr*msb, PExpr*lsb);
void set_range(PExpr*msb, PExpr*lsb, PWSRType type);
void set_net_range();
void set_memory_idx(PExpr*ldx, PExpr*rdx);
@@ -84,7 +90,7 @@ class PWire : public LineInfo {
NetNet* elaborate_sig(Design*, NetScope*scope) const;
private:
pform_name_t hname_;
perm_string name_;
NetNet::Type type_;
NetNet::PortType port_type_;
ivl_variable_type_t data_type_;
@@ -93,8 +99,13 @@ class PWire : public LineInfo {
// These members hold expressions for the bit width of the
// wire. If they do not exist, the wire is 1 bit wide.
svector<PExpr*>msb_;
svector<PExpr*>lsb_;
PExpr*port_msb_;
PExpr*port_lsb_;
bool port_set_;
PExpr*net_msb_;
PExpr*net_lsb_;
bool net_set_;
unsigned error_cnt_;
// If this wire is actually a memory, these indices will give
// me the size and address range of the memory.
@@ -106,50 +117,4 @@ class PWire : public LineInfo {
PWire& operator= (const PWire&);
};
/*
* $Log: PWire.h,v $
* Revision 1.21 2007/05/24 04:07:11 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.20 2007/04/26 03:06:22 steve
* Rework hname_t to use perm_strings.
*
* Revision 1.19 2006/04/10 00:37:42 steve
* Add support for generate loops w/ wires and gates.
*
* Revision 1.18 2005/07/07 16:22:49 steve
* Generalize signals to carry types.
*
* Revision 1.17 2004/02/20 18:53:33 steve
* Addtrbute keys are perm_strings.
*
* Revision 1.16 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.15 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions.
*
* Revision 1.14 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.13 2002/06/21 04:59:35 steve
* Carry integerness throughout the compilation.
*
* Revision 1.12 2002/05/23 03:08:51 steve
* Add language support for Verilog-2001 attribute
* syntax. Hook this support into existing $attribute
* handling, and add number and void value types.
*
* Add to the ivl_target API new functions for access
* of complex attributes attached to gates.
*
* Revision 1.11 2001/12/03 04:47:14 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
* Revision 1.10 2001/01/16 02:44:18 steve
* Use the iosfwd header if available.
*/
#endif
+8 -8
View File
@@ -86,18 +86,13 @@ PAssignNB::~PAssignNB()
{
}
PBlock::PBlock(perm_string n, BL_TYPE t, const svector<Statement*>&st)
: name_(n), bl_type_(t), list_(st)
{
}
PBlock::PBlock(BL_TYPE t, const svector<Statement*>&st)
: bl_type_(t), list_(st)
PBlock::PBlock(perm_string n, PScope*parent, BL_TYPE t)
: PScope(n, parent), bl_type_(t)
{
}
PBlock::PBlock(BL_TYPE t)
: bl_type_(t)
: PScope(perm_string(),0), bl_type_(t)
{
}
@@ -107,6 +102,11 @@ PBlock::~PBlock()
delete list_[idx];
}
void PBlock::set_statement(const svector<Statement*>&st)
{
list_ = st;
}
PCallTask::PCallTask(const pform_name_t&n, const svector<PExpr*>&p)
: path_(n), parms_(p)
{
+14 -4
View File
@@ -27,6 +27,7 @@
# include "StringHeap.h"
# include "PDelays.h"
# include "PExpr.h"
# include "PScope.h"
# include "HName.h"
# include "LineInfo.h"
class PExpr;
@@ -83,6 +84,7 @@ class Statement : public LineInfo {
virtual void dump(ostream&out, unsigned ind) const;
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
virtual void elaborate_scope(Design*des, NetScope*scope) const;
virtual void elaborate_sig(Design*des, NetScope*scope) const;
};
/*
@@ -147,25 +149,27 @@ class PAssignNB : public PAssign_ {
* statements before constructing this object, so it knows a priori
* what is contained.
*/
class PBlock : public Statement {
class PBlock : public PScope, public Statement {
public:
enum BL_TYPE { BL_SEQ, BL_PAR };
explicit PBlock(perm_string n, BL_TYPE t, const svector<Statement*>&st);
explicit PBlock(BL_TYPE t, const svector<Statement*>&st);
// If the block has a name, it is a scope and also has a parent.
explicit PBlock(perm_string n, PScope*parent, BL_TYPE t);
// If it doesn't have a name, it's not a scope
explicit PBlock(BL_TYPE t);
~PBlock();
BL_TYPE bl_type() const { return bl_type_; }
void set_statement(const svector<Statement*>&st);
virtual void dump(ostream&out, unsigned ind) const;
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
virtual void elaborate_scope(Design*des, NetScope*scope) const;
virtual void elaborate_sig(Design*des, NetScope*scope) const;
private:
perm_string name_;
const BL_TYPE bl_type_;
svector<Statement*>list_;
};
@@ -215,6 +219,7 @@ class PCase : public Statement {
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
virtual void elaborate_scope(Design*des, NetScope*scope) const;
virtual void elaborate_sig(Design*des, NetScope*scope) const;
virtual void dump(ostream&out, unsigned ind) const;
private:
@@ -250,6 +255,7 @@ class PCondit : public Statement {
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
virtual void elaborate_scope(Design*des, NetScope*scope) const;
virtual void elaborate_sig(Design*des, NetScope*scope) const;
virtual void dump(ostream&out, unsigned ind) const;
private:
@@ -284,6 +290,7 @@ class PDelayStatement : public Statement {
virtual void dump(ostream&out, unsigned ind) const;
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
virtual void elaborate_scope(Design*des, NetScope*scope) const;
virtual void elaborate_sig(Design*des, NetScope*scope) const;
private:
PExpr*delay_;
@@ -331,6 +338,7 @@ class PEventStatement : public Statement {
virtual void dump(ostream&out, unsigned ind) const;
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
virtual void elaborate_scope(Design*des, NetScope*scope) const;
virtual void elaborate_sig(Design*des, NetScope*scope) const;
// This method is used to elaborate, but attach a previously
// elaborated statement to the event.
@@ -364,6 +372,7 @@ class PForever : public Statement {
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
virtual void elaborate_scope(Design*des, NetScope*scope) const;
virtual void elaborate_sig(Design*des, NetScope*scope) const;
virtual void dump(ostream&out, unsigned ind) const;
private:
@@ -379,6 +388,7 @@ class PForStatement : public Statement {
virtual NetProc* elaborate(Design*des, NetScope*scope) const;
virtual void elaborate_scope(Design*des, NetScope*scope) const;
virtual void elaborate_sig(Design*des, NetScope*scope) const;
virtual void dump(ostream&out, unsigned ind) const;
private:
+1 -13
View File
@@ -33,7 +33,7 @@ bindir = @bindir@
libdir = @libdir@
includedir = $(prefix)/include
vpidir = @libdir@/ivl/@vpidir1@
vpidir = @libdir@/ivl
CC = @CC@
INSTALL = @INSTALL@
@@ -48,14 +48,6 @@ SHARED = @shared@
all:
ifeq (@enable_vvp32@,yes)
vpidir32 = $(libdir)/ivl/@vpidir2@
ALL32 = all32
INSTALL32 = install32
UNINSTALL32 = uninstall32
include $(srcdir)/enable_vvp32.mk
endif
all: dep cadpli.vpl $(ALL32)
# No specific check operations.
@@ -97,8 +89,4 @@ uninstall: $(UNINSTALL32)
uninstall32:
ifeq (@enable_vvp32@,yes)
include $(srcdir)/enable_vvp32.mk
endif
-include $(patsubst %.o, dep/%.d, $O)
-15
View File
@@ -12,10 +12,6 @@ AX_WIN32
AC_PROG_INSTALL
# vvp32 is by default disabled
#enable_vvp32=no
AC_SUBST(enable_vvp32)
AC_CHECK_HEADERS(malloc.h)
AC_CHECK_SIZEOF(unsigned long long)
@@ -62,15 +58,4 @@ AX_C_UNDERSCORES_TRAILING
AX_CPP_IDENT
# where to put vpi subdirectories
AC_MSG_CHECKING(for VPI subdirectories)
if test x${vpidir1} = x
then
vpidir1="."
fi
AC_SUBST(vpidir1)
AC_SUBST(vpidir2)
AC_MSG_RESULT(${vpidir1} ${vpidir2})
AC_OUTPUT(Makefile)
-39
View File
@@ -1,39 +0,0 @@
#
# This source code is free software; you can redistribute it
# and/or modify it in source code form under the terms of the GNU
# Library General Public License as published by the Free Software
# Foundation; either version 2 of the License, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU Library General Public License for more details.
#
# You should have received a copy of the GNU Library General Public
# License along with this program; if not, write to the Free
# Software Foundation, Inc.,
# 59 Temple Place - Suite 330
# Boston, MA 02111-1307, USA
#
#ident "$Id: enable_vvp32.mk,v 1.1 2003/10/09 01:07:20 steve Exp $"
#
all32: bin32 bin32/cadpli.vpl
bin32:
mkdir bin32
bin32/%.o: %.c
$(CC) -m32 -Wall -I$(srcdir) -I$(srcdir)/.. $(CPPFLAGS) $(CFLAGS) -MD -c $< -o $@
bin32/cadpli.vpl: $(addprefix bin32/,$O) ../vvp/bin32/libvpi.a ../libveriuser/bin32/libveriuser.o
$(CC) $(SHARED) -m32 -o $@ $(addprefix bin32/,$O) ../libveriuser/bin32/libveriuser.o ../vvp/bin32/libvpi.a
install32: all32 $(vpidir32)/cadpli.vpl
$(vpidir32)/cadpli.vpl: bin32/cadpli.vpl
$(INSTALL_PROGRAM) bin32/cadpli.vpl $(vpidir32)/cadpli.vpl
uninstall32:
rm -f $(vpidir32)/cadpli.vpl
+11 -11
View File
@@ -35,16 +35,16 @@ typedef shl_t ivl_dll_t;
#endif
#if defined(__MINGW32__)
inline ivl_dll_t ivl_dlopen(const char *name)
static inline ivl_dll_t ivl_dlopen(const char *name)
{ return (void *)LoadLibrary(name); }
inline void *ivl_dlsym(ivl_dll_t dll, const char *nm)
static inline void *ivl_dlsym(ivl_dll_t dll, const char *nm)
{ return (void *)GetProcAddress((HINSTANCE)dll,nm);}
inline void ivl_dlclose(ivl_dll_t dll)
static inline void ivl_dlclose(ivl_dll_t dll)
{ (void)FreeLibrary((HINSTANCE)dll);}
inline const char *dlerror(void)
static inline const char *dlerror(void)
{
static char msg[256];
unsigned long err = GetLastError();
@@ -61,10 +61,10 @@ inline const char *dlerror(void)
}
#elif defined(HAVE_DLFCN_H)
inline ivl_dll_t ivl_dlopen(const char*name)
static inline ivl_dll_t ivl_dlopen(const char*name)
{ return dlopen(name,RTLD_LAZY); }
inline void* ivl_dlsym(ivl_dll_t dll, const char*nm)
static inline void* ivl_dlsym(ivl_dll_t dll, const char*nm)
{
void*sym = dlsym(dll, nm);
/* Not found? try without the leading _ */
@@ -73,24 +73,24 @@ inline void* ivl_dlsym(ivl_dll_t dll, const char*nm)
return sym;
}
inline void ivl_dlclose(ivl_dll_t dll)
static inline void ivl_dlclose(ivl_dll_t dll)
{ dlclose(dll); }
#elif defined(HAVE_DL_H)
inline ivl_dll_t ivl_dlopen(const char*name)
static inline ivl_dll_t ivl_dlopen(const char*name)
{ return shl_load(name, BIND_IMMEDIATE, 0); }
inline void* ivl_dlsym(ivl_dll_t dll, const char*nm)
static inline void* ivl_dlsym(ivl_dll_t dll, const char*nm)
{
void*sym;
int rc = shl_findsym(&dll, nm, TYPE_PROCEDURE, &sym);
return (rc == 0) ? sym : 0;
}
inline void ivl_dlclose(ivl_dll_t dll)
static inline void ivl_dlclose(ivl_dll_t dll)
{ shl_unload(dll); }
inline const char*dlerror(void)
static inline const char*dlerror(void)
{ return strerror( errno ); }
#endif
+19 -68
View File
@@ -1,7 +1,7 @@
#ifndef __compiler_H
#define __compiler_H
/*
* Copyright (c) 1999-2004 Stephen Williams ([email protected])
* Copyright (c) 1999-2007 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: compiler.h,v 1.33 2007/04/19 02:52:53 steve Exp $"
#endif
# include <list>
# include <map>
@@ -32,7 +29,11 @@
*/
/* The integer_width is the width of integer variables. */
/*
* The integer_width is the width of integer variables. This is also
* the minimum width of unsized integers when they are found in
* self-determined contexts.
*/
extern unsigned integer_width;
/* The TIME_WIDTH is the width of time variables. */
@@ -112,6 +113,10 @@ inline bool gn_cadence_types_enabled()
is false, then skip elaboration of specify behavior. */
extern bool gn_specify_blocks_flag;
/* If this flag is false a warning is printed when the port declaration
is scalar and the net/register definition is vectored. */
extern bool gn_io_range_error_flag;
/* This is the string to use to invoke the preprocessor. */
extern char*ivlpp_string;
@@ -122,7 +127,7 @@ extern map<perm_string,unsigned> missing_modules;
matches an entry in this table, it will turn on the
library_active_flag so that modules know that they are in a
library. */
extern map<string,bool> library_file_map;
extern map<perm_string,bool> library_file_map;
/*
* the lex_strings are perm_strings made up of tokens from the source
@@ -132,6 +137,14 @@ extern map<string,bool> library_file_map;
extern StringHeapLex lex_strings;
extern StringHeap misc_strings;
/*
* The filename_strings are perm_strings for file names. They are put
* into their own StringHeapLex because these paths are used a *lot*
* and this makes them more sure to hash together.
*/
extern StringHeapLex filename_strings;
/*
* system task/function listings.
*/
@@ -150,66 +163,4 @@ struct sfunc_return_type {
extern const struct sfunc_return_type* lookup_sys_func(const char*name);
extern int load_sys_func_table(const char*path);
/*
* $Log: compiler.h,v $
* Revision 1.33 2007/04/19 02:52:53 steve
* Add support for -v flag in command file.
*
* Revision 1.32 2007/03/07 04:24:59 steve
* Make integer width controllable.
*
* Revision 1.31 2006/09/28 04:35:18 steve
* Support selective control of specify and xtypes features.
*
* Revision 1.30 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.29 2005/07/07 16:22:49 steve
* Generalize signals to carry types.
*
* Revision 1.28 2005/06/28 04:25:55 steve
* Remove reference to SystemVerilog.
*
* Revision 1.27 2005/04/24 23:44:01 steve
* Update DFF support to new data flow.
*
* Revision 1.26 2004/10/04 01:10:52 steve
* Clean up spurious trailing white space.
*
* Revision 1.25 2004/09/25 01:58:44 steve
* Add a debug_elaborate flag
*
* Revision 1.24 2004/09/10 23:51:42 steve
* Fix the evaluation of constant ternary expressions.
*
* Revision 1.23 2004/09/05 17:44:41 steve
* Add support for module instance arrays.
*
* Revision 1.22 2004/03/10 04:51:24 steve
* Add support for system function table files.
*
* Revision 1.21 2004/03/09 04:29:42 steve
* Separate out the lookup_sys_func table, for eventual
* support for function type tables.
*
* Remove ipal compile flags.
*
* Revision 1.20 2004/02/18 17:11:54 steve
* Use perm_strings for named langiage items.
*
* Revision 1.19 2003/11/13 05:55:33 steve
* Move the DLL= flag to target config files.
*
* Revision 1.18 2003/11/08 20:06:21 steve
* Spelling fixes in comments.
*
* Revision 1.17 2003/09/25 00:25:14 steve
* Summary list of missing modules.
*
* Revision 1.16 2003/03/01 06:25:30 steve
* Add the lex_strings string handler, and put
* scope names and system task/function names
* into this table. Also, permallocate event
* names from the beginning.
*/
#endif
+3 -26
View File
@@ -42,11 +42,6 @@ AC_SUBST(EXEEXT)
# Combined check for Microsoft-related bogosities; sets WIN32 if found
AX_WIN32
# vvp32 is by default disabled
#enable_vvp32=no
AC_SUBST(enable_vvp32)
AC_LANG_CPLUSPLUS
AC_CHECK_HEADERS(getopt.h malloc.h inttypes.h libiberty.h iosfwd sys/wait.h)
@@ -56,9 +51,12 @@ AC_CHECK_LIB(z, gzwrite, HAVE_LIBZ=yes, HAVE_LIBZ=no)
AC_SUBST(HAVE_LIBZ)
if test "$WIN32" = "yes"; then
AC_CHECK_LIB(bz2, main)
AC_CHECK_LIB(bz2, main, HAVE_LIBBZ2=yes, HAVE_LIBBZ2=no)
else
AC_CHECK_LIB(bz2, BZ2_bzdopen)
AC_CHECK_LIB(bz2, BZ2_bzdopen, HAVE_LIBBZ2=yes, HAVE_LIBBZ2=no)
fi
AC_SUBST(HAVE_LIBBZ2)
AC_MSG_CHECKING(for sys/times)
AC_TRY_LINK(
@@ -120,27 +118,6 @@ AX_C_UNDERSCORES_TRAILING
AX_CPP_IDENT
# If not otherwise specified, set the libdir64 variable
# to the same as libdir.
AC_MSG_CHECKING(for libdir64 path)
if test x${libdir64} = x
then
libdir64="${libdir}"
fi
AC_SUBST(libdir64)
AC_MSG_RESULT(${libdir64})
# where to put vpi subdirectories
AC_MSG_CHECKING(for VPI subdirectories)
if test x${vpidir1} = x
then
vpidir1="."
fi
AC_SUBST(vpidir1)
AC_SUBST(vpidir2)
AC_MSG_RESULT(${vpidir1} ${vpidir2})
# XXX disable tgt-fpga for the moment
AC_CONFIG_SUBDIRS(vvp vpi tgt-stub tgt-null tgt-vvp libveriuser cadpli)
+8 -86
View File
@@ -16,16 +16,14 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: cprop.cc,v 1.56 2007/03/07 00:38:15 steve Exp $"
#endif
# include "config.h"
# include <cstdlib>
# include "netlist.h"
# include "netmisc.h"
# include "functor.h"
# include <assert.h>
# include "ivl_assert.h"
@@ -846,15 +844,17 @@ struct cprop_dc_functor : public functor_t {
void cprop_dc_functor::lpm_const(Design*des, NetConst*obj)
{
// 'bz constant values drive high impedance to whatever is
// connected to it. In other words, it is a noop.
// connected to it. In other words, it is a noop. But that is
// only true if *all* the bits of the vectors.
{ unsigned tmp = 0;
for (unsigned idx = 0 ; idx < obj->pin_count() ; idx += 1)
ivl_assert(*obj, obj->pin_count()==1);
for (unsigned idx = 0 ; idx < obj->width() ; idx += 1) {
if (obj->value(idx) == verinum::Vz) {
obj->pin(idx).unlink();
tmp += 1;
}
}
if (tmp == obj->pin_count()) {
if (tmp == obj->width()) {
delete obj;
return;
}
@@ -948,81 +948,3 @@ void cprop(Design*des)
des->functor(&dc);
}
/*
* $Log: cprop.cc,v $
* Revision 1.56 2007/03/07 00:38:15 steve
* Lint fixes.
*
* Revision 1.55 2006/05/24 04:32:57 steve
* Fix handling of ternary-to-bufif0 constant propagation.
*
* Revision 1.54 2005/07/15 19:22:52 steve
* bufif enable is LOGIC.
*
* Revision 1.53 2005/05/15 04:44:30 steve
* Disable obsolete logic constant fixup code.
*
* Revision 1.52 2005/04/24 23:44:01 steve
* Update DFF support to new data flow.
*
* Revision 1.51 2005/02/12 22:52:45 steve
* Fix copyright notice.
*
* Revision 1.50 2005/02/12 06:25:40 steve
* Restructure NetMux devices to pass vectors.
* Generate NetMux devices from ternary expressions,
* Reduce NetMux devices to bufif when appropriate.
*
* Revision 1.49 2005/01/16 04:20:32 steve
* Implement LPM_COMPARE nodes as two-input vector functors.
*
* Revision 1.48 2004/12/11 02:31:25 steve
* Rework of internals to carry vectors through nexus instead
* of single bits. Make the ivl, tgt-vvp and vvp initial changes
* down this path.
*
* Revision 1.47 2004/02/20 18:53:34 steve
* Addtrbute keys are perm_strings.
*
* Revision 1.46 2003/11/08 17:53:34 steve
* Do not remove constants accessible to VPI.
*
* Revision 1.45 2003/10/31 02:40:06 steve
* Donot elide FF that has set or clr connections.
*
* Revision 1.44 2003/04/25 05:06:32 steve
* Handle X values in constant == nets.
*
* Revision 1.43 2003/03/06 00:28:41 steve
* All NetObj objects have lex_string base names.
*
* Revision 1.42 2003/02/26 01:29:24 steve
* LPM objects store only their base names.
*
* Revision 1.41 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.40 2003/01/27 05:09:17 steve
* Spelling fixes.
*
* Revision 1.39 2002/08/20 04:12:22 steve
* Copy gate delays when doing gate delay substitutions.
*
* Revision 1.38 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.37 2002/06/25 01:33:22 steve
* Cache calculated driven value.
*
* Revision 1.36 2002/06/24 01:49:38 steve
* Make link_drive_constant cache its results in
* the Nexus, to improve cprop performance.
*
* Revision 1.35 2002/05/26 01:39:02 steve
* Carry Verilog 2001 attributes with processes,
* all the way through to the ivl_target API.
*
* Divide signal reference counts between rval
* and lval references.
*/
+79 -411
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
* Copyright (c) 1998-2008 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: design_dump.cc,v 1.176 2007/06/02 03:42:12 steve Exp $"
#endif
# include "config.h"
@@ -128,7 +125,7 @@ void NetDelaySrc::dump(ostream&o, unsigned ind) const
<< "/" << transition_delays_[IVL_PE_x0]
<< "," << transition_delays_[IVL_PE_xz]
<< "," << transition_delays_[IVL_PE_zx]
<< "): " << endl;
<< ") scope=" << scope_path(scope()) << endl;
dump_node_pins(o, ind+4);
}
@@ -282,8 +279,13 @@ void NetCompare::dump_node(ostream&o, unsigned ind) const
void NetConcat::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "NetConcat: "
<< name()
<< " scope=" << scope_path(scope())
<< name();
if (rise_time())
o << " #(" << *rise_time()
<< "," << *fall_time() << "," << *decay_time() << ")";
else
o << " #(0,0,0)";
o << " scope=" << scope_path(scope())
<< " width=" << width_ << endl;
dump_node_pins(o, ind+4);
dump_obj_attr(o, ind+4);
@@ -303,6 +305,22 @@ void NetMult::dump_node(ostream&o, unsigned ind) const
dump_obj_attr(o, ind+4);
}
void NetPow::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "LPM_POW (NetPow): " << name()
<< " scope=" << scope_path(scope())
<< " delay=(";
if (rise_time())
o << *rise_time() << "," << *fall_time() << ","
<< *decay_time();
else
o << "0,0,0";
o << ")" << endl;
dump_node_pins(o, ind+4);
dump_obj_attr(o, ind+4);
}
void NetMux::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "Multiplexer (NetMux): " << name()
@@ -336,7 +354,14 @@ void NetConst::dump_node(ostream&o, unsigned ind) const
o << setw(ind) << "" << "constant " << width_ << "'b";
for (unsigned idx = width_ ; idx > 0 ; idx -= 1)
o << value_[idx-1];
o << ": " << name() << endl;
o << ": " << name();
if (rise_time())
o << " #(" << *rise_time()
<< "," << *fall_time()
<< "," << *decay_time() << ")";
else
o << " #(.,.,.)";
o << endl;
dump_node_pins(o, ind+4);
}
@@ -353,7 +378,14 @@ void NetFF::dump_node(ostream&o, unsigned ind) const
void NetLiteral::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "constant real " << real_
<< ": " << name() << endl;
<< ": " << name();
if (rise_time())
o << " #(" << *rise_time()
<< "," << *fall_time()
<< "," << *decay_time() << ")";
else
o << " #(.,.,.)";
o << endl;
dump_node_pins(o, ind+4);
}
@@ -373,6 +405,9 @@ void NetLogic::dump_node(ostream&o, unsigned ind) const
case BUFIF1:
o << "bufif1";
break;
case CMOS:
o << "cmos";
break;
case NAND:
o << "nand";
break;
@@ -400,6 +435,9 @@ void NetLogic::dump_node(ostream&o, unsigned ind) const
case PULLUP:
o << "pullup";
break;
case RCMOS:
o << "rcmos";
break;
case RNMOS:
o << "rnmos";
break;
@@ -447,7 +485,14 @@ void NetPartSelect::dump_node(ostream&o, unsigned ind) const
break;
}
o << setw(ind) << "" << "NetPartSelect(" << pt << "): "
<< name() << " off=" << off_ << " wid=" << wid_ <<endl;
<< name();
if (rise_time())
o << " #(" << *rise_time()
<< "," << *fall_time()
<< "," << *decay_time() << ")";
else
o << " #(.,.,.)";
o << " off=" << off_ << " wid=" << wid_ <<endl;
dump_node_pins(o, ind+4);
dump_obj_attr(o, ind+4);
}
@@ -506,15 +551,20 @@ void NetUReduce::dump_node(ostream&o, unsigned ind) const
void NetSysFunc::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << def_->name << "(...)" << endl;
o << setw(ind) << "" << def_->name << "(...) -->"
<< data_type() << " width=" << vector_width() << endl;
dump_node_pins(o, ind+4);
dump_obj_attr(o, ind+4);
}
void NetUserFunc::dump_node(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << scope_path(def_) << "(";
o << ")" << endl;
o << setw(ind) << "" << "USER FUNC: "
<< scope_path(def_);
if (rise_time())
o << " #(" <<*rise_time()
<<","<<*fall_time()
<< "," <<*decay_time() << ")" << endl;
dump_node_pins(o, ind+4);
dump_obj_attr(o, ind+4);
}
@@ -562,11 +612,11 @@ void NetProcTop::dump(ostream&o, unsigned ind) const
{
switch (type_) {
case NetProcTop::KINITIAL:
o << "initial /* " << get_line() << " in "
o << "initial /* " << get_fileline() << " in "
<< scope_path(scope_) << " */" << endl;
break;
case NetProcTop::KALWAYS:
o << "always /* " << get_line() << " in "
o << "always /* " << get_fileline() << " in "
<< scope_path(scope_) << " */" << endl;
break;
}
@@ -699,7 +749,7 @@ void NetCAssign::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "cassign ";
dump_lval(o);
o << " = " << *rval() << "; /* " << get_line() << " */" << endl;
o << " = " << *rval() << "; /* " << get_fileline() << " */" << endl;
}
void NetCondit::dump(ostream&o, unsigned ind) const
@@ -721,13 +771,13 @@ void NetDeassign::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "deassign ";
dump_lval(o);
o << "; /* " << get_line() << " */" << endl;
o << "; /* " << get_fileline() << " */" << endl;
}
void NetDisable::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "disable " << scope_path(target_) << "; "
<< "/* " << get_line() << " */" << endl;
<< "/* " << get_fileline() << " */" << endl;
}
void NetEvProbe::dump_node(ostream&o, unsigned ind) const
@@ -753,7 +803,7 @@ void NetEvProbe::dump_node(ostream&o, unsigned ind) const
void NetEvTrig::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "-> " << event_->name() << "; "
<< "// " << get_line() << endl;
<< "// " << get_fileline() << endl;
}
void NetEvWait::dump(ostream&o, unsigned ind) const
@@ -766,7 +816,7 @@ void NetEvWait::dump(ostream&o, unsigned ind) const
for (unsigned idx = 1 ; idx < nevents() ; idx += 1)
o << " or " << event(idx)->name();
o << ") // " << get_line() << endl;
o << ") // " << get_fileline() << endl;
if (statement_)
statement_->dump(o, ind+2);
@@ -778,7 +828,7 @@ void NetForce::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "force ";
dump_lval(o);
o << " = " << *rval() << "; /* " << get_line() << " */" << endl;
o << " = " << *rval() << "; /* " << get_fileline() << " */" << endl;
}
void NetForever::dump(ostream&o, unsigned ind) const
@@ -789,7 +839,7 @@ void NetForever::dump(ostream&o, unsigned ind) const
void NetFuncDef::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "function " << scope_path(scope_) << endl;
o << setw(ind) << "" << "function definition for " << scope_path(scope_) << endl;
if (result_sig_)
o << setw(ind+2) << "" << "Return signal: "
<< result_sig_->name() << endl;
@@ -820,7 +870,7 @@ void NetRelease::dump(ostream&o, unsigned ind) const
{
o << setw(ind) << "" << "release ";
dump_lval(o);
o << "; /* " << get_line() << " */" << endl;
o << "; /* " << get_fileline() << " */" << endl;
}
void NetRepeat::dump(ostream&o, unsigned ind) const
@@ -902,7 +952,7 @@ void NetScope::dump(ostream&o) const
for (NetEvent*cur = events_ ; cur ; cur = cur->snext_) {
o << " event " << cur->name() << "; nprobe="
<< cur->nprobe() << " scope=" << scope_path(cur->scope())
<< " // " << cur->get_line() << endl;
<< " // " << cur->get_fileline() << endl;
}
// Dump the signals,
@@ -943,7 +993,10 @@ void NetScope::dump(ostream&o) const
o << " MISSING FUNCTION DEFINITION" << endl;
break;
case TASK:
task_def()->dump(o, 4);
if (task_def())
task_def()->dump(o, 4);
else
o << " MISSING TASK DEFINITION" << endl;
break;
default:
break;
@@ -1210,6 +1263,7 @@ void Design::dump(ostream&o) const
if (nodes_) {
NetNode*cur = nodes_->node_next_;
do {
assert(cur);
cur->dump_node(o, 0);
cur = cur->node_next_;
} while (cur != nodes_->node_next_);
@@ -1222,389 +1276,3 @@ void Design::dump(ostream&o) const
idx->dump(o, 0);
}
/*
* $Log: design_dump.cc,v $
* Revision 1.176 2007/06/02 03:42:12 steve
* Properly evaluate scope path expressions.
*
* Revision 1.175 2007/05/24 04:07:11 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.174 2007/03/02 06:13:22 steve
* Add support for edge sensitive spec paths.
*
* Revision 1.173 2007/02/01 03:14:33 steve
* Detect and report arrays without index in net contexts.
*
* Revision 1.172 2007/01/16 05:44:14 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.171 2006/10/30 05:44:49 steve
* Expression widths with unsized literals are pseudo-infinite width.
*
* Revision 1.170 2006/10/03 05:06:00 steve
* Support real valued specify delays, properly scaled.
*
* Revision 1.169 2006/09/26 19:48:40 steve
* Missing PSpec.cc file.
*
* Revision 1.168 2006/09/23 04:57:19 steve
* Basic support for specify timing.
*
* Revision 1.167 2006/07/31 03:50:17 steve
* Add support for power in constant expressions.
*
* Revision 1.166 2006/06/18 04:15:50 steve
* Add support for system functions in continuous assignments.
*
* Revision 1.165 2006/04/10 00:37:42 steve
* Add support for generate loops w/ wires and gates.
*
* Revision 1.164 2006/02/02 02:43:57 steve
* Allow part selects of memory words in l-values.
*
* Revision 1.163 2005/08/27 04:32:08 steve
* Handle synthesis of fully packed case statements.
*
* Revision 1.162 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.161 2005/07/07 16:22:49 steve
* Generalize signals to carry types.
*
* Revision 1.160 2005/05/24 01:44:27 steve
* Do sign extension of structuran nets.
*
* Revision 1.159 2005/05/17 20:56:55 steve
* Parameters cannot have their width changed.
*
* Revision 1.158 2005/05/07 03:13:30 steve
* Include delay expressions for assignments in dump.
*
* Revision 1.157 2005/03/09 05:52:03 steve
* Handle case inequality in netlists.
*
* Revision 1.156 2005/02/08 00:12:36 steve
* Add the NetRepeat node, and code generator support.
*
* Revision 1.155 2005/02/03 04:56:20 steve
* laborate reduction gates into LPM_RED_ nodes.
*
* Revision 1.154 2005/01/24 05:28:30 steve
* Remove the NetEBitSel and combine all bit/part select
* behavior into the NetESelect node and IVL_EX_SELECT
* ivl_target expression type.
*
* Revision 1.153 2005/01/22 18:16:00 steve
* Remove obsolete NetSubnet class.
*
* Revision 1.152 2005/01/09 20:16:00 steve
* Use PartSelect/PV and VP to handle part selects through ports.
*
* Revision 1.151 2004/12/29 23:55:43 steve
* Unify elaboration of l-values for all proceedural assignments,
* including assing, cassign and force.
*
* Generate NetConcat devices for gate outputs that feed into a
* vector results. Use this to hande gate arrays. Also let gate
* arrays handle vectors of gates when the outputs allow for it.
*
* Revision 1.150 2004/12/11 02:31:25 steve
* Rework of internals to carry vectors through nexus instead
* of single bits. Make the ivl, tgt-vvp and vvp initial changes
* down this path.
*
* Revision 1.149 2004/10/04 01:10:52 steve
* Clean up spurious trailing white space.
*
* Revision 1.148 2004/05/31 23:34:36 steve
* Rewire/generalize parsing an elaboration of
* function return values to allow for better
* speed and more type support.
*
* Revision 1.147 2004/02/20 06:22:56 steve
* parameter keys are per_strings.
*
* Revision 1.146 2004/02/18 17:11:54 steve
* Use perm_strings for named langiage items.
*
* Revision 1.145 2003/12/17 16:52:39 steve
* Debug dumps for synth2.
*
* Revision 1.144 2003/07/26 03:34:42 steve
* Start handling pad of expressions in code generators.
*
* Revision 1.143 2003/07/05 20:42:08 steve
* Fix some enumeration warnings.
*
* Revision 1.142 2003/06/20 00:53:19 steve
* Module attributes from the parser
* through to elaborated form.
*
* Revision 1.141 2003/06/18 03:55:18 steve
* Add arithmetic shift operators.
*
* Revision 1.140 2003/05/30 02:55:32 steve
* Support parameters in real expressions and
* as real expressions, and fix multiply and
* divide with real results.
*
* Revision 1.139 2003/04/22 04:48:29 steve
* Support event names as expressions elements.
*
* Revision 1.138 2003/03/10 23:40:53 steve
* Keep parameter constants for the ivl_target API.
*
* Revision 1.137 2003/01/27 05:09:17 steve
* Spelling fixes.
*
* Revision 1.136 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions.
*
* Revision 1.135 2002/10/23 01:47:17 steve
* Fix synth2 handling of aset/aclr signals where
* flip-flops are split by begin-end blocks.
*
* Revision 1.134 2002/10/19 22:59:49 steve
* Redo the parameter vector support to allow
* parameter names in range expressions.
*
* Revision 1.133 2002/08/19 00:06:11 steve
* Allow release to handle removal of target net.
*
* Revision 1.132 2002/08/13 05:35:00 steve
* Do not elide named blocks.
*
* Revision 1.131 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.130 2002/08/04 18:28:14 steve
* Do not use hierarchical names of memories to
* generate vvp labels. -tdll target does not
* used hierarchical name string to look up the
* memory objects in the design.
*
* Revision 1.129 2002/06/19 04:20:03 steve
* Remove NetTmp and add NetSubnet class.
*
* Revision 1.128 2002/06/14 21:38:41 steve
* Fix expression width for repeat concatenations.
*
* Revision 1.127 2002/06/08 23:42:46 steve
* Add NetRamDq synthsesis from memory l-values.
*
* Revision 1.126 2002/06/05 03:44:25 steve
* Add support for memory words in l-value of
* non-blocking assignments, and remove the special
* NetAssignMem_ and NetAssignMemNB classes.
*
* Revision 1.125 2002/06/04 05:38:44 steve
* Add support for memory words in l-value of
* blocking assignments, and remove the special
* NetAssignMem class.
*
* Revision 1.124 2002/05/26 01:39:02 steve
* Carry Verilog 2001 attributes with processes,
* all the way through to the ivl_target API.
*
* Divide signal reference counts between rval
* and lval references.
*
* Revision 1.123 2002/05/05 21:11:49 steve
* Put off evaluation of concatenation repeat expresions
* until after parameters are defined. This allows parms
* to be used in repeat expresions.
*
* Add the builtin $signed system function.
*
* Revision 1.122 2002/03/09 02:10:22 steve
* Add the NetUserFunc netlist node.
*
* Revision 1.121 2001/12/31 00:03:05 steve
* Include s indicator in dump of signed numbers.
*
* Revision 1.120 2001/12/03 04:47:14 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
* Revision 1.119 2001/11/19 01:46:38 steve
* Print typename is fallback expression node dump.
*
* Revision 1.118 2001/10/19 21:53:24 steve
* Support multiple root modules (Philip Blundell)
*
* Revision 1.117 2001/08/25 23:50:02 steve
* Change the NetAssign_ class to refer to the signal
* instead of link into the netlist. This is faster
* and uses less space. Make the NetAssignNB carry
* the delays instead of the NetAssign_ lval objects.
*
* Change the vvp code generator to support multiple
* l-values, i.e. concatenations of part selects.
*
* Revision 1.116 2001/07/27 04:51:44 steve
* Handle part select expressions as variants of
* NetESignal/IVL_EX_SIGNAL objects, instead of
* creating new and useless temporary signals.
*
* Revision 1.115 2001/07/27 02:41:55 steve
* Fix binding of dangling function ports. do not elide them.
*
* Revision 1.114 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.113 2001/04/29 20:19:10 steve
* Add pullup and pulldown devices.
*
* Revision 1.112 2001/04/22 23:09:46 steve
* More UDP consolidation from Stephan Boettcher.
*
* Revision 1.111 2001/02/17 05:13:36 steve
* Check that the port really exists here.
*
* Revision 1.110 2001/01/18 03:16:35 steve
* NetMux needs a scope. (PR#115)
*
* Revision 1.109 2001/01/13 22:20:08 steve
* Parse parameters within nested scopes.
*
* Revision 1.108 2000/12/16 01:45:47 steve
* Detect recursive instantiations (PR#2)
*
* Revision 1.107 2000/12/11 00:31:43 steve
* Add support for signed reg variables,
* simulate in t-vvm signed comparisons.
*
* Revision 1.106 2000/12/10 06:41:59 steve
* Support delays on continuous assignment from idents. (PR#40)
*
* Revision 1.105 2000/12/04 17:37:03 steve
* Add Attrib class for holding NetObj attributes.
*
* Revision 1.104 2000/11/11 01:52:09 steve
* change set for support of nmos, pmos, rnmos, rpmos, notif0, and notif1
* change set to correct behavior of bufif0 and bufif1
* (Tim Leight)
*
* Also includes fix for PR#27
*
* Revision 1.103 2000/11/11 00:03:36 steve
* Add support for the t-dll backend grabing flip-flops.
*
* Revision 1.102 2000/11/04 06:36:24 steve
* Apply sequential UDP rework from Stephan Boettcher (PR#39)
*
* Revision 1.101 2000/10/28 00:51:41 steve
* Add scope to threads in vvm, pass that scope
* to vpi sysTaskFunc objects, and add vpi calls
* to access that information.
*
* $display displays scope in %m (PR#1)
*
* Revision 1.100 2000/10/07 19:45:42 steve
* Put logic devices into scopes.
*
* Revision 1.99 2000/10/06 23:46:50 steve
* ivl_target updates, including more complete
* handling of ivl_nexus_t objects. Much reduced
* dependencies on pointers to netlist objects.
*
* Revision 1.98 2000/09/26 01:35:42 steve
* Remove the obsolete NetEIdent class.
*
* Revision 1.97 2000/09/17 21:26:15 steve
* Add support for modulus (Eric Aardoom)
*
* Revision 1.96 2000/09/10 02:18:16 steve
* elaborate complex l-values
*
* Revision 1.95 2000/09/02 20:54:20 steve
* Rearrange NetAssign to make NetAssign_ separate.
*
* Revision 1.94 2000/07/30 18:25:43 steve
* Rearrange task and function elaboration so that the
* NetTaskDef and NetFuncDef functions are created during
* signal enaboration, and carry these objects in the
* NetScope class instead of the extra, useless map in
* the Design class.
*
* Revision 1.93 2000/07/29 03:55:38 steve
* fix problem coalescing events w/ probes.
*
* Revision 1.92 2000/07/27 05:13:44 steve
* Support elaboration of disable statements.
*
* Revision 1.91 2000/07/22 22:09:03 steve
* Parse and elaborate timescale to scopes.
*
* Revision 1.90 2000/07/14 06:12:57 steve
* Move inital value handling from NetNet to Nexus
* objects. This allows better propogation of inital
* values.
*
* Clean up constant propagation a bit to account
* for regs that are not really values.
*
* Revision 1.89 2000/07/07 04:53:53 steve
* Add support for non-constant delays in delay statements,
* Support evaluating ! in constant expressions, and
* move some code from netlist.cc to net_proc.cc.
*
* Revision 1.88 2000/06/25 19:59:42 steve
* Redesign Links to include the Nexus class that
* carries properties of the connected set of links.
*
* Revision 1.87 2000/06/24 22:55:19 steve
* Get rid of useless next_link method.
*
* Revision 1.86 2000/06/13 03:24:48 steve
* Index in memory assign should be a NetExpr.
*
* Revision 1.85 2000/05/11 23:37:27 steve
* Add support for procedural continuous assignment.
*
* Revision 1.84 2000/05/07 18:20:07 steve
* Import MCD support from Stephen Tell, and add
* system function parameter support to the IVL core.
*
* Revision 1.83 2000/05/07 04:37:56 steve
* Carry strength values from Verilog source to the
* pform and netlist for gates.
*
* Change vvm constants to use the driver_t to drive
* a constant value. This works better if there are
* multiple drivers on a signal.
*
* Revision 1.82 2000/05/04 03:37:58 steve
* Add infrastructure for system functions, move
* $time to that structure and add $random.
*
* Revision 1.81 2000/05/02 03:13:30 steve
* Move memories to the NetScope object.
*
* Revision 1.80 2000/05/02 00:58:11 steve
* Move signal tables to the NetScope class.
*
* Revision 1.79 2000/04/28 21:00:29 steve
* Over agressive signal elimination in constant probadation.
*
* Revision 1.78 2000/04/23 03:45:24 steve
* Add support for the procedural release statement.
*
* Revision 1.77 2000/04/22 04:20:19 steve
* Add support for force assignment.
*
* Revision 1.76 2000/04/12 20:02:52 steve
* Finally remove the NetNEvent and NetPEvent classes,
* Get synthesis working with the NetEvWait class,
* and get started supporting multiple events in a
* wait in vvm.
*/
+10 -4
View File
@@ -16,16 +16,17 @@
# 59 Temple Place - Suite 330
# Boston, MA 02111-1307, USA
#
#ident "$Id: Makefile.in,v 1.7 2004/10/13 22:01:34 steve Exp $"
#ident "$Id: Makefile.in,v 1.7.2.1 2006/10/04 17:08:59 steve Exp $"
#
#
SHELL = /bin/sh
VERSION = 0.8
VERSION = 0.8.3
prefix = @prefix@
exec_prefix = @exec_prefix@
srcdir = @srcdir@
datarootdir = @datarootdir@
VPATH = $(srcdir)
@@ -48,7 +49,7 @@ LDFLAGS = @LDFLAGS@
all: iverilog-vpi@EXEEXT@
clean:
rm -f *.o
rm -f *.o config.h
rm -f iverilog-vpi@EXEEXT@
distclean: clean
@@ -60,9 +61,14 @@ iverilog-vpi@EXEEXT@: $O
$(CC) $(LDFLAGS) $O -o iverilog-vpi@EXEEXT@ @EXTRALIBS@
main.o: main.c
main.o: main.c config.h
$(CC) $(CPPFLAGS) $(CFLAGS) -c $(srcdir)/main.c
config.h: config.h.in
sed -e 's;@IVLCC@;@CC@;' -e 's;@IVLCXX@;@CXX@;' \
-e 's;@IVLCFLAGS@;@CXXFLAGS@;' \
-e 's;@SHARED@;@shared@;' $< > $@
# Windows specific...
res.o: res.rc
windres -i res.rc -o res.o
+8
View File
@@ -0,0 +1,8 @@
/* For now do not put the Icarus Verilog include or library paths here.
* They are generated from a registry entry the user must set (-ivl=).
* This may change in the future once I have thought about it more. */
#define IVERILOG_VPI_CC "@IVLCC@"
#define IVERILOG_VPI_CXX "@IVLCXX@"
#define IVERILOG_VPI_CFLAGS " @IVLCFLAGS@"
#define IVERILOG_VPI_LDFLAGS "@SHARED@"
#define IVERILOG_VPI_LDLIBS "-lveriuser -lvpi"
+179 -107
View File
@@ -32,28 +32,28 @@
#include <windows.h>
/* Macros used for compiling and linking */
static void setup_ivl_environment();
static void assign(char **ptr, char *str);
#define IVERILOG_VPI_CC "gcc" /* no .exe extension */
#define IVERILOG_VPI_CXX "gcc" /* no .exe extension */
#define IVERILOG_VPI_CFLAGS "-O" /* -I appended later */
#define IVERILOG_VPI_LD "gcc" /* no .exe extension */
#define IVERILOG_VPI_LDFLAGS "-shared -Wl,--enable-auto-image-base"
#define IVERILOG_VPI_LDLIBS "-lveriuser -lvpi" /* -L prepended later */
/* The compile options: compiler, flags, etc. are in here */
#include "config.h"
/* pointers to global strings */
static struct global_strings {
char *pCCSRC; /* list of C source files */
char *pCXSRC; /* list of C++ source files */
char *pCCSRC; /* list of C source files (*.c) */
char *pCXSRC; /* list of C++ source files (*.cc, *.cpp) */
char *pOBJ; /* list of object files */
char *pLIB; /* list of library files */
char *pINCS; /* list of include directories */
char *pDEFS; /* list of definitions */
char *pOUT; /* output file name (.vpi extension), if 0 length then no source files specified */
char *pMINGW; /* path to MinGW directory */
char *pIVL; /* path to IVL directory */
char *pCFLAGS; /* CFLAGS option */
char *pLDLIBS; /* LDLIBS option */
char *pNewPath; /* new PATH environment variable setting */
char *pLD; /* what to use for a linker */
} gstr;
@@ -70,12 +70,15 @@ static void myExit(int exitVal)
deInitDynString(gstr.pCXSRC);
deInitDynString(gstr.pOBJ);
deInitDynString(gstr.pLIB);
deInitDynString(gstr.pINCS);
deInitDynString(gstr.pDEFS);
deInitDynString(gstr.pOUT);
deInitDynString(gstr.pMINGW);
deInitDynString(gstr.pIVL);
deInitDynString(gstr.pCFLAGS);
deInitDynString(gstr.pLDLIBS);
deInitDynString(gstr.pNewPath);
free(gstr.pLD);
exit(exitVal);
}
@@ -84,7 +87,7 @@ static void myExit(int exitVal)
static void usage()
{
fprintf(stderr,"usage: iverilog-vpi [--name=name] [-llibrary] [-mingw=dir] [-ivl=dir] sourcefile...\n");
fprintf(stderr,"usage: iverilog-vpi [src and obj files]...\n");
fprintf(stderr," or iverilog-vpi -mingw=dir\n");
fprintf(stderr," or iverilog-vpi -ivl=dir\n");
myExit(1);
@@ -110,12 +113,16 @@ static void init()
initDynString(&gstr.pCXSRC);
initDynString(&gstr.pOBJ);
initDynString(&gstr.pLIB);
initDynString(&gstr.pINCS);
initDynString(&gstr.pDEFS);
initDynString(&gstr.pOUT);
initDynString(&gstr.pMINGW);
initDynString(&gstr.pIVL);
initDynString(&gstr.pCFLAGS);
initDynString(&gstr.pLDLIBS);
initDynString(&gstr.pNewPath);
/* By default use the C compiler to link the programs. */
assign(&gstr.pLD, IVERILOG_VPI_CC);
}
/* return true if "str" is terminated with with "end", case insensitive */
@@ -281,67 +288,120 @@ static int parse(int argc, char *argv[])
char dot_o_ext[] = ".o";
char name_option[] = "--name=";
char lib_option[] = "-l";
char inc_option[] = "-I";
char mingw_option[] = "-mingw=";
char ivl_option[] = "-ivl=";
char def_option[] = "-D";
if (argc == 1)
return 0;
if (argc == 1) return 0;
for (idx=1; idx<argc; ++idx) {
if (endsIn(dot_c_ext,argv[idx])) { /* check for C source files */
/* Check for C source files (*.c) */
if (endsIn(dot_c_ext, argv[idx])) {
++srcFileCnt;
append(&gstr.pCCSRC,argv[idx]);
append(&gstr.pCCSRC," ");
append(&gstr.pCCSRC, argv[idx]);
append(&gstr.pCCSRC, " ");
if (!*gstr.pOUT)
assignn(&gstr.pOUT,argv[idx],strlen(argv[idx])-strlen(dot_c_ext));
assignn(&gstr.pOUT, argv[idx],
strlen(argv[idx])-strlen(dot_c_ext));
}
else if (endsIn(dot_cc_ext,argv[idx])) { /* check for C++ source files */
/* Check for C++ source files (*.cc) */
else if (endsIn(dot_cc_ext, argv[idx])) {
/* We need to link with the C++ compiler. */
assign(&gstr.pLD, IVERILOG_VPI_CXX);
++srcFileCnt;
append(&gstr.pCXSRC,argv[idx]);
append(&gstr.pCXSRC," ");
append(&gstr.pCXSRC, argv[idx]);
append(&gstr.pCXSRC, " ");
if (!*gstr.pOUT)
assignn(&gstr.pOUT,argv[idx],strlen(argv[idx])-strlen(dot_cc_ext));
assignn(&gstr.pOUT, argv[idx],
strlen(argv[idx])-strlen(dot_cc_ext));
}
else if (endsIn(dot_cpp_ext,argv[idx])) { /* check for C++ source files */
/* Check for C++ source files (*.cpp) */
else if (endsIn(dot_cpp_ext, argv[idx])) {
/* We need to link with the C++ compiler. */
assign(&gstr.pLD, IVERILOG_VPI_CXX);
++srcFileCnt;
append(&gstr.pCXSRC,argv[idx]);
append(&gstr.pCXSRC," ");
append(&gstr.pCXSRC, argv[idx]);
append(&gstr.pCXSRC, " ");
if (!*gstr.pOUT)
assignn(&gstr.pOUT,argv[idx],strlen(argv[idx])-strlen(dot_cpp_ext));
assignn(&gstr.pOUT, argv[idx],
strlen(argv[idx])-strlen(dot_cpp_ext));
}
else if (endsIn(dot_o_ext,argv[idx])) { /* check for compiled object files */
/* Check for compiled object files */
else if (endsIn(dot_o_ext, argv[idx])) {
++srcFileCnt;
append(&gstr.pOBJ,argv[idx]);
append(&gstr.pOBJ," ");
append(&gstr.pOBJ, argv[idx]);
if (!*gstr.pOUT)
assignn(&gstr.pOUT,argv[idx],strlen(argv[idx])-strlen(dot_o_ext));
assignn(&gstr.pOUT, argv[idx],
strlen(argv[idx])-strlen(dot_o_ext));
}
else if (startsWith(name_option,argv[idx])) { /* check for --name option */
assignn(&gstr.pOUT,argv[idx]+sizeof(name_option)-1,strlen(argv[idx])-(sizeof(name_option)-1));
/* Check for the --name option */
else if (startsWith(name_option, argv[idx])) {
assignn(&gstr.pOUT, argv[idx]+sizeof(name_option)-1,
strlen(argv[idx])-(sizeof(name_option)-1));
}
else if (startsWith(lib_option,argv[idx])) { /* check for -l option */
append(&gstr.pLIB,argv[idx]);
append(&gstr.pLIB," ");
/* Check for the -l option */
else if (startsWith(lib_option, argv[idx])) {
append(&gstr.pLIB, " ");
append(&gstr.pLIB, argv[idx]);
}
else if (startsWith(mingw_option,argv[idx])) /* check for -mingw option */
assignn(&gstr.pMINGW,argv[idx]+sizeof(mingw_option)-1,strlen(argv[idx])-(sizeof(mingw_option)-1));
else if (startsWith(ivl_option,argv[idx])) /* check for -ivl option */
assignn(&gstr.pIVL,argv[idx]+sizeof(ivl_option)-1,strlen(argv[idx])-(sizeof(ivl_option)-1));
else
return 0; /* different from iverilog-vpi.sh, we don't ignore accept arguments */
/* Check for the -I option */
else if (startsWith(inc_option, argv[idx])) {
append(&gstr.pINCS, " ");
append(&gstr.pINCS, argv[idx]);
}
/* Check for the -D option */
else if (startsWith(def_option, argv[idx])) {
append(&gstr.pDEFS, " ");
append(&gstr.pDEFS, argv[idx]);
}
/* Check for the -mingw option */
else if (startsWith(mingw_option, argv[idx]))
assignn(&gstr.pMINGW, argv[idx]+sizeof(mingw_option)-1,
strlen(argv[idx])-(sizeof(mingw_option)-1));
/* Check for the -ivl option */
else if (startsWith(ivl_option, argv[idx]))
assignn(&gstr.pIVL, argv[idx]+sizeof(ivl_option)-1,
strlen(argv[idx])-(sizeof(ivl_option)-1));
/* Check for the --cflags option */
else if (stricmp("--cflags", argv[idx]) == 0) {
setup_ivl_environment();
printf("%s\n", gstr.pCFLAGS);
myExit(0);
}
/* Check for the --ldflags option */
else if (stricmp("--ldflags", argv[idx]) == 0) {
printf("%s\n", IVERILOG_VPI_LDFLAGS);
myExit(0);
}
/* Check for the --ldlibs option */
else if (stricmp("--ldlibs", argv[idx]) == 0) {
setup_ivl_environment();
printf("%s\n", gstr.pLDLIBS);
myExit(0);
}
/* Check for the --install-dir option */
else if (stricmp("--install-dir", argv[idx]) == 0) {
setup_ivl_environment();
printf("%s\\\\lib\\\\ivl\\\\.\n", gstr.pIVL);
myExit(0);
}
/* This is different than iverilog-vpi.sh, we don't
* ignore unknown arguments */
else return 0;
}
if (0 == srcFileCnt)
assign(&gstr.pOUT,""); /* in case they used --name with no source files */
/* In case there is a --name without source/object files */
if (0 == srcFileCnt) assign(&gstr.pOUT,"");
if (!*gstr.pOUT) { /* normally it's an error if there are no *.c,*.cc,*.o files */
if (!*gstr.pMINGW && !*gstr.pIVL) /* unless they are just setting the IVL or MinGW registry entries */
usage();
}
else {
append(&gstr.pOUT,".vpi"); /* the result file should have a .vpi extension */
append(&gstr.pOUT," ");
}
/* Normally it's an error if there are no source or object files */
/* Unless we are setting the IVL or MinGW registry entries */
if (!*gstr.pOUT) {
if (!*gstr.pMINGW && !*gstr.pIVL) return 0;
} else
/* We have a valid result file so add the .vpi extension */
append(&gstr.pOUT, ".vpi");
return 1;
}
@@ -411,9 +471,7 @@ static void setup_mingw_environment()
if (*gstr.pMINGW) {
checkMingwDir(gstr.pMINGW);
SetRegistryKey(IVL_REGKEY_MINGW,gstr.pMINGW);
}
else
if (!GetRegistryKey(IVL_REGKEY_MINGW,&gstr.pMINGW)) {
} else if (!GetRegistryKey(IVL_REGKEY_MINGW,&gstr.pMINGW)) {
fprintf(stderr,"error: can not locate the MinGW root directory, use the -mingw option of\n");
fprintf(stderr," iverilog-vpi.exe to point to the MinGW root directory. For\n");
fprintf(stderr," a Windows command shell the option would be something like\n");
@@ -422,13 +480,16 @@ static void setup_mingw_environment()
myExit(5);
}
assign(&gstr.pNewPath,"PATH="); /* create new path */
/* Create new path with MinGW in it */
assign(&gstr.pNewPath,"PATH=");
append(&gstr.pNewPath,gstr.pMINGW);
appendBackSlash(&gstr.pNewPath);
append(&gstr.pNewPath, "\\");
append(&gstr.pNewPath,"bin;");
append(&gstr.pNewPath,pOldPATH);
_putenv(gstr.pNewPath); /* place new path in environment variable */
/* Place new path in environment */
_putenv(gstr.pNewPath);
}
/* see if we can find iverilog root */
@@ -440,9 +501,7 @@ static void setup_ivl_environment()
if (*gstr.pIVL) {
checkIvlDir(gstr.pIVL);
SetRegistryKey(IVL_REGKEY_IVL,gstr.pIVL);
}
else
if (!GetRegistryKey(IVL_REGKEY_IVL,&gstr.pIVL)) {
} else if (!GetRegistryKey(IVL_REGKEY_IVL,&gstr.pIVL)) {
fprintf(stderr,"error: can not locate the Icarus Verilog root directory, use the -ivl option\n");
fprintf(stderr," of iverilog-vpi.exe to point to the Icarus Verilog root directory.\n");
fprintf(stderr," For a Windows command shell the option would be something like\n");
@@ -451,56 +510,68 @@ static void setup_ivl_environment()
myExit(6);
}
/* build up the CFLAGS option string */
/* Build up the CFLAGS option string */
assign(&gstr.pCFLAGS,IVERILOG_VPI_CFLAGS);
append(&gstr.pCFLAGS," -I");
append(&gstr.pCFLAGS,gstr.pIVL);
appendBackSlash(&gstr.pCFLAGS);
append(&gstr.pCFLAGS, "\\");
append(&gstr.pCFLAGS,"include");
/* build up the LDFLAGS option string */
/* Build up the LDFLAGS option string */
assign(&gstr.pLDLIBS,"-L");
append(&gstr.pLDLIBS,gstr.pIVL);
appendBackSlash(&gstr.pLDLIBS);
append(&gstr.pLDLIBS, "\\");
append(&gstr.pLDLIBS,"lib ");
append(&gstr.pLDLIBS,IVERILOG_VPI_LDLIBS);
}
/* compile source modules */
static void compile(char *pSource, char **pObject, char *ext, int *compile_errors, char *compiler)
static void compile(char *pSource, char **pObject, int *compile_errors, char *compiler)
{
char *ptr1 = pSource;
char *ptr2 = strchr(pSource,' ');
char *buf=0,*src=0,*obj=0;
char *ptr2 = strchr(ptr1, ' ');
char *buf=0, *src=0, *obj=0;
while (ptr2) {
int len = ptr2 - ptr1;
assignn(&src,ptr1,len);
char *ostart;
int olen;
assignn(&src, ptr1, len);
assignn(&obj,ptr1,len-strlen(ext)); /* strip off the extension */
append (&obj,".o");
/* Build the object file name */
ostart = strrchr(ptr1, '/');
if (ostart == NULL) ostart = ptr1;
else ostart += 1;
olen = strrchr(ptr1, '.') - ostart;
assignn(&obj, ostart, olen);
append(&obj, ".o");
assign (&buf,compiler);
append (&buf," -c -o ");
append (&buf,obj);
append (&buf," ");
append (&buf,gstr.pCFLAGS);
append (&buf," ");
append (&buf,src);
/* Build the compile line */
assign(&buf, compiler);
append(&buf, " -c -o ");
append(&buf, obj);
append(&buf, " ");
append(&buf, gstr.pDEFS);
append(&buf, " ");
append(&buf, gstr.pCFLAGS);
append(&buf, " ");
append(&buf, gstr.pINCS);
append(&buf, " ");
append(&buf, src);
append (pObject,obj);
append (pObject," ");
append (pObject, " ");
append (pObject, obj);
printf("%s\n",buf);
printf("Compiling %s...\n", src);
if (system(buf))
++*compile_errors;
if (system(buf)) ++*compile_errors;
ptr1 = ptr2 + 1; /* advance to next token */
ptr2 = strchr(ptr1,' ');
/* advance to next token */
ptr1 = ptr2 + 1;
ptr2 = strchr(ptr1, ' ');
}
free(buf);
@@ -515,43 +586,44 @@ static void compile_and_link()
char *buf=0;
int iRet, compile_errors = 0;
/* print out the mingw and ivl directories to help the user debug problems */
/* To make the output match iverilog-vpi.sh do not print out the
* root directories */
printf("info: %s will be used as the MinGW root directory.\n",gstr.pMINGW);
// printf("MinGW root directory: %s.\n", gstr.pMINGW);
checkMingwDir(gstr.pMINGW);
printf("info: %s will be used as the Icarus Verilog root directory.\n",gstr.pIVL);
// printf("Icarus Verilog root directory: %s.\n", gstr.pIVL);
checkIvlDir(gstr.pIVL);
/* compile */
compile(gstr.pCCSRC,&gstr.pOBJ,".c" ,&compile_errors,IVERILOG_VPI_CC ); /* compile the C source files */
compile(gstr.pCXSRC,&gstr.pOBJ,".cc",&compile_errors,IVERILOG_VPI_CXX); /* compile the C++ source files */
/* compile the C source files (*.c) */
compile(gstr.pCCSRC, &gstr.pOBJ, &compile_errors, IVERILOG_VPI_CC );
/* compile the C++ source files (*.cc, *.cpp) */
compile(gstr.pCXSRC, &gstr.pOBJ, &compile_errors, IVERILOG_VPI_CXX);
if (compile_errors) {
fprintf(stderr,"iverilog-vpi: Some %d files failed to compile.\n",compile_errors);
fprintf(stderr,"iverilog-vpi: %d file(s) failed to compile.\n",
compile_errors);
myExit(2);
}
/* link */
/* link */
assign(&buf, gstr.pLD);
append(&buf, " -o ");
append(&buf, gstr.pOUT);
append(&buf, " ");
append(&buf, IVERILOG_VPI_LDFLAGS);
append(&buf, " ");
append(&buf, gstr.pOBJ);
append(&buf, " ");
append(&buf, gstr.pLIB);
append(&buf, " ");
append(&buf, gstr.pLDLIBS);
assign(&buf,IVERILOG_VPI_LD);
append(&buf," -o ");
append(&buf,gstr.pOUT); /* has a trailing space */
append(&buf,IVERILOG_VPI_LDFLAGS);
append(&buf," ");
append(&buf,gstr.pOBJ) /* has a trailing space */;
append(&buf,gstr.pLIB); /* has a trailing space */
append(&buf,gstr.pLDLIBS);
printf("%s\n",buf);
printf("Making %s from %s...\n", gstr.pOUT,gstr.pOBJ);
iRet = system(buf);
free(buf);
if (iRet)
myExit(3);
if (iRet) myExit(3);
}
/* program execution starts here */
@@ -560,14 +632,14 @@ int main(int argc, char *argv[])
{
init();
if (!parse(argc,argv))
usage();
if (!parse(argc,argv)) usage();
setup_mingw_environment();
setup_ivl_environment();
if (*gstr.pOUT) /* are there any *.c,*.cc,*.o files specified */
compile_and_link();
/* are there any source or object files specified */
if (*gstr.pOUT) compile_and_link();
myExit(0);
return 0; // eliminate warnings.
}
+1
View File
@@ -26,6 +26,7 @@ VERSION = 0.8
prefix = @prefix@
exec_prefix = @exec_prefix@
srcdir = @srcdir@
datarootdir = @datarootdir@
VPATH = $(srcdir)
+81 -16
View File
@@ -1,4 +1,7 @@
%option nounput
%option noinput
%{
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
@@ -27,17 +30,21 @@
# include "globals.h"
# include <string.h>
/*
* Lexical location information is passed in the yylloc variable to th
* parser. The file names, strings, are kept in a list so that I can
* re-use them. The set_file_name function will return a pointer to
* the name as it exists in the list (and delete the passed string.)
* If the name is new, it will be added to the list.
*/
YYLTYPE yylloc;
static int comment_enter;
static char* trim_trailing_white(char*txt, int trim);
static char* trim_trailing_white(char*txt, int trim);
/*
* Mostly copied from the flex manual. Do not make this arbitrary
* depth without checking for looping files.
*/
#define MAX_CMDFILE_DEPTH 15
typedef struct t_cmdfile {
char *cmdfile;
YY_BUFFER_STATE buffer;
} s_cmdfile;
s_cmdfile cmdfile_stack[MAX_CMDFILE_DEPTH];
int cmdfile_stack_ptr = 0;
%}
@@ -51,12 +58,12 @@ static int comment_enter;
/* Accept C++ style comments. */
"//".* { comment_enter = YY_START; BEGIN(LCOMMENT); }
<LCOMMENT>. { yymore(); }
<LCOMMENT>\n { yylloc.first_line += 1; BEGIN(comment_enter); }
<LCOMMENT>\n { cflloc.first_line += 1; BEGIN(comment_enter); }
/* Accept C style comments. */
"/*" { comment_enter = YY_START; BEGIN(CCOMMENT); }
<CCOMMENT>. { yymore(); }
<CCOMMENT>\n { yylloc.first_line += 1; yymore(); }
<CCOMMENT>\n { cflloc.first_line += 1; yymore(); }
<CCOMMENT>"*/" { BEGIN(comment_enter); }
/* Accept shell type comments. */
@@ -65,7 +72,7 @@ static int comment_enter;
/* Skip white space. */
[ \t\f\r] { ; }
/* Skip line ends, but also count the line. */
\n { yylloc.first_line += 1; }
\n { cflloc.first_line += 1; }
"+define+" { BEGIN(PLUS_ARGS); return TOK_DEFINE; }
@@ -100,12 +107,16 @@ static int comment_enter;
<PLUS_ARGS>[ \t\b\f\r] { BEGIN(0); }
<PLUS_ARGS>\n {
yylloc.first_line += 1;
cflloc.first_line += 1;
BEGIN(0); }
/* Notice the -a flag. */
"-a" { return TOK_Da; }
/* Notice the -c or -f flag. */
"-c" { return TOK_Dc; }
"-f" { return TOK_Dc; }
/* Notice the -v flag. */
"-v" { return TOK_Dv; }
@@ -142,6 +153,18 @@ static int comment_enter;
/* Fallback match. */
. { return yytext[0]; }
/* At the end of file switch back to the previous buffer. */
<<EOF>> {
if (--cmdfile_stack_ptr < 0) {
free(current_file);
yyterminate();
} else {
yy_delete_buffer(YY_CURRENT_BUFFER);
yy_switch_to_buffer(cmdfile_stack[cmdfile_stack_ptr].buffer);
free(current_file);
current_file = cmdfile_stack[cmdfile_stack_ptr].cmdfile;
} }
%%
static char* trim_trailing_white(char*text, int trim)
@@ -164,10 +187,52 @@ int yywrap()
return 1;
}
void switch_to_command_file(const char *file)
{
char path[4096];
char *cp;
if (cmdfile_stack_ptr >= MAX_CMDFILE_DEPTH) {
fprintf(stderr, "Error: command files nested too deeply (%d) "
"at %s:%d.\n", MAX_CMDFILE_DEPTH, current_file,
cflloc.first_line);
exit(1);
}
cmdfile_stack[cmdfile_stack_ptr].buffer = YY_CURRENT_BUFFER;
cmdfile_stack[cmdfile_stack_ptr].cmdfile = current_file;
cmdfile_stack_ptr += 1;
/*
* If this is a relative file then add the current path to the
* file name.
*/
if (file[0] != '/') {
strcpy(path, current_file);
cp = strrchr(path, '/');
if (cp == 0) strcpy(path, file); /* A base file. */
else {
*(cp+1) = '\0';
strcat(path, file);
}
} else strcpy(path, file); /* An absolute path. */
yyin = fopen(path, "r");
if (yyin == NULL) {
fprintf(stderr, "Error: unable to read nested command file (%s) "
"at %s:%d.\n", path, current_file, cflloc.first_line);
exit(1);
}
current_file = strdup(path);
yy_switch_to_buffer(yy_create_buffer(yyin, YY_BUF_SIZE));
cflloc.first_line = 1;
}
void cfreset(FILE*fd, const char*path)
{
yyin = fd;
yyrestart(fd);
yylloc.first_line = 1;
yylloc.text = (char*)path;
current_file = strdup(path);
cflloc.first_line = 1;
}
+17 -1
View File
@@ -60,7 +60,7 @@ static void translate_file_name(char*text)
char*text;
};
%token TOK_Da TOK_Dv TOK_Dy
%token TOK_Da TOK_Dc TOK_Dv TOK_Dy
%token TOK_DEFINE TOK_INCDIR TOK_LIBDIR TOK_LIBDIR_NOCASE TOK_LIBEXT
%token TOK_INTEGER_WIDTH
%token <text> TOK_PLUSARG TOK_PLUSWORD TOK_STRING
@@ -93,6 +93,16 @@ item
| TOK_Da { }
/* Match a -c <cmdfile> or -f <cmdfile> */
| TOK_Dc TOK_STRING
{ char*tmp = substitutions($2);
translate_file_name(tmp);
switch_to_command_file(tmp);
free($2);
free(tmp);
}
/* The -v <libfile> flag is ignored, and the <libfile> is processed
as an ordinary source file. */
@@ -173,6 +183,12 @@ item
}
free($1);
}
| error
{ fprintf(stderr, "Error: unable to parse line %d in "
"%s.\n", cflloc.first_line, current_file);
return 1;
}
;
/* inc_args are +incdir+ arguments in order. */
+2 -26
View File
@@ -19,9 +19,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: cfparse_misc.h,v 1.6 2004/02/15 18:03:30 steve Exp $"
#endif
/*
* The vlltype supports the passing of detailed source file location
@@ -36,32 +33,11 @@ struct cfltype {
const char*text;
};
# define YYLTYPE struct cfltype
extern YYLTYPE yylloc;
int cflex(void);
int cferror(const char *);
int cfparse(void);
void switch_to_command_file(const char *);
char *current_file;
/*
* $Log: cfparse_misc.h,v $
* Revision 1.6 2004/02/15 18:03:30 steve
* Cleanup of warnings.
*
* Revision 1.5 2003/09/26 21:25:58 steve
* Warnings cleanup.
*
* Revision 1.4 2002/08/12 01:35:01 steve
* conditional ident string using autoconfig.
*
* Revision 1.3 2002/01/02 02:39:34 steve
* Use my own cfltype to defend against bison 1.30.
*
* Revision 1.2 2001/11/12 18:47:32 steve
* Support +incdir in command files, and ignore other
* +args flags. Also ignore -a and -v flags.
*
* Revision 1.1 2001/11/12 01:26:36 steve
* More sophisticated command file parser.
*
*/
#endif
+2 -2
View File
@@ -31,10 +31,10 @@ extern const char*base;
extern char* iconfig_path;
extern char* iconfig_common_path;
/* Ths is the optional -M<dependfile> value, if one was supplied. */
/* This is the optional -M<dependfile> value, if one was supplied. */
extern const char*depfile;
/* Ths is the optional -N<path> value, if one was supplied. */
/* This is the optional -N<path> value, if one was supplied. */
extern const char*npath;
/* This is the name of the output file that the user selected. */
+44 -7
View File
@@ -4,7 +4,8 @@ iverilog - Icarus Verilog compiler
.SH SYNOPSIS
.B iverilog
[-ESVv] [-Bpath] [-ccmdfile] [-g1|-g2|-g2x|-gspecify-gxtypes] [-Dmacro[=defn]] [-pflag=value]
[-ESVv] [-Bpath] [-ccmdfile|-fcmdfile] [-Dmacro[=defn]] [-pflag=value]
[-dname] [-g1|-g2|-g2x|-gspecify|-gxtypes|-gio-range-error]
[-Iincludedir] [-mmodule] [-Mfile] [-Nfile] [-ooutputfilename]
[-stopmodule] [-ttype] [-Tmin/typ/max] [-Wclass] [-ypath] sourcefile
@@ -28,8 +29,8 @@ program. However, the \fB-B\fP switch allows the user to select a
different set of programs. The path given is used to locate
\fIivlpp\fP, \fIivl\fP, code generators and the VPI modules.
.TP 8
.B -c\fIfile\fP
This flag specifies an input file that contains a list of Verilog
.B -c\fIfile\fP -f\fIfile\fP
These flags specifies an input file that contains a list of Verilog
source files. This is similar to the \fIcommand file\fP of other
Verilog simulators, in that it is a file that contains the file names
instead of taking them on the command line. See \fBCommand Files\fP below.
@@ -42,6 +43,12 @@ Verilog source.
.B -D\fImacro=defn\fP
Defines macro \fImacro\fP as \fIdefn\fP.
.TP 8
.B -d\fIname\fP
Activate a class of compiler debugging messages. The \fB-d\fP switch may
be used as often as necessary to activate all the desired messages.
Supported names are scopes, eval_tree, elaborate, and synth2;
any other names are ignored.
.TP 8
.B -E
Preprocess the Verilog source, but do not compile it. The output file
is the Verilog input, but with file inclusions and macro references
@@ -65,6 +72,12 @@ simulation, and in fact can hurt performance of the
simulation. However, disabling specify blocks reduces accuracy of
full-timing simulations.
.TP 8
.B -gstd-include\fI|\fP-gno-std-include
Enable (default) or disable the search of a standard installation
include directory after all other explicit include directories. This
standard include directory is a convenient place to install standard
header files that a Verilog program may include.
.TP 8
.B -gxtypes\fI|\fP-gno-xtypes
Enable (default) or disable support for extended types. Enabling
extended types allows for new types that are supported by Icarus
@@ -72,6 +85,15 @@ Verilog as extensions beyond the baseline Verilog. It may be necessary
to disable extended types if compiling code that clashes with the few
new keywords used to implement the type system.
.TP 8
.B -gio-range-error\fI|\fP-gno-io-range-error
The standards requires that a vectored port have matching ranges for its
port declaration as well as any net/register declaration. It was common
practice in the past to only specify the range for the net/register
declaration and some tools still allow this. By default any mismatch is
reported as a error. Using \fI-gno-io-range-error\fP will produce a
warning instead of a fatal error for the case of a vectored net/register
and a scalar port declaration.
.TP 8
.B -I\fIincludedir\fP
Append directory \fIincludedir\fP to list of directories searched
for Verilog include files. The \fB-I\fP switch may be used many times
@@ -125,9 +147,9 @@ they will be used as root modules instead.
.B -T\fImin|typ|max\fP
Use this switch to select min, typ or max times from min:typ:max
expressions. Normally, the compiler will simply use the typ value from
these expressions (with a warning) but this switch will tell the
compiler explicitly which value to use. This will suppress the
warning that the compiler is making a choice.
these expressions (printing a warning for the first ten it finds) but
this switch will tell the compiler explicitly which value to use. This
will suppress the warning that the compiler is making a choice.
.TP 8
.B -t\fItarget\fP
Use this switch to specify the target output format. See the
@@ -268,6 +290,12 @@ A simple file name or file path is taken to be the name of a Verilog
source file. The path starts with the first non-white-space
character. Variables are substituted in file names.
.TP 8
.B -c\ \fIcmdfile\fP -f\ \fIcmdfile\fP
A \fB-c\fP or \fB-f\fP token prefixes a command file, exactly like it
does on the command line. The cmdfile may be on the same line or the
next non-comment line.
.TP 8
.B -y\ \fIlibdir\fP
A \fB-y\fP token prefixes a library directory in the command file,
@@ -339,6 +367,12 @@ and directory strings.
Variable values come from the operating system environment, and not
from preprocessor defines elsewhere in the file or the command line.
.SH PREDEFINED MACROS
The following macro is predefined by the compiler:
.TP 8
.B __ICARUS__ = 1\fP
.SH EXAMPLES
These examples assume that you have a Verilog source file called hello.v in
the current directory
@@ -368,9 +402,12 @@ Steve Williams ([email protected])
vvp(1),
.BR "<http://www.icarus.com/eda/verilog/>"
Tips on using, debugging, and developing the compiler can be found at
.BR "<http://iverilog.wikia.com/>"
.SH COPYRIGHT
.nf
Copyright \(co 2002 Stephen Williams
Copyright \(co 2002-2008 Stephen Williams
This document can be freely redistributed according to the terms of the
GNU General Public License version 2.0
+77 -120
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2000-2005 Stephen Williams ([email protected])
* Copyright (c) 2000-2007 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: main.c,v 1.76 2007/06/05 01:56:12 steve Exp $"
#endif
# include "config.h"
@@ -39,12 +36,13 @@ const char NOTICE[] =
;
const char HELP[] =
"Usage: iverilog [-ESvV] [-B base] [-c cmdfile] [-g1|-g2|-g2x]\n"
"Usage: iverilog [-ESvV] [-B base] [-c cmdfile|-f cmdfile] [-g1|-g2|-g2x]\n"
" [-D macro[=defn]] [-I includedir] [-M depfile] [-m module]\n"
" [-N file] [-o filename] [-p flag=value]\n"
" [-s topmodule] [-t target] [-T min|typ|max]\n"
" [-W class] [-y dir] [-Y suf] source_file(s)\n"
"See man page for details.";
"\n"
"See the man page for details.";
#define MAXSIZE 4096
@@ -110,6 +108,10 @@ const char*depfile = 0;
const char*generation = "2x";
const char*gen_specify = "specify";
const char*gen_xtypes = "xtypes";
const char*gen_io_range_error = "io-range-error";
/* Boolean: true means use a default include dir, false means don't */
int gen_std_include = 1;
char warning_flags[16] = "";
@@ -131,6 +133,8 @@ FILE*defines_file = 0;
char*iconfig_path = 0;
FILE*iconfig_file = 0;
char*compiled_defines_path = 0;
static char iconfig_common_path_buf[4096] = "";
char*iconfig_common_path = iconfig_common_path_buf;
@@ -152,7 +156,7 @@ typedef struct t_command_file {
p_command_file cmd_file_head = NULL; /* The FIFO head */
p_command_file cmd_file_tail = NULL; /* The FIFO tail */
/* Function to add a comamnd file name to the FIFO. */
/* Function to add a command file name to the FIFO. */
void add_cmd_file(const char* filename)
{
p_command_file new;
@@ -169,7 +173,7 @@ void add_cmd_file(const char* filename)
}
}
/* Function to return the top comamnd file name from the FIFO. */
/* Function to return the top command file name from the FIFO. */
char *get_cmd_file()
{
char *filename;
@@ -198,7 +202,7 @@ static FILE*fopen_safe(const char*path)
if (fd != -1)
file = _fdopen(fd, "w");
return file;
return file;
}
#else
# include <fcntl.h>
@@ -211,7 +215,7 @@ static FILE*fopen_safe(const char*path)
if (fd != -1)
file = fdopen(fd, "w");
return file;
return file;
}
#endif
@@ -318,6 +322,7 @@ static int t_default(char*cmd, unsigned ncmd)
remove(source_path);
remove(iconfig_path);
remove(defines_path);
remove(compiled_defines_path);
}
if (rc != 0) {
@@ -340,31 +345,32 @@ static int t_default(char*cmd, unsigned ncmd)
static void process_warning_switch(const char*name)
{
if (strcmp(name,"all") == 0) {
strcat(warning_flags, "ipt");
process_warning_switch("implicit");
process_warning_switch("portbind");
process_warning_switch("timescale");
} else if (strcmp(name,"implicit") == 0) {
if (! strchr(warning_flags+2, 'i'))
if (! strchr(warning_flags, 'i'))
strcat(warning_flags, "i");
} else if (strcmp(name,"portbind") == 0) {
if (! strchr(warning_flags+2, 'p'))
if (! strchr(warning_flags, 'p'))
strcat(warning_flags, "p");
} else if (strcmp(name,"timescale") == 0) {
if (! strchr(warning_flags+2, 't'))
if (! strchr(warning_flags, 't'))
strcat(warning_flags, "t");
} else if (strcmp(name,"no-implicit") == 0) {
char*cp = strchr(warning_flags+2, 'i');
char*cp = strchr(warning_flags, 'i');
if (cp) while (*cp) {
cp[0] = cp[1];
cp += 1;
}
} else if (strcmp(name,"no-portbind") == 0) {
char*cp = strchr(warning_flags+2, 'p');
char*cp = strchr(warning_flags, 'p');
if (cp) while (*cp) {
cp[0] = cp[1];
cp += 1;
}
} else if (strcmp(name,"no-timescale") == 0) {
char*cp = strchr(warning_flags+2, 't');
char*cp = strchr(warning_flags, 't');
if (cp) while (*cp) {
cp[0] = cp[1];
cp += 1;
@@ -430,25 +436,39 @@ int process_generation(const char*name)
else if (strcmp(name,"xtypes") == 0)
gen_xtypes = "xtypes";
else if (strcmp(name,"no-xtypes") == 0)
else if (strcmp(name,"no-xtypes") == 0)
gen_xtypes = "no-xtypes";
else if (strcmp(name,"specify") == 0)
else if (strcmp(name,"specify") == 0)
gen_specify = "specify";
else if (strcmp(name,"no-specify") == 0)
else if (strcmp(name,"no-specify") == 0)
gen_specify = "no-specify";
else if (strcmp(name,"std-include") == 0)
gen_std_include = 1;
else if (strcmp(name,"no-std-include") == 0)
gen_std_include = 0;
else if (strcmp(name,"io-range-error") == 0)
gen_io_range_error = "io-range-error";
else if (strcmp(name,"no-io-range-error") == 0)
gen_io_range_error = "no-io-range-error";
else {
fprintf(stderr, "Unknown/Unsupported Language generation "
"%s\n", name);
"%s\n\n", name);
fprintf(stderr, "Supported generations are:\n");
fprintf(stderr, " 1 -- IEEE1364-1995 (Verilog 1)\n"
" 2 -- IEEE1364-2001 (Verilog 2001)\n"
" 2x -- Verilog with extensions\n"
"Other generation flags:\n"
" specify | no-specify\n"
" xtypes | no-xtypes\n");
" std-include | no-std-include\n"
" xtypes | no-xtypes\n"
" io-range-error | no-io-range-error\n");
return 1;
}
@@ -564,7 +584,16 @@ int main(int argc, char **argv)
return 1;
}
while ((opt = getopt(argc, argv, "B:c:D:Ef:g:hI:M:m:N::o:p:Ss:T:t:vVW:y:Y:")) != EOF) {
/* Create a temporary file (I only really need the path) that
can carry preprocessor precompiled defines to the library. */
{ FILE*tmp_file = 0;
compiled_defines_path = strdup(my_tempfile("ivrli", &tmp_file));
if (tmp_file) {
fclose(tmp_file);
}
}
while ((opt = getopt(argc, argv, "B:c:D:d:Ef:g:hI:M:m:N::o:p:Ss:T:t:vVW:y:Y:")) != EOF) {
switch (opt) {
case 'B':
@@ -578,7 +607,8 @@ int main(int argc, char **argv)
base=optarg;
}
break;
case 'c':
case 'c':
case 'f':
add_cmd_file(optarg);
break;
case 'D':
@@ -587,11 +617,12 @@ int main(int argc, char **argv)
case 'E':
e_flag = 1;
break;
case 'f':
fprintf(stderr, "warning: The -f flag is moved to -p\n");
case 'p':
fprintf(iconfig_file, "flag:%s\n", optarg);
break;
case 'd':
fprintf(iconfig_file, "debug:%s\n", optarg);
break;
case 'g':
rc = process_generation(optarg);
@@ -670,8 +701,8 @@ int main(int argc, char **argv)
pbase = base;
if (version_flag || verbose_flag) {
printf("Icarus Verilog version " VERSION " ($Name: $)\n");
printf("Copyright 1998-2003 Stephen Williams\n");
printf("Icarus Verilog version " VERSION " ($Name: $)\n\n");
printf("Copyright 1998-2007 Stephen Williams\n");
puts(NOTICE);
if (version_flag)
@@ -694,6 +725,7 @@ int main(int argc, char **argv)
fprintf(iconfig_file, "generation:%s\n", generation);
fprintf(iconfig_file, "generation:%s\n", gen_specify);
fprintf(iconfig_file, "generation:%s\n", gen_xtypes);
fprintf(iconfig_file, "generation:%s\n", gen_io_range_error);
fprintf(iconfig_file, "warnings:%s\n", warning_flags);
fprintf(iconfig_file, "out:%s\n", opath);
if (depfile) fprintf(iconfig_file, "depfile:%s\n", depfile);
@@ -702,16 +734,16 @@ int main(int argc, char **argv)
int rc;
if (( fp = fopen(command_filename, "r")) == NULL ) {
fprintf(stderr, "%s: Can't open %s\n",
argv[0], command_filename);
fprintf(stderr, "%s: cannot open command file %s "
"for reading.\n", argv[0], command_filename);
return 1;
}
cfreset(fp, command_filename);
rc = cfparse();
if (rc != 0) {
fprintf(stderr, "%s: error reading command file\n",
command_filename);
fprintf(stderr, "%s: parsing failed in base command "
"file %s.\n", argv[0], command_filename);
return 1;
}
free(command_filename);
@@ -726,6 +758,12 @@ int main(int argc, char **argv)
for (idx = optind ; idx < argc ; idx += 1)
process_file_name(argv[idx], 0);
/* If the use of a default include directory is not
specifically disabled, then write that directory as the
very last include directory to use... always. */
if (gen_std_include) {
fprintf(defines_file, "I:%s%cinclude", base, sep);
}
fclose(source_file);
source_file = 0;
@@ -734,17 +772,17 @@ int main(int argc, char **argv)
defines_file = 0;
if (source_count == 0) {
fprintf(stderr, "%s: No input files.\n", argv[0]);
fprintf(stderr, "%s\n", HELP);
fprintf(stderr, "%s: no source files.\n\n%s\n", argv[0], HELP);
return 1;
}
/* Start building the preprocess command line. */
sprintf(tmp, "%s%civlpp %s%s -F%s -f%s ", pbase,sep,
sprintf(tmp, "%s%civlpp %s%s -F%s -f%s -p%s ", pbase,sep,
verbose_flag?" -v":"",
e_flag?"":" -L", defines_path, source_path);
e_flag?"":" -L", defines_path, source_path,
compiled_defines_path);
ncmd = strlen(tmp);
cmd = malloc(ncmd + 1);
@@ -789,8 +827,8 @@ int main(int argc, char **argv)
/* Write the preprocessor command needed to preprocess a
single file. This may be used to preprocess library
files. */
fprintf(iconfig_file, "ivlpp:%s%civlpp -L -F%s\n",
pbase, sep, defines_path);
fprintf(iconfig_file, "ivlpp:%s%civlpp -L -F%s -P%s\n",
pbase, sep, defines_path, compiled_defines_path);
/* Done writing to the iconfig file. Close it now. */
fclose(iconfig_file);
@@ -800,84 +838,3 @@ int main(int argc, char **argv)
return 0;
}
/*
* $Log: main.c,v $
* Revision 1.76 2007/06/05 01:56:12 steve
* Bring in .SFT file automatically if -m used.
*
* Revision 1.75 2007/04/19 02:52:53 steve
* Add support for -v flag in command file.
*
* Revision 1.74 2007/04/18 03:23:38 steve
* Add support for multiple command files. (Cary R.)
*
* Revision 1.73 2007/03/07 04:24:59 steve
* Make integer width controllable.
*
* Revision 1.72 2006/10/02 18:15:47 steve
* Fix handling of dep path in new argument passing method.
*
* Revision 1.71 2006/09/28 04:35:18 steve
* Support selective control of specify and xtypes features.
*
* Revision 1.70 2006/09/20 22:30:52 steve
* Do not pass -D__ICARUS__ to ivlpp.
*
* Revision 1.69 2006/07/26 00:11:40 steve
* Pass depfiles through temp defines file.
*
* Revision 1.68 2006/07/26 00:02:48 steve
* Pass defines and includes through temp file.
*
* Revision 1.67 2005/07/14 23:38:44 steve
* Display as version 0.9.devel
*
* Revision 1.66 2005/06/28 04:25:55 steve
* Remove reference to SystemVerilog.
*
* Revision 1.65 2004/06/17 14:47:22 steve
* Add a .sft file for the system functions.
*
* Revision 1.64 2004/03/10 04:51:25 steve
* Add support for system function table files.
*
* Revision 1.63 2004/02/15 18:03:30 steve
* Cleanup of warnings.
*
* Revision 1.62 2003/12/12 04:36:48 steve
* Fix make check to support -tconf configuration method.
*
* Revision 1.61 2003/11/18 06:31:46 steve
* Remove the iverilog.conf file.
*
* Revision 1.60 2003/11/13 05:55:33 steve
* Move the DLL= flag to target config files.
*
* Revision 1.59 2003/11/13 04:09:49 steve
* Pass flags through the temporary config file.
*
* Revision 1.58 2003/11/01 04:21:57 steve
* Add support for a target static config file.
*
* Revision 1.57 2003/10/26 22:43:42 steve
* Improve -V messages,
*
* Revision 1.56 2003/09/26 21:25:58 steve
* Warnings cleanup.
*
* Revision 1.55 2003/09/23 05:57:15 steve
* Pass -m flag from driver via iconfig file.
*
* Revision 1.54 2003/09/22 01:12:09 steve
* Pass more ivl arguments through the iconfig file.
*
* Revision 1.53 2003/08/26 16:26:02 steve
* ifdef idents correctly.
*
* Revision 1.52 2003/02/22 04:55:36 steve
* portbind adds p, not i, flag.
*
* Revision 1.51 2003/02/22 04:12:49 steve
* Add the portbind warning.
*/
+24 -86
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1999-2002 Stephen Williams ([email protected])
* Copyright (c) 1999-2008 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: dup_expr.cc,v 1.21 2006/11/04 06:10:13 steve Exp $"
#endif
# include "config.h"
@@ -27,14 +24,17 @@
NetEBComp* NetEBComp::dup_expr() const
{
NetEBComp*result = new NetEBComp(op_, left_->dup_expr(),
right_->dup_expr());
return result;
NetEBComp*tmp = new NetEBComp(op_, left_->dup_expr(),
right_->dup_expr());
assert(tmp);
tmp->set_line(*this);
return tmp;
}
NetEConst* NetEConst::dup_expr() const
{
NetEConst*tmp = new NetEConst(value_);
assert(tmp);
tmp->set_line(*this);
return tmp;
}
@@ -42,6 +42,7 @@ NetEConst* NetEConst::dup_expr() const
NetEConstParam* NetEConstParam::dup_expr() const
{
NetEConstParam*tmp = new NetEConstParam(scope_, name_, value());
assert(tmp);
tmp->set_line(*this);
return tmp;
}
@@ -49,6 +50,7 @@ NetEConstParam* NetEConstParam::dup_expr() const
NetECRealParam* NetECRealParam::dup_expr() const
{
NetECRealParam*tmp = new NetECRealParam(scope_, name_, value());
assert(tmp);
tmp->set_line(*this);
return tmp;
}
@@ -67,9 +69,12 @@ NetEScope* NetEScope::dup_expr() const
NetESelect* NetESelect::dup_expr() const
{
return new NetESelect(expr_->dup_expr(),
base_? base_->dup_expr() : 0,
expr_width());
NetESelect*tmp = new NetESelect(expr_->dup_expr(),
base_? base_->dup_expr() : 0,
expr_width());
assert(tmp);
tmp->set_line(*this);
return tmp;
}
NetESFunc* NetESFunc::dup_expr() const
@@ -83,14 +88,16 @@ NetESFunc* NetESFunc::dup_expr() const
tmp->parm(idx, tmp->parm(idx)->dup_expr());
}
tmp->set_line(*this);
return tmp;
}
NetESignal* NetESignal::dup_expr() const
{
NetESignal*tmp = new NetESignal(net_);
NetESignal*tmp = new NetESignal(net_, word_);
assert(tmp);
tmp->expr_width(expr_width());
tmp->set_line(*this);
return tmp;
}
@@ -99,6 +106,8 @@ NetETernary* NetETernary::dup_expr() const
NetETernary*tmp = new NetETernary(cond_->dup_expr(),
true_val_->dup_expr(),
false_val_->dup_expr());
assert(tmp);
tmp->set_line(*this);
return tmp;
}
@@ -112,9 +121,10 @@ NetEUFunc* NetEUFunc::dup_expr() const
tmp_parms[idx] = parms_[idx]->dup_expr();
}
tmp = new NetEUFunc(func_, result_sig_->dup_expr(), tmp_parms);
tmp = new NetEUFunc(scope_, func_, result_sig_->dup_expr(), tmp_parms);
assert(tmp);
tmp->set_line(*this);
return tmp;
}
@@ -122,6 +132,7 @@ NetEUnary* NetEUnary::dup_expr() const
{
NetEUnary*tmp = new NetEUnary(op_, expr_->dup_expr());
assert(tmp);
tmp->set_line(*this);
return tmp;
}
@@ -129,79 +140,6 @@ NetEUReduce* NetEUReduce::dup_expr() const
{
NetEUReduce*tmp = new NetEUReduce(op_, expr_->dup_expr());
assert(tmp);
tmp->set_line(*this);
return tmp;
}
/*
* $Log: dup_expr.cc,v $
* Revision 1.21 2006/11/04 06:10:13 steve
* Handle dup of pad as well as normal select.
*
* Revision 1.20 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.19 2004/12/11 02:31:25 steve
* Rework of internals to carry vectors through nexus instead
* of single bits. Make the ivl, tgt-vvp and vvp initial changes
* down this path.
*
* Revision 1.18 2004/06/17 16:06:18 steve
* Help system function signedness survive elaboration.
*
* Revision 1.17 2004/05/31 23:34:36 steve
* Rewire/generalize parsing an elaboration of
* function return values to allow for better
* speed and more type support.
*
* Revision 1.16 2003/10/31 02:47:11 steve
* NetEUReduce has its own dup_expr method.
*
* Revision 1.15 2003/05/30 02:55:32 steve
* Support parameters in real expressions and
* as real expressions, and fix multiply and
* divide with real results.
*
* Revision 1.14 2003/04/22 04:48:29 steve
* Support event names as expressions elements.
*
* Revision 1.13 2003/03/15 18:08:43 steve
* Comparison operators do have defined width.
*
* Revision 1.12 2003/03/15 04:46:28 steve
* Better organize the NetESFunc return type guesses.
*
* Revision 1.11 2003/03/10 23:40:53 steve
* Keep parameter constants for the ivl_target API.
*
* Revision 1.10 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions.
*
* Revision 1.9 2002/11/09 00:25:27 steve
* Add dup_expr for user defined function calls.
*
* Revision 1.8 2002/08/12 01:34:58 steve
* conditional ident string using autoconfig.
*
* Revision 1.7 2002/01/28 00:52:41 steve
* Add support for bit select of parameters.
* This leads to a NetESelect node and the
* vvp code generator to support that.
*
* Revision 1.6 2001/11/19 01:54:14 steve
* Port close cropping behavior from mcrgb
* Move window array reset to libmc.
*
* Revision 1.5 2001/07/25 03:10:48 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.4 2000/05/07 18:20:07 steve
* Import MCD support from Stephen Tell, and add
* system function parameter support to the IVL core.
*
* Revision 1.3 2000/05/04 03:37:58 steve
* Add infrastructure for system functions, move
* $time to that structure and add $random.
*/
+260 -372
View File
File diff suppressed because it is too large Load Diff
+45 -132
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2000-2006 Stephen Williams (steve@icarus.com)
* Copyright (c) 2000-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: elab_lval.cc,v 1.44 2007/06/02 03:42:12 steve Exp $"
#endif
# include "config.h"
@@ -26,7 +23,9 @@
# include "netlist.h"
# include "netmisc.h"
# include "compiler.h"
# include <cstdlib>
# include <iostream>
# include <climits>
# include "ivl_assert.h"
/*
@@ -34,7 +33,7 @@
* assignment. This is common code for the = and <= statements.
*
* What gets generated depends on the structure of the l-value. If the
* l-value is a simple name (i.e., foo <= <value>) the the NetAssign_
* l-value is a simple name (i.e., foo <= <value>) then the NetAssign_
* is created the width of the foo reg and connected to all the
* bits.
*
@@ -73,7 +72,7 @@ NetAssign_* PExpr::elaborate_lval(Design*des,
{
NetNet*ll = 0;
if (ll == 0) {
cerr << get_line() << ": Assignment l-value too complex."
cerr << get_fileline() << ": Assignment l-value too complex."
<< endl;
return 0;
}
@@ -100,7 +99,7 @@ NetAssign_* PEConcat::elaborate_lval(Design*des,
bool is_force) const
{
if (repeat_) {
cerr << get_line() << ": error: Repeat concatenations make "
cerr << get_fileline() << ": error: Repeat concatenations make "
"no sense in l-value expressions. I refuse." << endl;
des->errors += 1;
return 0;
@@ -111,7 +110,7 @@ NetAssign_* PEConcat::elaborate_lval(Design*des,
for (unsigned idx = 0 ; idx < parms_.count() ; idx += 1) {
if (parms_[idx] == 0) {
cerr << get_line() << ": error: Empty expressions "
cerr << get_fileline() << ": error: Empty expressions "
<< "not allowed in concatenations." << endl;
des->errors += 1;
continue;
@@ -155,7 +154,7 @@ NetAssign_* PEIdent::elaborate_lval(Design*des,
symbol_search(des, scope, path_, reg, par, eve);
if (reg == 0) {
cerr << get_line() << ": error: Could not find variable ``"
cerr << get_fileline() << ": error: Could not find variable ``"
<< path_ << "'' in ``" << scope_path(scope) <<
"''" << endl;
@@ -174,7 +173,7 @@ NetAssign_* PEIdent::elaborate_lval(Design*des,
// This is the special case that the l-value is an entire
// memory. This is, in fact, an error.
if (reg->array_dimensions() > 0 && name_tail.index.empty()) {
cerr << get_line() << ": error: Cannot assign to array "
cerr << get_fileline() << ": error: Cannot assign to array "
<< path_ << ". Did you forget a word index?" << endl;
des->errors += 1;
return 0;
@@ -189,15 +188,10 @@ NetAssign_* PEIdent::elaborate_lval(Design*des,
return lv;
}
if (use_sel == index_component_t::SEL_IDX_UP) {
if (use_sel == index_component_t::SEL_IDX_UP ||
use_sel == index_component_t::SEL_IDX_DO) {
NetAssign_*lv = new NetAssign_(reg);
elaborate_lval_net_idx_up_(des, scope, lv);
return lv;
}
if (use_sel == index_component_t::SEL_IDX_DO) {
NetAssign_*lv = new NetAssign_(reg);
elaborate_lval_net_idx_do_(des, scope, lv);
elaborate_lval_net_idx_(des, scope, lv, use_sel);
return lv;
}
@@ -205,10 +199,10 @@ NetAssign_* PEIdent::elaborate_lval(Design*des,
it is a register. Wires are not allows in this context,
unless this is the l-value of a force. */
if ((reg->type() != NetNet::REG) && !is_force) {
cerr << get_line() << ": error: " << path_ <<
cerr << get_fileline() << ": error: " << path_ <<
" is not a valid l-value in " << scope_path(scope) <<
"." << endl;
cerr << reg->get_line() << ": : " << path_ <<
cerr << reg->get_fileline() << ": : " << path_ <<
" is declared here as " << reg->type() << "." << endl;
des->errors += 1;
return 0;
@@ -285,7 +279,7 @@ NetAssign_* PEIdent::elaborate_lval(Design*des,
unsigned wid = moff - loff + 1;
if (moff < loff) {
cerr << get_line() << ": error: part select "
cerr << get_fileline() << ": error: part select "
<< reg->name() << "[" << msb<<":"<<lsb<<"]"
<< " is reversed." << endl;
des->errors += 1;
@@ -298,7 +292,7 @@ NetAssign_* PEIdent::elaborate_lval(Design*des,
variable pins. */
if ((wid + loff) > reg->vector_width()) {
cerr << get_line() << ": error: bit/part select "
cerr << get_fileline() << ": error: bit/part select "
<< reg->name() << "[" << msb<<":"<<lsb<<"]"
<< " is out of range." << endl;
des->errors += 1;
@@ -321,6 +315,13 @@ NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
ivl_assert(*this, !name_tail.index.empty());
const index_component_t&index_head = name_tail.index.front();
if (index_head.sel == index_component_t::SEL_PART) {
cerr << get_fileline() << ": error: cannot perform a part "
<< "select on array " << reg->name() << "." << endl;
des->errors += 1;
return 0;
}
ivl_assert(*this, index_head.sel == index_component_t::SEL_BIT);
ivl_assert(*this, index_head.msb != 0);
ivl_assert(*this, index_head.lsb == 0);
@@ -332,16 +333,14 @@ NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
if (long base = reg->array_first()) {
word = make_add_expr(word, 0-base);
if (NetExpr*tmp = word->eval_tree()) {
word = tmp;
}
eval_expr(word);
}
NetAssign_*lv = new NetAssign_(reg);
lv->set_word(word);
if (debug_elaborate)
cerr << get_line() << ": debug: Set array word=" << *word << endl;
cerr << get_fileline() << ": debug: Set array word=" << *word << endl;
// Test for the case that the index is a constant, and is out
// of bounds. The "word" expression is the word index already
@@ -350,8 +349,9 @@ NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
if (NetEConst*word_const = dynamic_cast<NetEConst*>(word)) {
verinum word_val = word_const->value();
long index = word_val.as_long();
if (index < 0 || index >= reg->array_count()) {
cerr << get_line() << ": warning: Constant array index "
assert (reg->array_count() <= LONG_MAX);
if (index < 0 || index >= (long) reg->array_count()) {
cerr << get_fileline() << ": warning: Constant array index "
<< (index + reg->array_first())
<< " is out of range for array "
<< reg->name() << "." << endl;
@@ -367,11 +367,9 @@ NetAssign_* PEIdent::elaborate_lval_net_word_(Design*des,
if (use_sel == index_component_t::SEL_PART)
elaborate_lval_net_part_(des, scope, lv);
if (use_sel == index_component_t::SEL_IDX_UP)
elaborate_lval_net_idx_up_(des, scope, lv);
if (use_sel == index_component_t::SEL_IDX_DO)
elaborate_lval_net_idx_do_(des, scope, lv);
if (use_sel == index_component_t::SEL_IDX_UP ||
use_sel == index_component_t::SEL_IDX_DO)
elaborate_lval_net_idx_(des, scope, lv, use_sel);
return lv;
}
@@ -403,7 +401,7 @@ bool PEIdent::elaborate_lval_net_part_(Design*des,
unsigned wid = moff - loff + 1;
if (moff < loff) {
cerr << get_line() << ": error: part select "
cerr << get_fileline() << ": error: part select "
<< reg->name() << "[" << msb<<":"<<lsb<<"]"
<< " is reversed." << endl;
des->errors += 1;
@@ -416,7 +414,7 @@ bool PEIdent::elaborate_lval_net_part_(Design*des,
variable pins. */
if ((wid + loff) > reg->vector_width()) {
cerr << get_line() << ": error: bit/part select "
cerr << get_fileline() << ": error: bit/part select "
<< reg->name() << "[" << msb<<":"<<lsb<<"]"
<< " is out of range." << endl;
des->errors += 1;
@@ -429,9 +427,10 @@ bool PEIdent::elaborate_lval_net_part_(Design*des,
return true;
}
bool PEIdent::elaborate_lval_net_idx_up_(Design*des,
NetScope*scope,
NetAssign_*lv) const
bool PEIdent::elaborate_lval_net_idx_(Design*des,
NetScope*scope,
NetAssign_*lv,
index_component_t::ctype_t use_sel) const
{
const name_component_t&name_tail = path_.back();;
ivl_assert(*this, !name_tail.index.empty());
@@ -444,10 +443,10 @@ bool PEIdent::elaborate_lval_net_idx_up_(Design*des,
assert(reg);
if (reg->type() != NetNet::REG) {
cerr << get_line() << ": error: " << path_ <<
cerr << get_fileline() << ": error: " << path_ <<
" is not a reg/integer/time in " << scope_path(scope) <<
"." << endl;
cerr << reg->get_line() << ": : " << path_ <<
cerr << reg->get_fileline() << ": : " << path_ <<
" is declared here as " << reg->type() << "." << endl;
des->errors += 1;
return false;
@@ -464,8 +463,12 @@ bool PEIdent::elaborate_lval_net_idx_up_(Design*des,
else if (reg->lsb() != 0)
base = make_add_expr(base, - reg->lsb());
if (use_sel == index_component_t::SEL_IDX_DO && wid > 1 ) {
base = make_add_expr(base, 1-(long)wid);
}
if (debug_elaborate)
cerr << get_line() << ": debug: Set part select width="
cerr << get_fileline() << ": debug: Set part select width="
<< wid << ", base=" << *base << endl;
lv->set_part(base, wid);
@@ -473,100 +476,10 @@ bool PEIdent::elaborate_lval_net_idx_up_(Design*des,
return true;
}
bool PEIdent::elaborate_lval_net_idx_do_(Design*des,
NetScope*scope,
NetAssign_*lv) const
{
const name_component_t&name_tail = path_.back();;
ivl_assert(*this, !name_tail.index.empty());
const index_component_t&index_tail = name_tail.index.back();
ivl_assert(*this, index_tail.msb != 0);
ivl_assert(*this, index_tail.lsb != 0);
cerr << get_line() << ": internal error: don't know how to "
"deal with SEL_IDX_DO in lval?" << endl;
des->errors += 1;
return false;
}
NetAssign_* PENumber::elaborate_lval(Design*des, NetScope*, bool) const
{
cerr << get_line() << ": error: Constant values not allowed "
cerr << get_fileline() << ": error: Constant values not allowed "
<< "in l-value expressions." << endl;
des->errors += 1;
return 0;
}
/*
* $Log: elab_lval.cc,v $
* Revision 1.44 2007/06/02 03:42:12 steve
* Properly evaluate scope path expressions.
*
* Revision 1.43 2007/05/24 04:07:11 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.42 2007/03/14 05:06:49 steve
* Replace some asserts with ivl_asserts.
*
* Revision 1.41 2007/03/05 05:59:10 steve
* Handle processes within generate loops.
*
* Revision 1.40 2007/02/27 05:14:38 steve
* Detect and warn about lval array index out fo bounds.
*
* Revision 1.39 2007/02/01 05:25:26 steve
* Error message better reflects more general reality.
*
* Revision 1.38 2007/01/16 05:44:15 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.37 2006/11/04 06:19:25 steve
* Remove last bits of relax_width methods, and use test_width
* to calculate the width of an r-value expression that may
* contain unsized numbers.
*
* Revision 1.36 2006/06/02 04:48:50 steve
* Make elaborate_expr methods aware of the width that the context
* requires of it. In the process, fix sizing of the width of unary
* minus is context determined sizes.
*
* Revision 1.35 2006/04/16 00:54:04 steve
* Cleanup lval part select handling.
*
* Revision 1.34 2006/04/16 00:15:43 steve
* Fix part selects in l-values.
*
* Revision 1.33 2006/02/02 02:43:57 steve
* Allow part selects of memory words in l-values.
*
* Revision 1.32 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.31 2004/12/29 23:55:43 steve
* Unify elaboration of l-values for all proceedural assignments,
* including assing, cassign and force.
*
* Generate NetConcat devices for gate outputs that feed into a
* vector results. Use this to hande gate arrays. Also let gate
* arrays handle vectors of gates when the outputs allow for it.
*
* Revision 1.30 2004/12/11 02:31:25 steve
* Rework of internals to carry vectors through nexus instead
* of single bits. Make the ivl, tgt-vvp and vvp initial changes
* down this path.
*
* Revision 1.29 2004/10/04 01:10:52 steve
* Clean up spurious trailing white space.
*
* Revision 1.28 2004/08/28 14:59:44 steve
* More detailed error message about bad variable.
*
* Revision 1.27 2003/09/19 03:30:05 steve
* Fix name search in elab_lval.
*/
+907 -691
View File
File diff suppressed because it is too large Load Diff
+42 -131
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2000 Stephen Williams (steve@icarus.com)
* Copyright (c) 2000-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: elab_pexpr.cc,v 1.28 2007/06/02 03:42:12 steve Exp $"
#endif
# include "config.h"
@@ -27,11 +24,13 @@
# include "util.h"
# include "netmisc.h"
# include <cstdlib>
# include <iostream>
# include "ivl_assert.h"
NetExpr*PExpr::elaborate_pexpr(Design*des, NetScope*sc) const
{
cerr << get_line() << ": error: invalid parameter expression: "
cerr << get_fileline() << ": error: invalid parameter expression: "
<< *this << endl;
des->errors += 1;
@@ -54,7 +53,7 @@ NetExpr*PEBinary::elaborate_pexpr (Design*des, NetScope*scope) const
return 0;
}
NetEBinary*tmp = elaborate_expr_base_(des, lp, rp, -1);
NetEBinary*tmp = elaborate_expr_base_(des, lp, rp, -2);
return tmp;
}
@@ -75,10 +74,11 @@ NetEConcat* PEConcat::elaborate_pexpr(Design*des, NetScope*scope) const
if (repeat_) {
repeat = repeat_->elaborate_pexpr(des, scope);
if (repeat == 0) {
cerr << get_line() << ": error: "
cerr << get_fileline() << ": error: "
"concatenation repeat expression cannot be evaluated."
<< endl;
des->errors += 1;
return 0;
}
/* continue on even if the repeat expression doesn't
@@ -105,11 +105,12 @@ NetEConcat* PEConcat::elaborate_pexpr(Design*des, NetScope*scope) const
the width check for later. */
} else if (! ex->has_width()) {
cerr << ex->get_line() << ": error: operand of "
cerr << ex->get_fileline() << ": error: operand of "
<< "concatenation has indefinite width: "
<< *ex << endl;
des->errors += 1;
delete tmp;
return 0;
}
tmp->set(idx, ex);
@@ -143,9 +144,21 @@ NetExpr*PEIdent::elaborate_pexpr(Design*des, NetScope*scope) const
const NetExpr*ex_msb;
const NetExpr*ex_lsb;
const NetExpr*ex = pscope->get_parameter(name_tail.name, ex_msb, ex_lsb);
const NetExpr*ex = 0;
// Look up the parameter name in the current scope. If the
// name is not found in the pscope, look in containing scopes,
// but do not go outside the containing module instance.
for (;;) {
ex = pscope->get_parameter(name_tail.name, ex_msb, ex_lsb);
if (ex != 0)
break;
if (pscope->type() == NetScope::MODULE)
break;
pscope = pscope->parent();
ivl_assert(*this, pscope);
}
if (ex == 0) {
cerr << get_line() << ": error: identifier ``" << name_tail.name <<
cerr << get_fileline() << ": error: identifier ``" << name_tail.name <<
"'' is not a parameter in "<< scope_path(scope)<< "." << endl;
des->errors += 1;
return 0;
@@ -162,21 +175,26 @@ NetExpr*PEIdent::elaborate_pexpr(Design*des, NetScope*scope) const
switch (use_sel) {
case index_component_t::SEL_NONE:
break;
default:
case index_component_t::SEL_PART:
cerr << get_line() << ": sorry: Cannot part select "
"bits of parameters." << endl;
cerr << get_fileline() << ": sorry: Cannot part select "
"bits of parameters." << endl;
des->errors += 1;
break;
delete res;
return 0;
case index_component_t::SEL_BIT:
/* We have here a bit select. Insert a NetESelect node
to handle it. */
NetExpr*tmp = name_tail.index.back().msb->elaborate_pexpr(des, scope);
if (tmp != 0) {
res = new NetESelect(res, tmp, 1);
if (tmp == 0) {
delete res;
return 0;
}
res = new NetESelect(res, tmp, 1);
res->set_line(*this);
break;
}
@@ -202,10 +220,11 @@ NetETernary* PETernary::elaborate_pexpr(Design*des, NetScope*scope) const
NetExpr*c = expr_->elaborate_pexpr(des, scope);
NetExpr*t = tru_->elaborate_pexpr(des, scope);
NetExpr*f = fal_->elaborate_pexpr(des, scope);
if (c == 0) return 0;
if (t == 0) return 0;
if (f == 0) return 0;
return new NetETernary(c, t, f);
if (c == 0 || t == 0 || f == 0) return 0;
NetETernary*tmp = new NetETernary(c, t, f);
tmp->set_line(*this);
return tmp;
}
NetExpr*PEUnary::elaborate_pexpr (Design*des, NetScope*scope) const
@@ -223,10 +242,12 @@ NetExpr*PEUnary::elaborate_pexpr (Design*des, NetScope*scope) const
tmp = new NetEUnary(op_, ip);
tmp->set_line(*this);
break;
case '~':
tmp = new NetEUBits(op_, ip);
tmp->set_line(*this);
break;
case '!': // Logical NOT
case '&': // Reduction AND
case '|': // Reduction OR
@@ -238,116 +259,6 @@ NetExpr*PEUnary::elaborate_pexpr (Design*des, NetScope*scope) const
tmp->set_line(*this);
break;
}
return tmp;
}
/*
* $Log: elab_pexpr.cc,v $
* Revision 1.28 2007/06/02 03:42:12 steve
* Properly evaluate scope path expressions.
*
* Revision 1.27 2007/05/24 04:07:11 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.26 2007/04/26 03:06:22 steve
* Rework hname_t to use perm_strings.
*
* Revision 1.25 2006/11/04 06:19:25 steve
* Remove last bits of relax_width methods, and use test_width
* to calculate the width of an r-value expression that may
* contain unsized numbers.
*
* Revision 1.24 2006/06/02 04:48:50 steve
* Make elaborate_expr methods aware of the width that the context
* requires of it. In the process, fix sizing of the width of unary
* minus is context determined sizes.
*
* Revision 1.23 2006/02/02 02:43:58 steve
* Allow part selects of memory words in l-values.
*
* Revision 1.22 2005/11/27 05:56:20 steve
* Handle bit select of parameter with ranges.
*
* Revision 1.21 2004/02/20 06:22:56 steve
* parameter keys are per_strings.
*
* Revision 1.20 2003/05/30 02:55:32 steve
* Support parameters in real expressions and
* as real expressions, and fix multiply and
* divide with real results.
*
* Revision 1.19 2003/01/27 05:09:17 steve
* Spelling fixes.
*
* Revision 1.18 2002/12/05 02:14:33 steve
* Support bit select in constant expressions.
*
* Revision 1.17 2002/11/09 01:40:19 steve
* Postpone parameter width check to evaluation.
*
* Revision 1.16 2002/08/12 01:34:59 steve
* conditional ident string using autoconfig.
*
* Revision 1.15 2002/05/06 02:30:27 steve
* Allow parameters in concatenation of widths are defined.
*
* Revision 1.14 2002/05/05 21:11:50 steve
* Put off evaluation of concatenation repeat expresions
* until after parameters are defined. This allows parms
* to be used in repeat expresions.
*
* Add the builtin $signed system function.
*
* Revision 1.13 2002/01/28 00:52:41 steve
* Add support for bit select of parameters.
* This leads to a NetESelect node and the
* vvp code generator to support that.
*
* Revision 1.12 2001/12/03 04:47:14 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
* Revision 1.11 2001/11/07 04:01:59 steve
* eval_const uses scope instead of a string path.
*
* Revision 1.10 2001/10/07 03:38:08 steve
* parameter names do not have defined size.
*
* Revision 1.9 2001/07/25 03:10:49 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.8 2001/01/14 23:04:56 steve
* Generalize the evaluation of floating point delays, and
* get it working with delay assignment statements.
*
* Allow parameters to be referenced by hierarchical name.
*
* Revision 1.7 2001/01/02 04:21:13 steve
* Support a bunch of unary operators in parameter expressions.
*
* Revision 1.6 2000/12/16 19:03:30 steve
* Evaluate <= and ?: in parameter expressions (PR#81)
*
* Revision 1.5 2000/06/13 05:22:16 steve
* Support concatenation in parameter expressions.
*
* Revision 1.4 2000/06/01 02:31:39 steve
* Parameters can be strings.
*
* Revision 1.3 2000/03/12 18:22:11 steve
* Binary and unary operators in parameter expressions.
*
* Revision 1.2 2000/03/12 04:35:22 steve
* Allow parameter identifiers in parameter expressions.
*
* Revision 1.1 2000/03/08 04:36:53 steve
* Redesign the implementation of scopes and parameters.
* I now generate the scopes and notice the parameters
* in a separate pass over the pform. Once the scopes
* are generated, I can process overrides and evalutate
* paremeters before elaboration begins.
*
*/
+262 -220
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2000-2003 Stephen Williams (steve@icarus.com)
* Copyright (c) 2000-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,13 +16,11 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: elab_scope.cc,v 1.46 2007/06/02 03:42:12 steve Exp $"
#endif
# include "config.h"
# include "compiler.h"
# include "netmisc.h"
# include <cstring>
# include <iostream>
# include <stdio.h>
@@ -46,11 +44,53 @@
# include <typeinfo>
# include <assert.h>
void Module::elaborate_parm_item_(perm_string name, const param_expr_t&cur,
Design*des, NetScope*scope)
{
PExpr*ex = cur.expr;
assert(ex);
NetExpr*val = ex->elaborate_pexpr(des, scope);
if (val == 0) return;
NetExpr*msb = 0;
NetExpr*lsb = 0;
bool signed_flag = cur.signed_flag;
/* If the parameter declaration includes msb and lsb,
then use them to calculate a width for the
result. Then make sure the constant expression of the
parameter value is coerced to have the correct
and defined width. */
if (cur.msb) {
msb = cur.msb ->elaborate_pexpr(des, scope);
assert(msb);
lsb = cur.lsb ->elaborate_pexpr(des, scope);
}
if (signed_flag) {
/* If explicitly signed, then say so. */
val->cast_signed(true);
} else if (cur.msb) {
/* If there is a range, then the signedness comes
from the type and not the expression. */
val->cast_signed(signed_flag);
} else {
/* otherwise, let the expression describe
itself. */
signed_flag = val->has_sign();
}
val = scope->set_parameter(name, val,
msb, lsb, signed_flag);
assert(val);
delete val;
}
bool Module::elaborate_scope(Design*des, NetScope*scope,
const replace_t&replacements) const
{
if (debug_scopes) {
cerr << get_line() << ": debug: Elaborate scope "
cerr << get_fileline() << ": debug: Elaborate scope "
<< scope_path(scope) << "." << endl;
}
@@ -102,42 +142,7 @@ bool Module::elaborate_scope(Design*des, NetScope*scope,
for (mparm_it_t cur = parameters.begin()
; cur != parameters.end() ; cur ++) {
PExpr*ex = (*cur).second.expr;
assert(ex);
NetExpr*val = ex->elaborate_pexpr(des, scope);
NetExpr*msb = 0;
NetExpr*lsb = 0;
bool signed_flag = (*cur).second.signed_flag;
/* If the parameter declaration includes msb and lsb,
then use them to calculate a width for the
result. Then make sure the constant expression of the
parameter value is coerced to have the correct
and defined width. */
if ((*cur).second.msb) {
msb = (*cur).second.msb ->elaborate_pexpr(des, scope);
assert(msb);
lsb = (*cur).second.lsb ->elaborate_pexpr(des, scope);
}
if (signed_flag) {
/* If explicitly signed, then say so. */
val->cast_signed(true);
} else if ((*cur).second.msb) {
/* If there is a range, then the signedness comes
from the type and not the expression. */
val->cast_signed(signed_flag);
} else {
/* otherwise, let the expression describe
itself. */
signed_flag = val->has_sign();
}
val = scope->set_parameter((*cur).first, val,
msb, lsb, signed_flag);
assert(val);
delete val;
elaborate_parm_item_((*cur).first, (*cur).second, des, scope);
}
/* run parameter replacements that were collected from the
@@ -146,15 +151,21 @@ bool Module::elaborate_scope(Design*des, NetScope*scope,
; cur != replacements.end() ; cur ++) {
NetExpr*val = (*cur).second;
if (val == 0) {
cerr << get_fileline() << ": internal error: "
<< "Missing expression in parameter replacement for "
<< (*cur).first;
}
assert(val);
if (debug_scopes) {
cerr << get_line() << ": debug: "
cerr << get_fileline() << ": debug: "
<< "Replace " << (*cur).first
<< " with expression " << *val
<< " from " << val->get_line() << "." << endl;
<< " from " << val->get_fileline() << "." << endl;
}
bool flag = scope->replace_parameter((*cur).first, val);
if (! flag) {
cerr << val->get_line() << ": warning: parameter "
cerr << val->get_fileline() << ": warning: parameter "
<< (*cur).first << " not found in "
<< scope_path(scope) << "." << endl;
}
@@ -163,31 +174,7 @@ bool Module::elaborate_scope(Design*des, NetScope*scope,
for (mparm_it_t cur = localparams.begin()
; cur != localparams.end() ; cur ++) {
PExpr*ex = (*cur).second.expr;
assert(ex);
NetExpr*val = ex->elaborate_pexpr(des, scope);
NetExpr*msb = 0;
NetExpr*lsb = 0;
bool signed_flag = false;
/* If the parameter declaration includes msb and lsb,
then use them to calculate a width for the
result. Then make sure the constant expression of the
parameter value is coerced to have the correct
and defined width. */
if ((*cur).second.msb) {
msb = (*cur).second.msb ->elaborate_pexpr(des, scope);
assert(msb);
lsb = (*cur).second.lsb ->elaborate_pexpr(des, scope);
signed_flag = (*cur).second.signed_flag;
}
val->cast_signed(signed_flag);
val = scope->set_parameter((*cur).first, val,
msb, lsb, signed_flag);
assert(val);
delete val;
elaborate_parm_item_((*cur).first, (*cur).second, des, scope);
}
// Run through the defparams for this module, elaborate the
@@ -244,6 +231,13 @@ bool Module::elaborate_scope(Design*des, NetScope*scope,
; cur != tasks_.end() ; cur ++ ) {
hname_t use_name( (*cur).first );
if (scope->child(use_name)) {
cerr << get_fileline() << ": error: task/scope name "
<< use_name << " already used in this context."
<< endl;
des->errors += 1;
continue;
}
NetScope*task_scope = new NetScope(scope, use_name,
NetScope::TASK);
(*cur).second->elaborate_scope(des, task_scope);
@@ -260,6 +254,13 @@ bool Module::elaborate_scope(Design*des, NetScope*scope,
; cur != funcs_.end() ; cur ++ ) {
hname_t use_name( (*cur).first );
if (scope->child(use_name)) {
cerr << get_fileline() << ": error: function/scope name "
<< use_name << " already used in this context."
<< endl;
des->errors += 1;
continue;
}
NetScope*func_scope = new NetScope(scope, use_name,
NetScope::FUNC);
(*cur).second->elaborate_scope(des, func_scope);
@@ -283,8 +284,8 @@ bool Module::elaborate_scope(Design*des, NetScope*scope,
typedef list<PProcess*>::const_iterator proc_it_t;
for (proc_it_t cur = behaviors_.begin()
; cur != behaviors_.end() ; cur ++ ) {
for (proc_it_t cur = behaviors.begin()
; cur != behaviors.end() ; cur ++ ) {
(*cur) -> statement() -> elaborate_scope(des, scope);
}
@@ -309,8 +310,23 @@ bool PGenerate::generate_scope(Design*des, NetScope*container)
case GS_LOOP:
return generate_scope_loop_(des, container);
case GS_CONDIT:
return generate_scope_condit_(des, container, false);
case GS_ELSE:
return generate_scope_condit_(des, container, true);
case GS_CASE:
return generate_scope_case_(des, container);
return true;
case GS_CASE_ITEM:
cerr << get_fileline() << ": internal error: "
<< "Case item outside of a case generate scheme?" << endl;
return false;
default:
cerr << get_line() << ": sorry: Generate of this sort"
cerr << get_fileline() << ": sorry: Generate of this sort"
<< " is not supported yet!" << endl;
return false;
}
@@ -326,11 +342,11 @@ bool PGenerate::generate_scope_loop_(Design*des, NetScope*container)
// The initial value for the genvar does not need (nor can it
// use) the genvar itself, so we can evaluate this expression
// the same way any other paramter value is evaluated.
// the same way any other parameter value is evaluated.
NetExpr*init_ex = elab_and_eval(des, container, loop_init, -1);
NetEConst*init = dynamic_cast<NetEConst*> (init_ex);
if (init == 0) {
cerr << get_line() << ": error: Cannot evaluate genvar"
cerr << get_fileline() << ": error: Cannot evaluate genvar"
<< " init expression: " << *loop_init << endl;
des->errors += 1;
return false;
@@ -339,11 +355,11 @@ bool PGenerate::generate_scope_loop_(Design*des, NetScope*container)
genvar = init->value().as_long();
delete init_ex;
if (debug_elaborate)
cerr << get_line() << ": debug: genvar init = " << genvar << endl;
if (debug_scopes)
cerr << get_fileline() << ": debug: genvar init = " << genvar << endl;
container->genvar_tmp = loop_index;
container->genvar_tmp_val = 0;
container->genvar_tmp_val = genvar;
NetExpr*test_ex = elab_and_eval(des, container, loop_test, -1);
NetEConst*test = dynamic_cast<NetEConst*>(test_ex);
assert(test);
@@ -354,8 +370,15 @@ bool PGenerate::generate_scope_loop_(Design*des, NetScope*container)
// container. The format of using [] is part of the
// Verilog standard.
hname_t use_name (scope_name, genvar);
if (debug_elaborate)
cerr << get_line() << ": debug: "
if (container->child(use_name)) {
cerr << get_fileline() << ": error: block/scope name "
<< use_name << " already used in this context."
<< endl;
des->errors += 1;
return false;
}
if (debug_scopes)
cerr << get_fileline() << ": debug: "
<< "Create generated scope " << use_name << endl;
NetScope*scope = new NetScope(container, use_name,
@@ -373,28 +396,20 @@ bool PGenerate::generate_scope_loop_(Design*des, NetScope*container)
genvar_verinum);
scope->set_localparam(loop_index, gp);
if (debug_elaborate)
cerr << get_line() << ": debug: "
if (debug_scopes)
cerr << get_fileline() << ": debug: "
<< "Create implicit localparam "
<< loop_index << " = " << genvar_verinum << endl;
}
// Scan the generated scope for gates that may create
// their own scopes.
typedef list<PGate*>::const_iterator pgate_list_it_t;
for (pgate_list_it_t cur = gates.begin()
; cur != gates.end() ; cur ++) {
(*cur) ->elaborate_scope(des, scope);
}
scope_list_.push_back(scope);
elaborate_subscope_(des, scope);
// Calculate the step for the loop variable.
NetExpr*step_ex = elab_and_eval(des, container, loop_step, -1);
NetEConst*step = dynamic_cast<NetEConst*>(step_ex);
assert(step);
if (debug_elaborate)
cerr << get_line() << ": debug: genvar step from "
if (debug_scopes)
cerr << get_fileline() << ": debug: genvar step from "
<< genvar << " to " << step->value().as_long() << endl;
genvar = step->value().as_long();
@@ -413,10 +428,140 @@ bool PGenerate::generate_scope_loop_(Design*des, NetScope*container)
return true;
}
bool PGenerate::generate_scope_condit_(Design*des, NetScope*container, bool else_flag)
{
NetExpr*test_ex = elab_and_eval(des, container, loop_test, -1);
NetEConst*test = dynamic_cast<NetEConst*> (test_ex);
assert(test);
// If the condition evaluates as false, then do not create the
// scope.
if ( (test->value().as_long() == 0 && !else_flag)
|| (test->value().as_long() != 0 && else_flag) ) {
if (debug_scopes)
cerr << get_fileline() << ": debug: Generate condition "
<< (else_flag? "(else)" : "(if)")
<< " value=" << test->value() << ": skip generation"
<< endl;
delete test_ex;
return true;
}
hname_t use_name (scope_name);
if (container->child(use_name)) {
cerr << get_fileline() << ": error: block/scope name "
<< scope_name << " already used in this context."
<< endl;
des->errors += 1;
return false;
}
if (debug_scopes)
cerr << get_fileline() << ": debug: Generate condition "
<< (else_flag? "(else)" : "(if)")
<< " value=" << test->value() << ": Generate scope="
<< use_name << endl;
NetScope*scope = new NetScope(container, use_name,
NetScope::GENBLOCK);
elaborate_subscope_(des, scope);
return true;
}
bool PGenerate::generate_scope_case_(Design*des, NetScope*container)
{
NetExpr*case_value_ex = elab_and_eval(des, container, loop_test, -1);
NetEConst*case_value_co = dynamic_cast<NetEConst*>(case_value_ex);
assert(case_value_co);
// The name of the scope to generate, whatever that item is.
hname_t use_name (scope_name);
if (debug_scopes)
cerr << get_fileline() << ": debug: Generate case "
<< "switch value=" << case_value_co->value() << endl;
PGenerate*default_item = 0;
typedef list<PGenerate*>::const_iterator generator_it_t;
generator_it_t cur = generates.begin();
while (cur != generates.end()) {
PGenerate*item = *cur;
assert( item->scheme_type == PGenerate::GS_CASE_ITEM );
// Detect that the item is a default.
if (item->loop_test == 0) {
default_item = item;
cur ++;
continue;
}
NetExpr*item_value_ex = elab_and_eval(des, container, item->loop_test, -1);
NetEConst*item_value_co = dynamic_cast<NetEConst*>(item_value_ex);
assert(item_value_co);
// If we stumble on the item that matches, then break
// out now.
if (case_value_co->value() == item_value_co->value()) {
delete item_value_co;
break;
}
delete item_value_co;
cur ++;
}
delete case_value_co;
case_value_co = 0;
PGenerate*item = (cur == generates.end())? default_item : *cur;
if (item == 0) {
cerr << get_fileline() << ": debug: "
<< "No generate items found" << endl;
return true;
}
if (debug_scopes)
cerr << get_fileline() << ": debug: "
<< "Generate case matches item at "
<< item->get_fileline() << endl;
NetScope*scope = new NetScope(container, use_name,
NetScope::GENBLOCK);
item->elaborate_subscope_(des, scope);
return true;
}
void PGenerate::elaborate_subscope_(Design*des, NetScope*scope)
{
// Scan the generated scope for nested generate schemes,
// and *generate* new scopes, which is slightly different
// from simple elaboration.
typedef list<PGenerate*>::const_iterator generate_it_t;
for (generate_it_t cur = generates.begin()
; cur != generates.end() ; cur ++ ) {
(*cur) -> generate_scope(des, scope);
}
// Scan the generated scope for gates that may create
// their own scopes.
typedef list<PGate*>::const_iterator pgate_list_it_t;
for (pgate_list_it_t cur = gates.begin()
; cur != gates.end() ; cur ++) {
(*cur) ->elaborate_scope(des, scope);
}
// Save the scope that we created, for future use.
scope_list_.push_back(scope);
}
void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
{
if (get_name() == "") {
cerr << get_line() << ": error: Instantiation of module "
cerr << get_fileline() << ": error: Instantiation of module "
<< mod->mod_name() << " requires an instance name." << endl;
des->errors += 1;
return;
@@ -430,7 +575,7 @@ void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
// it.
if (sc->child(hname_t(get_name()))) {
cerr << get_line() << ": error: Instance/Scope name " <<
cerr << get_fileline() << ": error: Instance/Scope name " <<
get_name() << " already used in this context." <<
endl;
des->errors += 1;
@@ -448,10 +593,10 @@ void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
if (strcmp(mod->mod_name(), scn->module_name()) != 0)
continue;
cerr << get_line() << ": error: You cannot instantiate "
cerr << get_fileline() << ": error: You cannot instantiate "
<< "module " << mod->mod_name() << " within itself." << endl;
cerr << get_line() << ": : The offending instance is "
cerr << get_fileline() << ": : The offending instance is "
<< scope_path(sc) << "." << get_name() << " within "
<< scope_path(scn) << "." << endl;
@@ -486,7 +631,7 @@ void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
NetScope::scope_vec_t instances (instance_count);
if (debug_scopes) {
cerr << get_line() << ": debug: Create " << instance_count
cerr << get_fileline() << ": debug: Create " << instance_count
<< " instances of " << get_name()
<< "." << endl;
}
@@ -509,7 +654,7 @@ void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
}
if (debug_scopes) {
cerr << get_line() << ": debug: Module instance " << use_name
cerr << get_fileline() << ": debug: Module instance " << use_name
<< " becomes child of " << scope_path(sc)
<< "." << endl;
}
@@ -578,6 +723,10 @@ void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
; cur != replace.end() ; cur ++ ) {
PExpr*tmp = (*cur).second;
// No expression means that the parameter is not
// replaced at all.
if (tmp == 0)
continue;
NetExpr*val = tmp->elaborate_pexpr(des, sc);
replace_net[(*cur).first] = val;
}
@@ -593,7 +742,11 @@ void PGModule::elaborate_scope_mod_(Design*des, Module*mod, NetScope*sc) const
/* Stash the instance array of scopes into the parent
scope. Later elaboration passes will use this vector to
further elaborate the array. */
further elaborate the array.
Note that the array is ordered from LSB to MSB. We will use
that fact in the main elaborate to connect things in the
correct order. */
sc->instance_arrays[get_name()] = instances;
}
@@ -646,8 +799,16 @@ void PBlock::elaborate_scope(Design*des, NetScope*scope) const
{
NetScope*my_scope = scope;
if (name_ != 0) {
my_scope = new NetScope(scope, hname_t(name_), bl_type_==BL_PAR
if (pscope_name() != 0) {
hname_t use_name(pscope_name());
if (scope->child(use_name)) {
cerr << get_fileline() << ": error: block/scope name "
<< use_name << " already used in this context."
<< endl;
des->errors += 1;
return;
}
my_scope = new NetScope(scope, use_name, bl_type_==BL_PAR
? NetScope::FORK_JOIN
: NetScope::BEGIN_END);
}
@@ -752,122 +913,3 @@ void PWhile::elaborate_scope(Design*des, NetScope*scope) const
if (statement_)
statement_ -> elaborate_scope(des, scope);
}
/*
* $Log: elab_scope.cc,v $
* Revision 1.46 2007/06/02 03:42:12 steve
* Properly evaluate scope path expressions.
*
* Revision 1.45 2007/05/24 04:07:11 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.44 2007/03/22 16:08:15 steve
* Spelling fixes from Larry
*
* Revision 1.43 2007/03/08 06:11:35 steve
* Elaborate scopes of modules instantated in generate loops.
*
* Revision 1.42 2007/03/05 05:59:10 steve
* Handle processes within generate loops.
*
* Revision 1.41 2006/06/02 04:48:50 steve
* Make elaborate_expr methods aware of the width that the context
* requires of it. In the process, fix sizing of the width of unary
* minus is context determined sizes.
*
* Revision 1.40 2006/04/12 05:05:03 steve
* Use elab_and_eval to evaluate genvar expressions.
*
* Revision 1.39 2006/04/10 00:37:42 steve
* Add support for generate loops w/ wires and gates.
*
* Revision 1.38 2006/03/30 01:49:07 steve
* Fix instance arrays indexed by overridden parameters.
*
* Revision 1.37 2006/03/18 22:53:38 steve
* Support more parameter syntax.
*
* Revision 1.36 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.35 2004/09/10 00:15:17 steve
* Missing stdio.h header for warnings.
*
* Revision 1.34 2004/09/05 17:44:41 steve
* Add support for module instance arrays.
*
* Revision 1.33 2004/08/26 04:02:03 steve
* Add support for localparam ranges.
*
* Revision 1.32 2004/06/13 04:56:54 steve
* Add support for the default_nettype directive.
*
* Revision 1.31 2004/05/25 19:21:06 steve
* More identifier lists use perm_strings.
*
* Revision 1.30 2004/02/20 06:22:56 steve
* parameter keys are per_strings.
*
* Revision 1.29 2004/02/19 07:06:57 steve
* LPM, logic and Variables have perm_string names.
*
* Revision 1.28 2004/02/18 17:11:55 steve
* Use perm_strings for named langiage items.
*
* Revision 1.27 2003/09/13 01:01:51 steve
* Spelling fixes.
*
* Revision 1.26 2003/08/28 04:11:17 steve
* Spelling patch.
*
* Revision 1.25 2003/06/24 01:38:02 steve
* Various warnings fixed.
*
* Revision 1.24 2003/06/20 00:53:19 steve
* Module attributes from the parser
* through to elaborated form.
*
* Revision 1.23 2003/06/16 00:34:08 steve
* Functions can have sub-scope.
*
* Revision 1.22 2003/06/13 19:10:46 steve
* Properly manage real variables in subscopes.
*
* Revision 1.21 2003/05/30 02:55:32 steve
* Support parameters in real expressions and
* as real expressions, and fix multiply and
* divide with real results.
*
* Revision 1.20 2003/03/06 00:28:41 steve
* All NetObj objects have lex_string base names.
*
* Revision 1.19 2003/01/27 05:09:17 steve
* Spelling fixes.
*
* Revision 1.18 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions.
*
* Revision 1.17 2002/10/19 22:59:49 steve
* Redo the parameter vector support to allow
* parameter names in range expressions.
*
* Revision 1.16 2002/09/01 03:01:48 steve
* Properly cast signedness of parameters with ranges.
*
* Revision 1.15 2002/08/19 02:39:16 steve
* Support parameters with defined ranges.
*
* Revision 1.14 2002/08/12 01:34:59 steve
* conditional ident string using autoconfig.
*
* Revision 1.13 2001/12/30 04:47:57 steve
* Properly handle empty target in positionla parameter override.
*
* Revision 1.12 2001/12/03 04:47:14 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*/
+359 -412
View File
File diff suppressed because it is too large Load Diff
+508 -401
View File
File diff suppressed because it is too large Load Diff
+12 -85
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1998-2005 Stephen Williams (steve@icarus.com)
* Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: emit.cc,v 1.89 2007/01/16 05:44:15 steve Exp $"
#endif
# include "config.h"
@@ -32,6 +29,7 @@
# include "netlist.h"
# include <typeinfo>
# include <cassert>
# include <cstring>
bool NetNode::emit_node(struct target_t*tgt) const
{
@@ -130,6 +128,12 @@ bool NetPartSelect::emit_node(struct target_t*tgt) const
return tgt->part_select(this);
}
bool NetPow::emit_node(struct target_t*tgt) const
{
tgt->lpm_pow(this);
return true;
}
bool NetReplicate::emit_node(struct target_t*tgt) const
{
return tgt->replicate(this);
@@ -374,7 +378,9 @@ bool NetScope::emit_defs(struct target_t*tgt) const
case TASK:
tgt->task_def(this);
break;
default: /* BEGIN_END and FORK_JOIN, do nothing */
default: /* BEGIN_END and FORK_JOIN, GENERATE... */
for (NetScope*cur = sub_ ; cur ; cur = cur->sib_)
flag &= cur->emit_defs(tgt);
break;
}
@@ -466,7 +472,7 @@ void NetECRealParam::expr_scan(struct expr_scan_t*tgt) const
void NetEParam::expr_scan(struct expr_scan_t*tgt) const
{
cerr << get_line() << ":internal error: unexpected NetEParam."
cerr << get_fileline() << ":internal error: unexpected NetEParam."
<< endl;
}
@@ -523,82 +529,3 @@ int emit(const Design*des, const char*type)
<< " not found." << endl;
return -1;
}
/*
* $Log: emit.cc,v $
* Revision 1.89 2007/01/16 05:44:15 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.88 2006/11/10 05:44:44 steve
* Process delay paths in second path over signals.
*
* Revision 1.87 2006/06/18 04:15:50 steve
* Add support for system functions in continuous assignments.
*
* Revision 1.86 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.85 2005/07/07 16:22:49 steve
* Generalize signals to carry types.
*
* Revision 1.84 2005/05/24 01:44:27 steve
* Do sign extension of structuran nets.
*
* Revision 1.83 2005/02/08 00:12:36 steve
* Add the NetRepeat node, and code generator support.
*
* Revision 1.82 2005/02/03 04:56:20 steve
* laborate reduction gates into LPM_RED_ nodes.
*
* Revision 1.81 2005/01/24 05:28:30 steve
* Remove the NetEBitSel and combine all bit/part select
* behavior into the NetESelect node and IVL_EX_SELECT
* ivl_target expression type.
*
* Revision 1.80 2005/01/22 01:06:55 steve
* Change case compare from logic to an LPM node.
*
* Revision 1.79 2004/12/29 23:55:43 steve
* Unify elaboration of l-values for all proceedural assignments,
* including assing, cassign and force.
*
* Generate NetConcat devices for gate outputs that feed into a
* vector results. Use this to hande gate arrays. Also let gate
* arrays handle vectors of gates when the outputs allow for it.
*
* Revision 1.78 2004/12/11 02:31:26 steve
* Rework of internals to carry vectors through nexus instead
* of single bits. Make the ivl, tgt-vvp and vvp initial changes
* down this path.
*
* Revision 1.77 2004/10/04 01:10:53 steve
* Clean up spurious trailing white space.
*
* Revision 1.76 2004/05/31 23:34:37 steve
* Rewire/generalize parsing an elaboration of
* function return values to allow for better
* speed and more type support.
*
* Revision 1.75 2003/09/13 01:30:07 steve
* Missing case warnings.
*
* Revision 1.74 2003/05/30 02:55:32 steve
* Support parameters in real expressions and
* as real expressions, and fix multiply and
* divide with real results.
*
* Revision 1.73 2003/04/22 04:48:29 steve
* Support event names as expressions elements.
*
* Revision 1.72 2003/03/10 23:40:53 steve
* Keep parameter constants for the ivl_target API.
*
* Revision 1.71 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions.
*/
+2 -124
View File
@@ -16,12 +16,10 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: eval.cc,v 1.47 2007/06/04 19:14:06 steve Exp $"
#endif
# include "config.h"
# include <cstring>
# include <iostream>
# include "PExpr.h"
@@ -194,7 +192,7 @@ verinum* PEIdent::eval_const(Design*des, NetScope*scope) const
const NetEConst*eval = dynamic_cast<const NetEConst*>(expr);
if (eval == 0) {
cerr << get_line() << ": internal error: Unable to evaluate "
cerr << get_fileline() << ": internal error: Unable to evaluate "
<< "constant expression (parameter=" << path_
<< "): " << *expr << endl;
return 0;
@@ -272,123 +270,3 @@ verinum* PEUnary::eval_const(Design*des, NetScope*scope) const
delete val;
return 0;
}
/*
* $Log: eval.cc,v $
* Revision 1.47 2007/06/04 19:14:06 steve
* Build errors in picky GCC compilers.
*
* Revision 1.46 2007/05/24 04:07:12 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.45 2007/03/07 00:38:15 steve
* Lint fixes.
*
* Revision 1.44 2007/01/16 05:44:15 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.43 2006/08/08 05:11:37 steve
* Handle 64bit delay constants.
*
* Revision 1.42 2006/05/19 04:07:24 steve
* eval_const is not strict.
*
* Revision 1.41 2006/05/17 16:49:30 steve
* Error message if concat expression cannot evaluate.
*
* Revision 1.40 2006/04/10 00:37:42 steve
* Add support for generate loops w/ wires and gates.
*
* Revision 1.39 2005/12/07 04:04:23 steve
* Allow constant concat expressions.
*
* Revision 1.38 2005/11/27 17:01:57 steve
* Fix for stubborn compiler.
*
* Revision 1.37 2005/11/27 05:56:20 steve
* Handle bit select of parameter with ranges.
*
* Revision 1.36 2003/06/21 01:21:43 steve
* Harmless fixup of warnings.
*
* Revision 1.35 2003/04/14 03:40:21 steve
* Make some effort to preserve bits while
* operating on constant values.
*
* Revision 1.34 2003/03/26 06:16:18 steve
* Evaluate > and < in constant expressions.
*
* Revision 1.33 2003/03/10 23:40:53 steve
* Keep parameter constants for the ivl_target API.
*
* Revision 1.32 2002/10/19 22:59:49 steve
* Redo the parameter vector support to allow
* parameter names in range expressions.
*
* Revision 1.31 2002/10/13 05:01:07 steve
* More verbose eval_const assert message.
*
* Revision 1.30 2002/08/12 01:34:59 steve
* conditional ident string using autoconfig.
*
* Revision 1.29 2002/06/07 02:57:54 steve
* Simply give up on constants with indices.
*
* Revision 1.28 2002/06/06 18:57:04 steve
* Better error for identifier index eval.
*
* Revision 1.27 2002/05/23 03:08:51 steve
* Add language support for Verilog-2001 attribute
* syntax. Hook this support into existing $attribute
* handling, and add number and void value types.
*
* Add to the ivl_target API new functions for access
* of complex attributes attached to gates.
*
* Revision 1.26 2001/12/29 22:10:10 steve
* constant eval of arithmetic with x and z.
*
* Revision 1.25 2001/12/29 00:43:55 steve
* Evaluate constant right shifts.
*
* Revision 1.24 2001/12/03 04:47:15 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
* Revision 1.23 2001/11/07 04:01:59 steve
* eval_const uses scope instead of a string path.
*
* Revision 1.22 2001/11/06 06:11:55 steve
* Support more real arithmetic in delay constants.
*
* Revision 1.21 2001/07/25 03:10:49 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.20 2001/02/09 02:49:59 steve
* Be more clear about scope of failure.
*
* Revision 1.19 2001/01/27 05:41:48 steve
* Fix sign extension of evaluated constants. (PR#91)
*
* Revision 1.18 2001/01/14 23:04:56 steve
* Generalize the evaluation of floating point delays, and
* get it working with delay assignment statements.
*
* Allow parameters to be referenced by hierarchical name.
*
* Revision 1.17 2001/01/04 04:47:51 steve
* Add support for << is signal indices.
*
* Revision 1.16 2000/12/10 22:01:36 steve
* Support decimal constants in behavioral delays.
*
* Revision 1.15 2000/09/07 22:38:13 steve
* Support unary + and - in constants.
*/
+307 -464
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File diff suppressed because it is too large Load Diff
+3 -3
View File
@@ -26,7 +26,7 @@
* iverilog -tpal -ppart=generic-22v10-plcc -opal_reg.jed pal_reg.v
*
* The output file name (passed through the -o<file> switch) can be
* any file you desire. If the compilation and fittin all succeed, the
* any file you desire. If the compilation and fitting all succeed, the
* output file will be a JEDEC file that you can take to your favorite
* PROM programmer to program the part.
*
@@ -45,7 +45,7 @@
*
* The output drivers are controlled by a single active low output
* enable. I used bufif0 devices in this example, but the exact same
* thing can be achived with a continuous assignment like so:
* thing can be achieved with a continuous assignment like so:
*
* assign out = oe? 8'hzz : Q;
*
@@ -76,7 +76,7 @@ endmodule
* a PLCC package.
*
* Note that this module has no logic in it. It is a convention I use
* that I put all the functionality in a seperate module (seen above)
* that I put all the functionality in a separate module (seen above)
* and isolate the Icarus Verilog specific $attribute madness into a
* top-level module. The advantage of this style is that the entire
* module can be `ifdef'ed out when doing simulation and you don't
+1 -1
View File
@@ -63,7 +63,7 @@
*
* The $dumpvars task tells the simulation what variables to write to
* the VCD output. The first parameter is how far to descend while
* scanning a scope, and the remaining paramters are signals or scope
* scanning a scope, and the remaining parameters are signals or scope
* names to include in the dump. If a scope name is given, all the
* signals within the scope are dumped. If a wire or register name is
* given, that signal is included.
+4 -4
View File
@@ -20,7 +20,7 @@
*/
/*
* This module is a synthesizeable square-root function. It is also a
* This module is a synthesizable square-root function. It is also a
* detailed example of how to target Xilinx Virtex parts using
* Icarus Verilog. In fact, for no particular reason other than to
* be excessively specific, I will step through the process of
@@ -30,7 +30,7 @@
* In addition to Icarus Verilog, you will need implementation
* software from Xilinx. As of this writing, this example was tested
* with Foundation 4.2i, but it should work the same with ISE and
* Webpack software.
* WebPACK software.
*
* This example source contains all the Verilog needed to do
* everything described below. We use conditional compilation to
@@ -55,7 +55,7 @@
* "PASSED" and finishes the simulation.
*
* When you take a close look at the "main" module below, you will see
* that it uses Verilog constructs that are not synthesizeable. This
* that it uses Verilog constructs that are not synthesizable. This
* is fine, as we will never try to synthesize it.
*
* LIBRARY PARTS
@@ -78,7 +78,7 @@
* Without any preprocessor directives, the only module is the sqrt32
* module, so sqrt32 is compiled as the root. The ports of the module
* are automatically made into ports of the sqrt32.edf netlist, and
* the contents of the sqrt32 module are connected approprately.
* the contents of the sqrt32 module are connected appropriately.
*
* COMPLETE CHIP DESIGNS
*
+334 -272
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1999-2005 Stephen Williams (steve@icarus.com)
* Copyright (c) 1999-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,11 +16,9 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: expr_synth.cc,v 1.87 2007/06/02 03:42:12 steve Exp $"
#endif
# include "config.h"
# include "compiler.h"
# include <iostream>
@@ -28,9 +26,60 @@
# include "netmisc.h"
# include "ivl_assert.h"
NetNet* convert_to_real_const(Design*des, NetExpr*expr, NetExpr*obj)
{
NetNet* sig;
if (NetEConst*tmp = dynamic_cast<NetEConst*>(expr)) {
verireal vrl(tmp->value().as_double());
NetECReal rlval(vrl);
sig = rlval.synthesize(des);
} else {
cerr << obj->get_fileline() << ": sorry: Cannot convert "
"bit based value (" << *expr << ") to real." << endl;
des->errors += 1;
sig = 0;
}
return sig;
}
/* Note that lsig, rsig and real_args are references. */
bool process_binary_args(Design*des, NetExpr*left, NetExpr*right,
NetNet*&lsig, NetNet*&rsig, bool&real_args,
NetExpr*obj)
{
if (left->expr_type() == IVL_VT_REAL ||
right->expr_type() == IVL_VT_REAL) {
real_args = true;
/* Currently we will have a runtime assert if both expressions
are not real, though we can convert constants. */
if (left->expr_type() == IVL_VT_REAL) {
lsig = left->synthesize(des);
} else {
lsig = convert_to_real_const(des, left, obj);
}
if (right->expr_type() == IVL_VT_REAL) {
rsig = right->synthesize(des);
} else {
rsig = convert_to_real_const(des, right, obj);
}
} else {
real_args = false;
lsig = left->synthesize(des);
rsig = right->synthesize(des);
}
if (lsig == 0 || rsig == 0) return true;
else return false;
}
NetNet* NetExpr::synthesize(Design*des)
{
cerr << get_line() << ": internal error: cannot synthesize expression: "
cerr << get_fileline() << ": internal error: cannot synthesize expression: "
<< *this << endl;
des->errors += 1;
return 0;
@@ -43,8 +92,12 @@ NetNet* NetEBAdd::synthesize(Design*des)
{
assert((op()=='+') || (op()=='-'));
NetNet*lsig = left_->synthesize(des);
NetNet*rsig = right_->synthesize(des);
NetNet *lsig=0, *rsig=0;
bool real_args=false;
if (process_binary_args(des, left_, right_, lsig, rsig,
real_args, this)) {
return 0;
}
assert(expr_width() >= lsig->vector_width());
assert(expr_width() >= rsig->vector_width());
@@ -90,17 +143,29 @@ NetNet* NetEBBits::synthesize(Design*des)
NetNet*lsig = left_->synthesize(des);
NetNet*rsig = right_->synthesize(des);
if (lsig == 0 || rsig == 0) return 0;
/* You cannot do bitwise operations on real values. */
if (lsig->data_type() == IVL_VT_REAL ||
rsig->data_type() == IVL_VT_REAL) {
cerr << get_fileline() << ": error: " << human_readable_op(op_)
<< " operator may not have REAL operands." << endl;
des->errors += 1;
return 0;
}
NetScope*scope = lsig->scope();
assert(scope);
if (lsig->vector_width() != rsig->vector_width()) {
cerr << get_line() << ": internal error: bitwise (" << op_
cerr << get_fileline() << ": internal error: bitwise (" << op_
<< ") widths do not match: " << lsig->vector_width()
<< " != " << rsig->vector_width() << endl;
cerr << get_line() << ": : width="
cerr << get_fileline() << ": : width="
<< lsig->vector_width() << ": " << *left_ << endl;
cerr << get_line() << ": : width="
cerr << get_fileline() << ": : width="
<< rsig->vector_width() << ": " << *right_ << endl;
des->errors += 1;
return 0;
}
@@ -118,6 +183,9 @@ NetNet* NetEBBits::synthesize(Design*des)
case '&':
gate = new NetLogic(scope, oname, 3, NetLogic::AND, wid);
break;
case 'A':
gate = new NetLogic(scope, oname, 3, NetLogic::NAND, wid);
break;
case '|':
gate = new NetLogic(scope, oname, 3, NetLogic::OR, wid);
break;
@@ -147,19 +215,27 @@ NetNet* NetEBBits::synthesize(Design*des)
NetNet* NetEBComp::synthesize(Design*des)
{
NetNet*lsig = left_->synthesize(des);
NetNet*rsig = right_->synthesize(des);
NetNet *lsig=0, *rsig=0;
unsigned width;
bool real_args=false;
if (process_binary_args(des, left_, right_, lsig, rsig,
real_args, this)) {
return 0;
}
if (real_args) {
width = 1;
} else {
width = lsig->vector_width();
if (rsig->vector_width() > width) width = rsig->vector_width();
lsig = pad_to_width(des, lsig, width);
rsig = pad_to_width(des, rsig, width);
}
NetScope*scope = lsig->scope();
assert(scope);
unsigned width = lsig->vector_width();
if (rsig->vector_width() > width)
width = rsig->vector_width();
lsig = pad_to_width(des, lsig, width);
rsig = pad_to_width(des, rsig, width);
NetNet*osig = new NetNet(scope, scope->local_symbol(),
NetNet::IMPLICIT, 1);
osig->set_line(*this);
@@ -168,7 +244,7 @@ NetNet* NetEBComp::synthesize(Design*des)
/* Handle the special case of a single bit equality
operation. Make an XNOR gate instead of a comparator. */
if ((width == 1) && ((op_ == 'e') || (op_ == 'E'))) {
if ((width == 1) && ((op_ == 'e') || (op_ == 'E')) && !real_args) {
NetLogic*gate = new NetLogic(scope, scope->local_symbol(),
3, NetLogic::XNOR, 1);
gate->set_line(*this);
@@ -182,7 +258,7 @@ NetNet* NetEBComp::synthesize(Design*des)
/* Handle the special case of a single bit inequality
operation. This is similar to single bit equality, but uses
an XOR instead of an XNOR gate. */
if ((width == 1) && ((op_ == 'n') || (op_ == 'N'))) {
if ((width == 1) && ((op_ == 'n') || (op_ == 'N')) && !real_args) {
NetLogic*gate = new NetLogic(scope, scope->local_symbol(),
3, NetLogic::XOR, 1);
gate->set_line(*this);
@@ -209,8 +285,14 @@ NetNet* NetEBComp::synthesize(Design*des)
case '>':
connect(dev->pin_AGB(), osig->pin(0));
break;
case 'e': // ==
case 'E': // === ?
if (real_args) {
cerr << get_fileline() << ": error: Case equality may "
"not have real operands." << endl;
des->errors += 1;
return 0;
}
case 'e': // ==
connect(dev->pin_AEB(), osig->pin(0));
break;
case 'G': // >=
@@ -219,13 +301,19 @@ NetNet* NetEBComp::synthesize(Design*des)
case 'L': // <=
connect(dev->pin_ALEB(), osig->pin(0));
break;
case 'n': // !=
case 'N': // !==
if (real_args) {
cerr << get_fileline() << ": error: Case inequality may "
"not have real operands." << endl;
des->errors += 1;
return 0;
}
case 'n': // !=
connect(dev->pin_ANEB(), osig->pin(0));
break;
default:
cerr << get_line() << ": internal error: cannot synthesize "
cerr << get_fileline() << ": internal error: cannot synthesize "
"comparison: " << *this << endl;
des->errors += 1;
return 0;
@@ -236,28 +324,60 @@ NetNet* NetEBComp::synthesize(Design*des)
NetNet* NetEBPow::synthesize(Design*des)
{
cerr << get_line() << ": internal error: Do not yet know how to handle"
<< " power operator in this context." << endl;
des->errors += 1;
return 0;
NetNet *lsig=0, *rsig=0;
unsigned width;
bool real_args=false;
if (process_binary_args(des, left_, right_, lsig, rsig,
real_args, this)) {
return 0;
}
if (real_args) width = 1;
else width = expr_width();
NetScope*scope = lsig->scope();
assert(scope);
NetPow*powr = new NetPow(scope, scope->local_symbol(), width,
lsig->vector_width(),
rsig->vector_width());
des->add_node(powr);
powr->set_signed( has_sign() );
powr->set_line(*this);
connect(powr->pin_DataA(), lsig->pin(0));
connect(powr->pin_DataB(), rsig->pin(0));
NetNet*osig = new NetNet(scope, scope->local_symbol(),
NetNet::IMPLICIT, width);
osig->set_line(*this);
osig->data_type(expr_type());
osig->local_flag(true);
connect(powr->pin_Result(), osig->pin(0));
return osig;
}
NetNet* NetEBMult::synthesize(Design*des)
{
NetNet*lsig = left_->synthesize(des);
NetNet*rsig = right_->synthesize(des);
if (lsig == 0)
NetNet *lsig=0, *rsig=0;
unsigned width;
bool real_args=false;
if (process_binary_args(des, left_, right_, lsig, rsig,
real_args, this)) {
return 0;
}
if (rsig == 0)
return 0;
if (real_args) width = 1;
else width = expr_width();
NetScope*scope = lsig->scope();
assert(scope);
NetMult*mult = new NetMult(scope, scope->local_symbol(),
expr_width(),
width,
lsig->vector_width(),
rsig->vector_width());
des->add_node(mult);
@@ -269,8 +389,7 @@ NetNet* NetEBMult::synthesize(Design*des)
connect(mult->pin_DataB(), rsig->pin(0));
NetNet*osig = new NetNet(scope, scope->local_symbol(),
NetNet::IMPLICIT, expr_width());
osig->data_type(lsig->data_type());
NetNet::IMPLICIT, width);
osig->set_line(*this);
osig->data_type(expr_type());
osig->local_flag(true);
@@ -282,13 +401,21 @@ NetNet* NetEBMult::synthesize(Design*des)
NetNet* NetEBDiv::synthesize(Design*des)
{
NetNet*lsig = left_->synthesize(des);
NetNet*rsig = right_->synthesize(des);
NetNet *lsig=0, *rsig=0;
unsigned width;
bool real_args=false;
if (process_binary_args(des, left_, right_, lsig, rsig,
real_args, this)) {
return 0;
}
if (real_args) width = 1;
else width = expr_width();
NetScope*scope = lsig->scope();
NetNet*osig = new NetNet(scope, scope->local_symbol(),
NetNet::IMPLICIT, expr_width());
NetNet::IMPLICIT, width);
osig->set_line(*this);
osig->data_type(lsig->data_type());
osig->local_flag(true);
@@ -297,7 +424,7 @@ NetNet* NetEBDiv::synthesize(Design*des)
case '/': {
NetDivide*div = new NetDivide(scope, scope->local_symbol(),
expr_width(),
width,
lsig->vector_width(),
rsig->vector_width());
div->set_line(*this);
@@ -310,8 +437,16 @@ NetNet* NetEBDiv::synthesize(Design*des)
}
case '%': {
/* Baseline Verilog does not support the % operator with
real arguments, but we allow it in our extended form. */
if (real_args && generation_flag < GN_VER2001X) {
cerr << get_fileline() << ": error: Modulus operator "
"may not have REAL operands." << endl;
des->errors += 1;
return 0;
}
NetModulo*div = new NetModulo(scope, scope->local_symbol(),
expr_width(),
width,
lsig->vector_width(),
rsig->vector_width());
div->set_line(*this);
@@ -324,7 +459,7 @@ NetNet* NetEBDiv::synthesize(Design*des)
}
default: {
cerr << get_line() << ": internal error: "
cerr << get_fileline() << ": internal error: "
<< "NetEBDiv has unexpeced op() code: "
<< op() << endl;
des->errors += 1;
@@ -342,11 +477,16 @@ NetNet* NetEBLogic::synthesize(Design*des)
NetNet*lsig = left_->synthesize(des);
NetNet*rsig = right_->synthesize(des);
if (lsig == 0)
return 0;
if (lsig == 0 || rsig == 0) return 0;
if (rsig == 0)
/* You cannot currently do logical operations on real values. */
if (lsig->data_type() == IVL_VT_REAL ||
rsig->data_type() == IVL_VT_REAL) {
cerr << get_fileline() << ": sorry: " << human_readable_op(op_)
<< " is currently unsupported for real values." << endl;
des->errors += 1;
return 0;
}
NetScope*scope = lsig->scope();
assert(scope);
@@ -414,17 +554,20 @@ NetNet* NetEBLogic::synthesize(Design*des)
NetNet* NetEBShift::synthesize(Design*des)
{
if (! dynamic_cast<NetEConst*>(right_)) {
NetExpr*tmp = right_->eval_tree();
if (tmp) {
delete right_;
right_ = tmp;
}
}
eval_expr(right_);
NetNet*lsig = left_->synthesize(des);
if (lsig == 0)
if (lsig == 0) return 0;
/* Cannot shift a real values. */
if (lsig->data_type() == IVL_VT_REAL) {
cerr << get_fileline() << ": error: shift operator ("
<< human_readable_op(op_)
<< ") cannot shift a real values." << endl;
des->errors += 1;
return 0;
}
bool right_flag = op_ == 'r' || op_ == 'R';
bool signed_flag = op_ == 'R';
@@ -511,8 +654,8 @@ NetNet* NetEBShift::synthesize(Design*des)
}
NetNet*rsig = right_->synthesize(des);
if (rsig == 0)
return 0;
if (rsig == 0) return 0;
NetNet*osig = new NetNet(scope, scope->local_symbol(),
NetNet::IMPLICIT, expr_width());
@@ -561,13 +704,18 @@ NetNet* NetEConcat::synthesize(Design*des)
osig->data_type(tmp[0]->data_type());
NetConcat*concat = new NetConcat(scope, scope->local_symbol(),
osig->vector_width(), parms_.count());
osig->vector_width(),
parms_.count() * repeat());
concat->set_line(*this);
des->add_node(concat);
connect(concat->pin(0), osig->pin(0));
for (unsigned idx = 0 ; idx < parms_.count() ; idx += 1) {
connect(concat->pin(idx+1), tmp[parms_.count()-idx-1]->pin(0));
unsigned cur_pin = 1;
for (unsigned rpt = 0; rpt < repeat(); rpt += 1) {
for (unsigned idx = 0 ; idx < parms_.count() ; idx += 1) {
connect(concat->pin(cur_pin), tmp[parms_.count()-idx-1]->pin(0));
cur_pin += 1;
}
}
delete[]tmp;
@@ -625,6 +773,16 @@ NetNet* NetEUBits::synthesize(Design*des)
{
NetNet*isig = expr_->synthesize(des);
if (isig == 0) return 0;
if (isig->data_type() == IVL_VT_REAL) {
cerr << get_fileline() << ": error: bit-wise negation ("
<< human_readable_op(op_)
<< ") may not have a REAL operand." << endl;
des->errors += 1;
return 0;
}
NetScope*scope = isig->scope();
assert(scope);
@@ -657,6 +815,16 @@ NetNet* NetEUReduce::synthesize(Design*des)
{
NetNet*isig = expr_->synthesize(des);
if (isig == 0) return 0;
if (isig->data_type() == IVL_VT_REAL) {
cerr << get_fileline() << ": error: reduction operator ("
<< human_readable_op(op_)
<< ") may not have a REAL operand." << endl;
des->errors += 1;
return 0;
}
NetScope*scope = isig->scope();
assert(scope);
@@ -688,7 +856,7 @@ NetNet* NetEUReduce::synthesize(Design*des)
rtype = NetUReduce::XNOR;
break;
default:
cerr << get_line() << ": internal error: "
cerr << get_fileline() << ": internal error: "
<< "Unable to synthesize " << *this << "." << endl;
return 0;
}
@@ -708,8 +876,8 @@ NetNet* NetESelect::synthesize(Design *des)
{
NetNet*sub = expr_->synthesize(des);
if (sub == 0)
return 0;
if (sub == 0) return 0;
NetScope*scope = sub->scope();
@@ -801,9 +969,27 @@ NetNet* NetESelect::synthesize(Design *des)
*/
NetNet* NetETernary::synthesize(Design *des)
{
NetNet*csig = cond_->synthesize(des);
NetNet*tsig = true_val_->synthesize(des);
NetNet*fsig = false_val_->synthesize(des);
NetNet*csig = cond_->synthesize(des),
*tsig = true_val_->synthesize(des),
*fsig = false_val_->synthesize(des);
if (csig == 0 || tsig == 0 || fsig == 0) return 0;
if (tsig->data_type() != fsig->data_type()) {
cerr << get_fileline() << ": error: True and False clauses of "
"ternary expression have different types." << endl;
cerr << get_fileline() << ": : True clause is: "
<< tsig->data_type() << endl;
cerr << get_fileline() << ": : False clause is: "
<< fsig->data_type() << endl;
des->errors += 1;
return 0;
} else if (tsig->data_type() == IVL_VT_NO_TYPE) {
cerr << get_fileline() << ": internal error: True and False "
"clauses of ternary both have NO TYPE." << endl;
des->errors += 1;
return 0;
}
perm_string path = csig->scope()->local_symbol();
@@ -835,216 +1021,92 @@ NetNet* NetETernary::synthesize(Design *des)
/*
* When synthesizing a signal expression, it is usually fine to simply
* return the NetNet that it refers to. If this is a part select,
* though, a bit more work needs to be done. Return a temporary that
* represents the connections to the selected bits.
*
* For example, if there is a reg foo, like so:
* reg [5:0] foo;
* and this expression node represents a part select foo[3:2], then
* create a temporary like so:
*
* foo
* +---+
* | 5 |
* +---+
* tmp | 4 |
* +---+ +---+
* | 1 | <---> | 3 |
* +---+ +---+
* | 0 | <---> | 2 |
* +---+ +---+
* | 1 |
* +---+
* | 0 |
* +---+
* The temporary is marked as a temporary and returned to the
* caller. This causes the caller to get only the selected part of the
* signal, and when it hooks up to tmp, it hooks up to the right parts
* of foo.
* return the NetNet that it refers to. If this is an array word though,
* a bit more work needs to be done. Return a temporary that represents
* the selected word.
*/
NetNet* NetESignal::synthesize(Design*des)
{
return net_;
if (word_ == 0)
return net_;
NetScope*scope = net_->scope();
NetNet*tmp = new NetNet(scope, scope->local_symbol(),
NetNet::IMPLICIT, net_->vector_width());
tmp->set_line(*this);
tmp->local_flag(true);
tmp->data_type(net_->data_type());
if (NetEConst*index_co = dynamic_cast<NetEConst*> (word_)) {
long index = index_co->value().as_long();
assert(net_->array_index_is_valid(index));
index = net_->array_index_to_address(index);
connect(tmp->pin(0), net_->pin(index));
} else {
unsigned selwid = word_->expr_width();
NetArrayDq*mux = new NetArrayDq(scope, scope->local_symbol(),
net_, selwid);
mux->set_line(*this);
des->add_node(mux);
NetNet*index_net = word_->synthesize(des);
connect(mux->pin_Address(), index_net->pin(0));
connect(tmp->pin(0), mux->pin_Result());
}
return tmp;
}
/*
* $Log: expr_synth.cc,v $
* Revision 1.87 2007/06/02 03:42:12 steve
* Properly evaluate scope path expressions.
*
* Revision 1.86 2007/04/15 01:37:29 steve
* Allow bit/part select of vectors in continuous assignments.
*
* Revision 1.85 2007/04/12 05:21:54 steve
* fix handling of unary reduction logic in certain nets.
*
* Revision 1.84 2007/04/04 02:31:57 steve
* Remove useless assert
*
* Revision 1.83 2007/02/05 01:42:31 steve
* Set some missing local flags.
*
* Revision 1.82 2007/01/20 02:10:45 steve
* Get argument widths right for shift results.
*
* Revision 1.81 2007/01/16 05:44:15 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.80 2006/08/08 05:11:37 steve
* Handle 64bit delay constants.
*
* Revision 1.79 2006/07/31 03:50:17 steve
* Add support for power in constant expressions.
*
* Revision 1.78 2006/07/08 21:48:46 steve
* Handle real valued literals in net contexts.
*
* Revision 1.77 2006/05/01 20:47:59 steve
* More explicit datatype setup.
*
* Revision 1.76 2006/05/01 05:40:21 steve
* fix net type of multiply output.
*
* Revision 1.75 2006/04/30 05:17:48 steve
* Get the data type of part select results right.
*
* Revision 1.74 2006/01/03 05:15:33 steve
* Fix the return type of a synthesized divide.
*
* Revision 1.73 2005/09/15 23:04:09 steve
* Make sure div, mod and mult nodes have line number info.
*
* Revision 1.72 2005/08/31 05:07:31 steve
* Handle memory references is continuous assignments.
*
* Revision 1.71 2005/06/13 23:22:14 steve
* use NetPartSelect to shrink part from high bits.
*
* Revision 1.70 2005/06/13 22:26:03 steve
* Make synthesized padding vector-aware.
*
* Revision 1.69 2005/05/15 04:47:00 steve
* synthesis of Logic and shifts using vector gates.
*
* Revision 1.68 2005/05/06 00:25:13 steve
* Handle synthesis of concatenation expressions.
*
* Revision 1.67 2005/04/25 01:30:31 steve
* synthesis of add and unary get vector widths right.
*
* Revision 1.66 2005/04/24 23:44:02 steve
* Update DFF support to new data flow.
*
* Revision 1.65 2005/03/12 06:43:35 steve
* Update support for LPM_MOD.
*
* Revision 1.64 2005/02/19 02:43:38 steve
* Support shifts and divide.
*
* Revision 1.63 2005/02/12 06:25:40 steve
* Restructure NetMux devices to pass vectors.
* Generate NetMux devices from ternary expressions,
* Reduce NetMux devices to bufif when appropriate.
*
* Revision 1.62 2005/01/28 05:39:33 steve
* Simplified NetMult and IVL_LPM_MULT.
*
* Revision 1.61 2005/01/16 04:20:32 steve
* Implement LPM_COMPARE nodes as two-input vector functors.
*
* Revision 1.60 2004/12/11 02:31:26 steve
* Rework of internals to carry vectors through nexus instead
* of single bits. Make the ivl, tgt-vvp and vvp initial changes
* down this path.
*
* Revision 1.59 2004/06/30 02:16:26 steve
* Implement signed divide and signed right shift in nets.
*
* Revision 1.58 2004/06/16 16:21:34 steve
* Connect rsif of multiply to DataB.
*
* Revision 1.57 2004/06/12 15:00:02 steve
* Support / and % in synthesized contexts.
*
* Revision 1.56 2004/06/01 01:04:57 steve
* Fix synthesis method for logical and/or
*
* Revision 1.55 2004/02/20 18:53:35 steve
* Addtrbute keys are perm_strings.
*
* Revision 1.54 2004/02/18 17:11:56 steve
* Use perm_strings for named langiage items.
*
* Revision 1.53 2004/02/15 04:23:48 steve
* Fix evaluation of compare to constant expression.
*
* Revision 1.52 2003/11/10 19:39:20 steve
* Remove redundant scope tokens.
*
* Revision 1.51 2003/10/27 06:04:21 steve
* More flexible width handling for synthesized add.
*
* Revision 1.50 2003/09/26 02:44:27 steve
* Assure ternary arguments are wide enough.
*
* Revision 1.49 2003/09/03 23:31:36 steve
* Support synthesis of constant downshifts.
*
* Revision 1.48 2003/08/28 04:11:18 steve
* Spelling patch.
*
* Revision 1.47 2003/08/09 03:23:40 steve
* Add support for IVL_LPM_MULT device.
*
* Revision 1.46 2003/07/26 03:34:42 steve
* Start handling pad of expressions in code generators.
*
* Revision 1.45 2003/06/24 01:38:02 steve
* Various warnings fixed.
*
* Revision 1.44 2003/04/19 04:52:56 steve
* Less picky about expression widths while synthesizing ternary.
*
* Revision 1.43 2003/04/08 05:07:15 steve
* Detect constant shift distances in synthesis.
*
* Revision 1.42 2003/04/08 04:33:55 steve
* Synthesize shift expressions.
*
* Revision 1.41 2003/03/06 00:28:41 steve
* All NetObj objects have lex_string base names.
*
* Revision 1.40 2003/02/26 01:29:24 steve
* LPM objects store only their base names.
*
* Revision 1.39 2003/01/30 16:23:07 steve
* Spelling fixes.
*
* Revision 1.38 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions.
*
* Revision 1.37 2002/11/17 23:37:55 steve
* Magnitude compare to 0.
*
* Revision 1.36 2002/08/12 01:34:59 steve
* conditional ident string using autoconfig.
*
* Revision 1.35 2002/07/07 22:31:39 steve
* Smart synthesis of binary AND expressions.
*
* Revision 1.34 2002/07/05 21:26:17 steve
* Avoid emitting to vvp local net symbols.
*
* Revision 1.33 2002/05/26 01:39:02 steve
* Carry Verilog 2001 attributes with processes,
* all the way through to the ivl_target API.
*
* Divide signal reference counts between rval
* and lval references.
*/
NetNet* NetESFunc::synthesize(Design*des)
{
cerr << get_fileline() << ": sorry: cannot synthesize system function: "
<< *this << " in this context" << endl;
des->errors += 1;
return 0;
}
NetNet* NetEUFunc::synthesize(Design*des)
{
svector<NetNet*> eparms (parms_.count());
/* Synthesize the arguments. */
bool errors = false;
for (unsigned idx = 0; idx < eparms.count(); idx += 1) {
NetNet*tmp = parms_[idx]->synthesize(des);
if (tmp == 0) {
cerr << get_fileline() << ": error: Unable to synthesize "
"port " << idx << " of call to "
<< func_->basename() << "." << endl;
errors = true;
des->errors += 1;
continue;
}
eparms[idx] = tmp;
}
if (errors) return 0;
NetUserFunc*net = new NetUserFunc(scope_, scope_->local_symbol(), func_);
net->set_line(*this);
des->add_node(net);
/* Create an output signal and connect it to the function. */
NetNet*osig = new NetNet(scope_, scope_->local_symbol(), NetNet::WIRE,
result_sig_->vector_width());
osig->local_flag(true);
osig->data_type(result_sig_->expr_type());
connect(net->pin(0), osig->pin(0));
/* Connect the pins to the arguments. */
NetFuncDef*def = func_->func_def();
for (unsigned idx = 0; idx < eparms.count(); idx += 1) {
NetNet*tmp = pad_to_width(des, eparms[idx],
def->port(idx)->vector_width());
connect(net->pin(idx+1), tmp->pin(0));
}
return osig;
}
+1 -1
View File
@@ -59,7 +59,7 @@ types as nets.
- Ports
Module and task ports in standard verilog are restricted to logic
Module and task ports in standard Verilog are restricted to logic
types. This extension removes that restriction, allowing any type to
pass through the port consistent with the continuous assignment
connectivity that is implied by the type.
+10 -58
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1999-2005 Stephen Williams (steve@icarus.com)
* Copyright (c) 1999-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: functor.cc,v 1.35 2005/07/07 16:22:49 steve Exp $"
#endif
# include "config.h"
@@ -83,6 +80,10 @@ void functor_t::lpm_mux(class Design*, class NetMux*)
{
}
void functor_t::lpm_pow(class Design*, class NetPow*)
{
}
void functor_t::sign_extend(class Design*, class NetSignExtend*)
{
}
@@ -223,6 +224,11 @@ void NetMux::functor_node(Design*des, functor_t*fun)
fun->lpm_mux(des, this);
}
void NetPow::functor_node(Design*des, functor_t*fun)
{
fun->lpm_pow(des, this);
}
void NetSignExtend::functor_node(Design*des, functor_t*fun)
{
fun->sign_extend(des, this);
@@ -291,57 +297,3 @@ int proc_match_t::event_wait(NetEvWait*)
{
return 0;
}
/*
* $Log: functor.cc,v $
* Revision 1.35 2005/07/07 16:22:49 steve
* Generalize signals to carry types.
*
* Revision 1.34 2005/05/24 01:44:27 steve
* Do sign extension of structuran nets.
*
* Revision 1.33 2005/02/03 04:56:20 steve
* laborate reduction gates into LPM_RED_ nodes.
*
* Revision 1.32 2004/10/04 01:10:53 steve
* Clean up spurious trailing white space.
*
* Revision 1.31 2002/08/16 05:18:27 steve
* Fix intermix of node functors and node delete.
*
* Revision 1.30 2002/08/12 01:34:59 steve
* conditional ident string using autoconfig.
*
* Revision 1.29 2002/08/10 22:07:38 steve
* Remove useless error messages.
*
* Revision 1.28 2002/06/05 03:44:25 steve
* Add support for memory words in l-value of
* non-blocking assignments, and remove the special
* NetAssignMem_ and NetAssignMemNB classes.
*
* Revision 1.27 2002/06/04 05:38:44 steve
* Add support for memory words in l-value of
* blocking assignments, and remove the special
* NetAssignMem class.
*
* Revision 1.26 2001/10/19 21:53:24 steve
* Support multiple root modules (Philip Blundell)
*
* Revision 1.25 2001/07/25 03:10:49 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.24 2000/11/19 20:48:30 steve
* Fix cases where signal iteration might die early.
*
* Revision 1.23 2000/11/18 04:53:04 steve
* Watch out in functor, it may delete the last signal.
*
* Revision 1.22 2000/09/17 21:26:15 steve
* Add support for modulus (Eric Aardoom)
*
* Revision 1.21 2000/08/01 02:48:41 steve
* Support <= in synthesis of DFF and ram devices.
*/
+4 -44
View File
@@ -1,7 +1,7 @@
#ifndef __functor_H
#define __functor_H
/*
* Copyright (c) 1999-2005 Stephen Williams (steve@icarus.com)
* Copyright (c) 1999-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: functor.h,v 1.23 2005/07/07 16:22:49 steve Exp $"
#endif
/*
* The functor is an object that can be applied to a design to
@@ -81,6 +78,9 @@ struct functor_t {
/* This method is called for each MUX. */
virtual void lpm_mux(class Design*des, class NetMux*);
/* This method is called for each power. */
virtual void lpm_pow(class Design*des, class NetPow*);
/* This method is called for each unary reduction gate. */
virtual void lpm_ureduce(class Design*des, class NetUReduce*);
@@ -97,44 +97,4 @@ struct proc_match_t {
virtual int block(class NetBlock*);
};
/*
* $Log: functor.h,v $
* Revision 1.23 2005/07/07 16:22:49 steve
* Generalize signals to carry types.
*
* Revision 1.22 2005/05/24 01:44:27 steve
* Do sign extension of structuran nets.
*
* Revision 1.21 2005/02/03 04:56:20 steve
* laborate reduction gates into LPM_RED_ nodes.
*
* Revision 1.20 2002/08/12 01:34:59 steve
* conditional ident string using autoconfig.
*
* Revision 1.19 2002/06/05 03:44:25 steve
* Add support for memory words in l-value of
* non-blocking assignments, and remove the special
* NetAssignMem_ and NetAssignMemNB classes.
*
* Revision 1.18 2002/06/04 05:38:44 steve
* Add support for memory words in l-value of
* blocking assignments, and remove the special
* NetAssignMem class.
*
* Revision 1.17 2000/09/17 21:26:15 steve
* Add support for modulus (Eric Aardoom)
*
* Revision 1.16 2000/08/01 02:48:42 steve
* Support <= in synthesis of DFF and ram devices.
*
* Revision 1.15 2000/07/16 04:56:07 steve
* Handle some edge cases during node scans.
*
* Revision 1.14 2000/07/15 05:13:44 steve
* Detect muxing Vz as a bufufN.
*
* Revision 1.13 2000/04/20 00:28:03 steve
* Catch some simple identity compareoptimizations.
*/
#endif
+13
View File
@@ -27,6 +27,15 @@ first source file is named \fIfoo.c\fP, the output becomes
Include the named library in the link of the VPI module. This allows
VPI modules to further reference external libraries.
.TP 8
.B -I\fIdirectory\fP
Add \fIdirectory\fP to the list of directories that will be search for
header files.
.TP 8
.B -D\fIdefine\fP
Define a macro named \fIdefine\fP.
.TP 8
.B --name=\fIname\fP
Normally, the output VPI module will be named after the first source
@@ -39,6 +48,10 @@ This flag causes the program to print the install directory for VPI
modules, then exit. It is a convenience for makefiles or automated
plug-in installers.
.TP 8
.B --cflags, --ldflags and -ldlibs
These flags provide compile time information.
.SH "PC-ONLY OPTIONS"
The PC port of \fIiverilog-vpi\fP includes two special flags needed to
+9 -22
View File
@@ -25,27 +25,17 @@ CXX=@IVCXX@
CFLAGS="@PIC@ @IVCFLAGS@ -I@INCLUDEDIR@"
# These are used for linking...
LD=gcc
LDFLAGS32="@SHARED@ -L@LIBDIR@"
LDFLAGS64="@SHARED@ -L@LIBDIR64@"
LDFLAGS="$LDFLAGS64"
LD=$CC
LDFLAGS="@SHARED@ -L@LIBDIR@"
LDLIBS="-lveriuser -lvpi"
INSTDIR64="@VPIDIR1@"
INSTDIR32="@VPIDIR2@"
if test x$INSTDIR32 = x
then
INSTDIR32=$INSTDIR64
fi
INSTDIR="$INSTDIR64"
CCSRC=
CXSRC=
OBJ=
LIB=
OUT=
INCOPT=
DEFS=
# --
# parse the command line switches. This collects the source files
@@ -90,13 +80,10 @@ do
;;
-I*) INCOPT="$INCOPT $parm"
echo "$parm"
;;
-m32) LDFLAGS="-m32 $LDFLAGS32"
CFLAGS="-m32 $CFLAGS"
INSTDIR="$INSTDIR32"
;;
-D*) DEFS="$DEFS $parm"
;;
--cflags)
echo "$CFLAGS"
@@ -114,7 +101,7 @@ do
;;
--install-dir)
echo "@LIBDIR@/ivl/$INSTDIR"
echo "@LIBDIR@/ivl"
exit
;;
esac
@@ -138,7 +125,7 @@ do
obj=$base".o"
echo "Compiling $src..."
$CC -c -o $obj $CFLAGS $INCOPT $src || compile_errors=`expr $compile_errors + 1`
$CC -c -o $obj $DEFS $CFLAGS $INCOPT $src || compile_errors=`expr $compile_errors + 1`
OBJ="$OBJ $obj"
done
@@ -148,13 +135,13 @@ do
obj=$base".o"
echo "Compiling $src..."
$CXX -c -o $obj $CFLAGS $INCOPT $src || compile_errors=`expr $compile_errors + 1`
$CXX -c -o $obj $DEFS $CFLAGS $INCOPT $src || compile_errors=`expr $compile_errors + 1`
OBJ="$OBJ $obj"
done
if test $compile_errors -gt 0
then
echo "Some ($compile_errors) files failed to compile."
echo "$0: $compile_errors file(s) failed to compile."
exit $compile_errors
fi
+14
View File
@@ -9,6 +9,7 @@ ivl_design_roots
ivl_design_time_precision
ivl_const_bits
ivl_const_delay
ivl_const_real
ivl_const_signed
ivl_const_type
@@ -29,6 +30,8 @@ ivl_expr_bits
ivl_expr_def
ivl_expr_dvalue
ivl_expr_event
ivl_expr_file
ivl_expr_lineno
ivl_expr_name
ivl_expr_opcode
ivl_expr_oper1
@@ -46,6 +49,10 @@ ivl_expr_uvalue
ivl_expr_value
ivl_expr_width
ivl_file_table_index
ivl_file_table_item
ivl_file_table_size
ivl_logic_attr
ivl_logic_attr_cnt
ivl_logic_attr_val
@@ -71,7 +78,10 @@ ivl_lpm_clk
ivl_lpm_data
ivl_lpm_datab
ivl_lpm_define
ivl_lpm_delay
ivl_lpm_enable
ivl_lpm_file
ivl_lpm_lineno
ivl_lpm_name
ivl_lpm_q
ivl_lpm_scope
@@ -111,6 +121,7 @@ ivl_parameter_expr
ivl_path_condit
ivl_path_delay
ivl_path_scope
ivl_path_source
ivl_path_source_negedge
ivl_path_source_posedge
@@ -134,6 +145,7 @@ ivl_scope_port
ivl_scope_ports
ivl_scope_sigs
ivl_scope_sig
ivl_scope_time_precision
ivl_scope_time_units
ivl_scope_type
ivl_scope_tname
@@ -183,6 +195,8 @@ ivl_stmt_cond_true
ivl_stmt_delay_expr
ivl_stmt_delay_val
ivl_stmt_events
ivl_stmt_file
ivl_stmt_lineno
ivl_stmt_lval
ivl_stmt_lvals
ivl_stmt_lwidth
+1 -1
View File
@@ -33,7 +33,7 @@
#define __ivl_assert(expression, tok, file, line) \
do { \
cerr << (tok).get_line() << ": assert: " \
cerr << (tok).get_fileline() << ": assert: " \
<< file << ":" << line \
<< ": failed assertion " << (expression) << endl; \
abort(); \
+64 -88
View File
@@ -1,7 +1,7 @@
#ifndef __ivl_target_H
#define __ivl_target_H
/*
* Copyright (c) 2000-2004 Stephen Williams (steve@icarus.com)
* Copyright (c) 2000-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: ivl_target.h,v 1.182 2007/04/02 01:12:34 steve Exp $"
#endif
# include <inttypes.h>
@@ -209,6 +206,7 @@ typedef enum ivl_logic_e {
IVL_LO_BUFIF0 = 3,
IVL_LO_BUFIF1 = 4,
IVL_LO_BUFZ = 5,
IVL_LO_CMOS = 22,
IVL_LO_NAND = 6,
IVL_LO_NMOS = 7,
IVL_LO_NOR = 8,
@@ -218,6 +216,7 @@ typedef enum ivl_logic_e {
IVL_LO_OR = 12,
IVL_LO_PULLDOWN = 13,
IVL_LO_PULLUP = 14,
IVL_LO_RCMOS = 23,
IVL_LO_RNMOS = 15,
IVL_LO_RPMOS = 16,
IVL_LO_PMOS = 17,
@@ -246,6 +245,7 @@ typedef enum ivl_lpm_type_e {
IVL_LPM_PART_BI= 28, /* part select: bi-directional (part on 0) */
IVL_LPM_PART_VP= 15, /* part select: vector to part */
IVL_LPM_PART_PV= 17, /* part select: part written to vector */
IVL_LPM_POW = 31,
IVL_LPM_RE_AND = 20,
IVL_LPM_RE_NAND= 21,
IVL_LPM_RE_NOR = 22,
@@ -380,9 +380,13 @@ typedef const struct ivl_attribute_s*ivl_attribute_t;
/* DELAYPATH
* Delaypath objects represent delay paths called out by a specify
* block in the verilog source file. The destination signal references
* block in the Verilog source file. The destination signal references
* the path object, which in turn points to the source for the path.
*
* ivl_path_scope
* This returns the scope of the delay path. This scope corresponds
* to the scope of the specify-block that led to this path.
*
* ivl_path_source
* This returns the nexus that is the source end of the delay
* path. Transitions on the source are the start of the delay time
@@ -392,10 +396,11 @@ typedef const struct ivl_attribute_s*ivl_attribute_t;
* This returns the nexus that tracks the condition for the
* delay. If the delay path is unconditional, this returns nil.
*
* ivl_path_srouce_posedge
* ivl_path_source_posedge
* ivl_path_source_negedge
* These functions return true if the source is edge sensitive.
*/
extern ivl_scope_t ivl_path_scope(ivl_delaypath_t obj);
extern ivl_nexus_t ivl_path_source(ivl_delaypath_t obj);
extern uint64_t ivl_path_delay(ivl_delaypath_t obj, ivl_path_edge_t pt);
extern ivl_nexus_t ivl_path_condit(ivl_delaypath_t obj);
@@ -465,7 +470,7 @@ extern ivl_net_const_t ivl_design_const(ivl_design_t, unsigned idx);
* The is the type of the node.
*
* ivl_const_bits
* This returns a pointer to an array of conststant characters,
* This returns a pointer to an array of constant characters,
* each byte a '0', '1', 'x' or 'z'. The array is *not* nul
* terminated.
*
@@ -478,6 +483,9 @@ extern ivl_net_const_t ivl_design_const(ivl_design_t, unsigned idx);
* ivl_const_width
* Return the width, in logical bits, of the constant.
*
* ivl_const_delay
* T0 delay for a transition (0, 1 and Z).
*
* SEMANTIC NOTES
*
* The const_type of the literal constant must match the
@@ -493,6 +501,7 @@ extern ivl_net_const_t ivl_design_const(ivl_design_t, unsigned idx);
*/
extern ivl_variable_type_t ivl_const_type(ivl_net_const_t net);
extern const char* ivl_const_bits(ivl_net_const_t net);
extern ivl_expr_t ivl_const_delay(ivl_net_const_t net, unsigned transition);
extern ivl_nexus_t ivl_const_nex(ivl_net_const_t net);
extern int ivl_const_signed(ivl_net_const_t net);
extern unsigned ivl_const_width(ivl_net_const_t net);
@@ -639,6 +648,8 @@ extern ivl_nexus_t ivl_event_pos(ivl_event_t net, unsigned idx);
extern ivl_expr_type_t ivl_expr_type(ivl_expr_t net);
extern ivl_variable_type_t ivl_expr_value(ivl_expr_t net);
extern const char*ivl_expr_file(ivl_expr_t net);
extern unsigned ivl_expr_lineno(ivl_expr_t net);
/* IVL_EX_NUMBER */
extern const char* ivl_expr_bits(ivl_expr_t net);
@@ -679,6 +690,9 @@ extern unsigned long ivl_expr_uvalue(ivl_expr_t net);
/* any expression */
extern unsigned ivl_expr_width(ivl_expr_t net);
extern const char* ivl_file_table_item(unsigned idx);
extern unsigned ivl_file_table_index(const char *);
extern unsigned ivl_file_table_size(void);
/* LOGIC
@@ -734,7 +748,7 @@ extern unsigned ivl_expr_width(ivl_expr_t net);
* SEMANTIC NOTES
* The ivl_logic_width applies to all the pins of a logic device. If a
* logic device has width, that means that it is actually an array of
* logic devices tha each process a bit slice of the
* logic devices that each process a bit slice of the
* inputs/output. That implies that the widths of all the inputs and
* the output must be identical.
*
@@ -842,6 +856,9 @@ extern unsigned ivl_udp_rows(ivl_udp_t net);
extern const char* ivl_udp_name(ivl_udp_t net);
extern const char* ivl_lpm_file(ivl_lpm_t net);
extern unsigned ivl_lpm_lineno(ivl_lpm_t net);
/* LPM
* These functions support access to the properties of LPM
* devices. LPM devices are a variety of devices that handle more
@@ -855,6 +872,9 @@ extern const char* ivl_udp_name(ivl_udp_t net);
* Return the name of the device. The name is the name of the
* device with the scope part, and the basename is without the scope.
*
* ivl_lpm_delay
* LPM devices have a delay for each transition (0, 1 and Z).
*
* ivl_lpm_scope
* LPM devices exist within a scope. Return the scope that contains
* this device.
@@ -910,7 +930,7 @@ extern const char* ivl_udp_name(ivl_udp_t net);
* The ivl_lpm_q nexus is the output from the concatenation.
*
* The ivl_lpm_data function returns the connections for the inputs to
* the concatentation. The ivl_lpm_size function returns the number of
* the concatenation. The ivl_lpm_size function returns the number of
* inputs help by the device.
*
* - Divide (IVL_LPM_DIVIDE)
@@ -932,6 +952,16 @@ extern const char* ivl_udp_name(ivl_udp_t net);
* Multiply may be signed. If so, the output should be sign extended
* to fill in its result.
*
* - Power (IVL_LPM_POW)
* The power takes two inputs and generates an output. Unlike other
* arithmetic nodes, the width only refers to the output. The inputs
* have independent widths, to reflect the arithmetic truth that the
* width of a general power is the XXXX of the widths of the
* inputs.
*
* Power may be signed. If so, the output should be sign extended
* to fill in its result.
*
* - Part Select (IVL_LPM_PART_VP and IVL_LPM_PART_PV)
* There are two part select devices, one that extracts a part from a
* vector, and another that writes a part of a vector. The _VP is
@@ -984,7 +1014,7 @@ extern const char* ivl_udp_name(ivl_udp_t net);
* The ivl_lpm_data() method returns the inputs of the MUX device. The
* ivl_lpm_size() method returns the number of data inputs there
* are. All the data inputs have the same width, the width of the
* ivl_lpm_q output. The type of the device is devined from the
* ivl_lpm_q output. The type of the device is divined from the
* inputs and the Q. All the types must be exactly the same.
*
* - D-FlipFlop (IVL_LPM_FF)
@@ -1037,7 +1067,7 @@ extern const char* ivl_udp_name(ivl_udp_t net);
* output, but the distance has its own width.
*
* The ivl_lpm_signed() flag means for IVL_LPM_SHIFTR that the right
* shift is *signed*. For SHIFTL, then signed-ness is emaningless.
* shift is *signed*. For SHIFTL, then signed-ness is meaningless.
*
* - System function call (IVL_LPM_SFUNC)
* This device represents a netlist call to a system function. The
@@ -1058,15 +1088,15 @@ extern const char* ivl_udp_name(ivl_udp_t net);
* function are connected to the net, as is the output.
*
* The function definition is associated with a scope, and the
* ivl_lpm_define fuction returns the scope that is that definition.
* See the ivl_scope_* fuctions for how to get at the actual
* ivl_lpm_define function returns the scope that is that definition.
* See the ivl_scope_* functions for how to get at the actual
* definition.
*
* As with many LPM nodes, the ivl_lpm_q function returns the nexus
* for the signal function return value. The width of this nexus must
* exactly match the width of the device from ivl_lpm_width.
*
* The ivl_lpm_data function retrives the nexa for all the input
* The ivl_lpm_data function retrieves the nexa for all the input
* ports. The ivl_lpm_size function returns the number of inputs for
* the device, and the ivl_lpm_data() function index argument selects
* the port to retrieve. Each port is sized independently.
@@ -1074,6 +1104,7 @@ extern const char* ivl_udp_name(ivl_udp_t net);
extern const char* ivl_lpm_name(ivl_lpm_t net); /* (Obsolete) */
extern const char* ivl_lpm_basename(ivl_lpm_t net);
extern ivl_expr_t ivl_lpm_delay(ivl_lpm_t net, unsigned transition);
extern ivl_scope_t ivl_lpm_scope(ivl_lpm_t net);
extern int ivl_lpm_signed(ivl_lpm_t net);
extern ivl_lpm_type_t ivl_lpm_type(ivl_lpm_t net);
@@ -1097,12 +1128,12 @@ extern ivl_scope_t ivl_lpm_define(ivl_lpm_t net);
/* IVL_LPM_FF */
extern ivl_nexus_t ivl_lpm_enable(ivl_lpm_t net);
/* IVL_LPM_ADD IVL_LPM_CONCAT IVL_LPM_FF IVL_LPM_PART IVL_LPM_MULT
IVL_LPM_MUX IVL_LPM_SHIFTL IVL_LPM_SHIFTR IVL_LPM_SUB
IVL_LPM_MUX IVL_LPM_POW IVL_LPM_SHIFTL IVL_LPM_SHIFTR IVL_LPM_SUB
IVL_LPM_UFUNC */
extern ivl_nexus_t ivl_lpm_data(ivl_lpm_t net, unsigned idx);
/* IVL_LPM_ADD IVL_LPM_MULT IVL_LPM_SUB */
/* IVL_LPM_ADD IVL_LPM_MULT IVL_LPM_POW IVL_LPM_SUB */
extern ivl_nexus_t ivl_lpm_datab(ivl_lpm_t net, unsigned idx);
/* IVL_LPM_ADD IVL_LPM_FF IVL_LPM_MULT IVL_LPM_PART
/* IVL_LPM_ADD IVL_LPM_FF IVL_LPM_MULT IVL_LPM_PART IVL_LPM_POW
IVL_LPM_SUB IVL_LPM_UFUNC */
extern ivl_nexus_t ivl_lpm_q(ivl_lpm_t net, unsigned idx);
/* IVL_LPM_MUX */
@@ -1158,7 +1189,7 @@ extern const char*ivl_lpm_string(ivl_lpm_t net);
* SEMANTIC NOTES
* The ivl_lval_width is not necessarily the same as the width of the
* signal or memory word it represents. It is the width of the vector
* it receives and assigns. This may be less then the width of the
* it receives and assigns. This may be less than the width of the
* signal (or even 1) if only a part of the l-value signal is to be
* assigned.
*
@@ -1177,7 +1208,7 @@ extern const char*ivl_lpm_string(ivl_lpm_t net);
* an expression that calculates the address of the array word. If
* the referenced signal has more than one word, this expression must
* be present. If the signal has exactly one word (it is not an array)
* then the ivl_lval_idx exression must *not* be present.
* then the ivl_lval_idx expression must *not* be present.
*
* For array words, the ivl_lval_width is the width of the word.
*/
@@ -1406,6 +1437,11 @@ extern ivl_expr_t ivl_parameter_expr(ivl_parameter_t net);
* anything that can become and ivl_signal_t, include synthetic
* signals generated by the compiler.
*
* ivl_scope_time_precision
* Scopes have their own intrinsic time precision, typically from
* the timescale compiler directive. This method returns the
* precision as a signed power of 10 value.
*
* ivl_scope_time_units
* Scopes have their own intrinsic time units, typically from the
* timescale compiler directive. This method returns the units as a
@@ -1444,6 +1480,7 @@ extern unsigned ivl_scope_sigs(ivl_scope_t net);
extern ivl_signal_t ivl_scope_sig(ivl_scope_t net, unsigned idx);
extern ivl_scope_type_t ivl_scope_type(ivl_scope_t net);
extern const char* ivl_scope_tname(ivl_scope_t net);
extern int ivl_scope_time_precision(ivl_scope_t net);
extern int ivl_scope_time_units(ivl_scope_t net);
@@ -1467,7 +1504,7 @@ extern int ivl_scope_time_units(ivl_scope_t net);
* ivl_signal_array_count
* The signal may be arrayed. If so, the array_count is >1. Each
* word of the array has its own nexus. The array_base is the
* address is the Verilg source for the canonical zero word. This
* address is the Verilog source for the canonical zero word. This
* may be negative, positive or zero.
*
* Note that arraying of the signal into words is distinct from the
@@ -1598,9 +1635,16 @@ extern ivl_attribute_t ivl_process_attr_val(ivl_process_t net, unsigned idx);
* The ivl_statement_type() function returns the type code for the
* statement. This is the major type, and implies which of the later
* functions are applicable to the statement.
*
* the ivl_statement_file() and _lineno() functions return the source
* file and line number of the statement in the Verilog source. This
* information is useful for diagnostic information.
*/
extern ivl_statement_type_t ivl_statement_type(ivl_statement_t net);
extern const char* ivl_stmt_file(ivl_statement_t net);
extern unsigned ivl_stmt_lineno(ivl_statement_t net);
/*
* The following functions retrieve specific single values from the
* statement. These values are the bits of data and parameters that
@@ -1782,72 +1826,4 @@ typedef int (*target_design_f)(ivl_design_t des);
_END_DECL
/*
* $Log: ivl_target.h,v $
* Revision 1.182 2007/04/02 01:12:34 steve
* Seperate arrayness from word count
*
* Revision 1.181 2007/03/22 16:08:16 steve
* Spelling fixes from Larry
*
* Revision 1.180 2007/03/02 06:13:22 steve
* Add support for edge sensitive spec paths.
*
* Revision 1.179 2007/03/01 06:19:38 steve
* Add support for conditional specify delay paths.
*
* Revision 1.178 2007/02/26 19:49:49 steve
* Spelling fixes (larry doolittle)
*
* Revision 1.177 2007/02/25 23:08:24 steve
* Process Verilog escape sequences much earlier.
*
* Revision 1.176 2007/02/02 04:33:00 steve
* Use inttypes.h instead of stdint.h for portability.
*
* Revision 1.175 2007/01/29 01:52:51 steve
* Clarify the use of ivl_scope_def for not-functions.
*
* Revision 1.174 2007/01/17 05:00:12 steve
* Dead code for memories in scopes.
*
* Revision 1.173 2007/01/17 04:39:18 steve
* Remove dead code related to memories.
*
* Revision 1.172 2007/01/16 05:44:15 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.171 2006/09/23 04:57:19 steve
* Basic support for specify timing.
*
* Revision 1.170 2006/08/08 05:11:37 steve
* Handle 64bit delay constants.
*
* Revision 1.169 2006/07/30 02:51:35 steve
* Fix/implement signed right shift.
*
* Revision 1.168 2006/06/18 04:15:50 steve
* Add support for system functions in continuous assignments.
*
* Revision 1.167 2006/04/16 00:15:43 steve
* Fix part selects in l-values.
*
* Revision 1.166 2006/04/10 00:37:42 steve
* Add support for generate loops w/ wires and gates.
*
* Revision 1.165 2006/02/02 02:43:58 steve
* Allow part selects of memory words in l-values.
*
* Revision 1.164 2006/01/02 05:33:19 steve
* Node delays can be more general expressions in structural contexts.
*
* Revision 1.163 2005/12/22 15:44:29 steve
* Document binary expression use.
*
* Revision 1.162 2005/11/20 15:58:25 steve
* Document the IVL_ST_DELAY statements.
*/
#endif
-3
View File
@@ -1,6 +1,3 @@
lexor.c
parse.c
parse.h
parse.output
Makefile
ivlpp
+4 -8
View File
@@ -47,21 +47,18 @@ LDFLAGS = @LDFLAGS@
all: ivlpp@EXEEXT@
clean:
rm -f *.o lexor.c parse.c parse.h parse.output ivlpp@EXEEXT@
rm -f *.o lexor.c ivlpp@EXEEXT@
distclean: clean
rm -f Makefile
O = main.o lexor.o parse.o
O = main.o lexor.o
ivlpp@EXEEXT@: $O
$(CC) $(LDFLAGS) $O -o ivlpp@EXEEXT@ @EXTRALIBS@
lexor.c: lexor.lex
flex -s -olexor.c $(srcdir)/lexor.lex
parse.h parse.c: parse.y
bison --verbose -t -d -o parse.c $(srcdir)/parse.y
flex -olexor.c $(srcdir)/lexor.lex
install: all installdirs $(libdir)/ivl/ivlpp@EXEEXT@
@@ -74,6 +71,5 @@ installdirs: ../mkinstalldirs
uninstall:
rm -f $(libdir)/ivl/ivlpp@EXEEXT@
lexor.o: lexor.c parse.h globals.h
lexor.o: lexor.c globals.h
main.o: main.c globals.h
parse.o: parse.c
+7 -31
View File
@@ -1,7 +1,7 @@
#ifndef __globals_H
#define __globals_H
/*
* Copyright (c) 1999 Stephen Williams (steve@icarus.com)
* Copyright (c) 1999-2007 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,14 +18,14 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: globals.h,v 1.7 2002/08/12 01:35:02 steve Exp $"
#endif
# include <stdio.h>
extern void reset_lexor(FILE*out, char*paths[]);
extern void define_macro(const char*name, const char*value, int keyword);
extern void load_precompiled_defines(FILE*src);
extern void define_macro(const char*name, const char*value, int keyword,
int argc);
extern void dump_precompiled_defines(FILE*out);
/* These variables contain the include directories to be searched when
an include directive in encountered. */
@@ -39,31 +39,7 @@ extern unsigned error_count;
extern FILE *depend_file;
/* This is the entry to the parser. */
extern int yyparse();
/* This is the entry to the lexer. */
extern int yylex();
/*
* $Log: globals.h,v $
* Revision 1.7 2002/08/12 01:35:02 steve
* conditional ident string using autoconfig.
*
* Revision 1.6 2002/04/04 05:26:13 steve
* Add dependency generation.
*
* Revision 1.5 2000/09/13 22:33:13 steve
* undefined macros are null (with warnings.)
*
* Revision 1.4 2000/08/20 17:49:04 steve
* Clean up warnings and portability issues.
*
* Revision 1.3 2000/06/30 15:49:44 steve
* Handle errors from parser slightly differently.
*
* Revision 1.2 1999/09/05 22:33:18 steve
* Take multiple source files on the command line.
*
* Revision 1.1 1999/07/03 20:03:47 steve
* Add include path and line directives.
*
*/
#endif
+1 -1
View File
@@ -19,7 +19,7 @@
THE IVL PREPROCESSOR
The ivlpp command is a verilog preprocessor that handles file
The ivlpp command is a Verilog preprocessor that handles file
inclusion and macro substitution. The program runs separate from the
actual compiler so as to ease the task of the compiler proper, and
provides a means of preprocessing files off-line.
+1371 -618
View File
File diff suppressed because it is too large Load Diff
+65 -80
View File
@@ -1,5 +1,5 @@
const char COPYRIGHT[] =
"Copyright (c) 1999 Stephen Williams ([email protected])";
"Copyright (c) 1999-2007 Stephen Williams ([email protected])";
/*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@ const char COPYRIGHT[] =
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: main.c,v 1.23 2006/10/02 18:16:18 steve Exp $"
#endif
# include "config.h"
@@ -61,6 +58,7 @@ extern const char*optarg;
/* Path to the dependency file, if there is one. */
char *dep_path = NULL;
/*
* Keep in source_list an array of pointers to file names. The array
* is terminated by a pointer to null.
@@ -130,7 +128,7 @@ static int flist_read_flags(const char*path)
else
val = "1";
define_macro(arg, val, 0);
define_macro(arg, val, 0, 0);
} else if (strcmp(cp,"I") == 0) {
include_dir = realloc(include_dir,
@@ -142,7 +140,7 @@ static int flist_read_flags(const char*path)
char*buf = malloc(strlen(arg) + 2);
buf[0] = '`';
strcpy(buf+1, optarg);
define_macro(optarg, buf, 1);
define_macro(optarg, buf, 1, 0);
free(buf);
} else if (strcmp(cp,"M") == 0) {
@@ -200,31 +198,34 @@ int main(int argc, char*argv[])
unsigned flag_errors = 0;
char*out_path = 0;
FILE*out;
char*precomp_out_path = 0;
FILE*precomp_out = NULL;
/* Define preprocessor keywords that I plan to just pass. */
define_macro("celldefine", "`celldefine", 1);
define_macro("default_nettype", "`default_nettype", 1);
define_macro("delay_mode_distributed", "`delay_mode_distributed", 1);
define_macro("delay_mode_unit", "`delay_mode_unit", 1);
define_macro("delay_mode_path", "`delay_mode_path", 1);
define_macro("disable_portfaults", "`disable_portfaults", 1);
define_macro("enable_portfaults", "`enable_portfaults", 1);
define_macro("endcelldefine", "`endcelldefine", 1);
define_macro("endprotect", "`endprotect", 1);
define_macro("nosuppress_faults", "`nosuppress_faults", 1);
define_macro("nounconnected_drive", "`nounconnected_drive", 1);
define_macro("protect", "`protect", 1);
define_macro("resetall", "`resetall", 1);
define_macro("suppress_faults", "`suppress_faults", 1);
define_macro("timescale", "`timescale", 1);
define_macro("unconnected_drive", "`unconnected_drive", 1);
define_macro("uselib", "`uselib", 1);
define_macro("celldefine", "`celldefine", 1, 0);
define_macro("default_nettype", "`default_nettype", 1, 0);
define_macro("delay_mode_distributed", "`delay_mode_distributed", 1, 0);
define_macro("delay_mode_unit", "`delay_mode_unit", 1, 0);
define_macro("delay_mode_path", "`delay_mode_path", 1, 0);
define_macro("disable_portfaults", "`disable_portfaults", 1, 0);
define_macro("enable_portfaults", "`enable_portfaults", 1, 0);
define_macro("endcelldefine", "`endcelldefine", 1, 0);
define_macro("endprotect", "`endprotect", 1, 0);
define_macro("nosuppress_faults", "`nosuppress_faults", 1, 0);
define_macro("nounconnected_drive", "`nounconnected_drive", 1, 0);
define_macro("protect", "`protect", 1, 0);
define_macro("resetall", "`resetall", 1, 0);
define_macro("suppress_faults", "`suppress_faults", 1, 0);
define_macro("timescale", "`timescale", 1, 0);
define_macro("unconnected_drive", "`unconnected_drive", 1, 0);
define_macro("uselib", "`uselib", 1, 0);
include_dir = malloc(sizeof(char*));
include_dir[0] = strdup(".");
include_cnt = 1;
include_cnt = 2;
include_dir = malloc(include_cnt*sizeof(char*));
include_dir[0] = 0; /* 0 is reserved for the current files path. */
include_dir[1] = strdup(".");
while ((opt=getopt(argc, argv, "F:f:K:Lo:v")) != EOF) switch (opt) {
while ((opt=getopt(argc, argv, "F:f:K:Lo:p:P:v")) != EOF) switch (opt) {
case 'F':
flist_read_flags(optarg);
@@ -242,7 +243,7 @@ int main(int argc, char*argv[])
char*buf = malloc(strlen(optarg) + 2);
buf[0] = '`';
strcpy(buf+1, optarg);
define_macro(optarg, buf, 1);
define_macro(optarg, buf, 1, 0);
free(buf);
break;
}
@@ -259,6 +260,25 @@ int main(int argc, char*argv[])
}
break;
case 'p':
if (precomp_out_path) {
fprintf(stderr, "duplicate -p flag.\n");
} else {
precomp_out_path = optarg;
}
break;
case 'P': {
FILE*src = fopen(optarg, "rb");
if (src == 0) {
perror(optarg);
exit(1);
}
load_precompiled_defines(src);
fclose(src);
break;
}
case 'v':
fprintf(stderr, "Icarus Verilog Preprocessor version %s\n",
VERSION);
@@ -278,6 +298,8 @@ int main(int argc, char*argv[])
" -K<def> - Define a keyword macro that I just pass\n"
" -L - Emit line number directives\n"
" -o<fil> - Send the output to <fil>\n"
" -p<fil> - Write precompiled defines to <fil>\n"
" -P<fil> - Read precompiled defines from <fil>\n"
" -v - Print version information\n",
argv[0]);
return flag_errors;
@@ -308,6 +330,14 @@ int main(int argc, char*argv[])
out = stdout;
}
if (precomp_out_path) {
precomp_out = fopen(precomp_out_path, "wb");
if (precomp_out == 0) {
perror(precomp_out_path);
exit(1);
}
}
if(dep_path) {
depend_file = fopen(dep_path, "w");
if (depend_file == 0) {
@@ -322,63 +352,18 @@ int main(int argc, char*argv[])
}
/* Pass to the lexical analyzer the list of input file, and
start the parser. */
start scanning. */
reset_lexor(out, source_list);
if (yyparse()) return -1;
if (yylex()) return -1;
if(depend_file) {
fclose(depend_file);
}
if (precomp_out) {
dump_precompiled_defines(precomp_out);
fclose(precomp_out);
}
return error_count;
}
/*
* $Log: main.c,v $
* Revision 1.23 2006/10/02 18:16:18 steve
* Save dep_path because arg space is overrun.
*
* Revision 1.22 2006/07/26 00:11:40 steve
* Pass depfiles through temp defines file.
*
* Revision 1.21 2006/07/26 00:02:48 steve
* Pass defines and includes through temp file.
*
* Revision 1.20 2004/09/10 00:15:45 steve
* Remove bad casts.
*
* Revision 1.19 2004/09/05 21:29:08 steve
* Better type safety.
*
* Revision 1.18 2004/02/15 18:03:30 steve
* Cleanup of warnings.
*
* Revision 1.17 2003/09/26 02:08:31 steve
* Detect missing endif markers.
*
* Revision 1.16 2002/08/12 01:35:02 steve
* conditional ident string using autoconfig.
*
* Revision 1.15 2002/04/04 05:26:13 steve
* Add dependency generation.
*
* Revision 1.14 2001/11/21 02:59:27 steve
* Remove diag print.
*
* Revision 1.13 2001/11/21 02:20:35 steve
* Pass list of file to ivlpp via temporary file.
*
* Revision 1.12 2001/09/15 18:27:04 steve
* Make configure detect malloc.h
*
* Revision 1.11 2001/07/25 03:10:50 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.10 2001/06/23 18:41:02 steve
* Include stdlib.h
*
* Revision 1.9 2001/05/20 18:08:07 steve
* local declares if the header is missing.
*/
+84 -38
View File
@@ -1,9 +1,10 @@
%option never-interactive
%option nounput
%{
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
* Copyright (c) 1998-2007 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -20,9 +21,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: lexor.lex,v 1.96 2007/06/14 03:50:00 steve Exp $"
#endif
# include "config.h"
@@ -50,37 +48,17 @@
*/
extern YYLTYPE yylloc;
struct file_name_cell {
const char*text;
struct file_name_cell*next;
bool library_flag;
};
static struct file_name_cell*file_names = 0;
static const char* set_file_name(char*text)
{
struct file_name_cell*cur = file_names;
while (cur) {
if (strcmp(cur->text, text) == 0) {
delete[]text;
return cur->text;
}
cur = cur->next;
}
cur = new struct file_name_cell;
cur->text = text;
cur->next = file_names;
perm_string path = filename_strings.make(text);
delete[]text;
/* Check this file name with the list of library file
names. If there is a match, then turn on the
pform_library_flag. This is how the parser knows that
modules declared in this file are library modules. */
cur->library_flag = library_file_map[cur->text];
pform_library_flag = cur->library_flag;
return text;
pform_library_flag = library_file_map[path];
return path;
}
@@ -91,6 +69,7 @@ static void line_directive();
static void line_directive2();
static verinum*make_unsized_binary(const char*txt);
static verinum*make_undef_highz_dec(const char*txt);
static verinum*make_unsized_dec(const char*txt);
static verinum*make_unsized_octal(const char*txt);
static verinum*make_unsized_hex(const char*txt);
@@ -252,7 +231,7 @@ W [ \t\b\f\r]+
}
return rc;
}
}
\\[^ \t\b\f\r\n]+ {
@@ -282,6 +261,8 @@ W [ \t\b\f\r]+
\'[sS]?[dD][ \t]*[0-9][0-9_]* { yylval.number = make_unsized_dec(yytext);
return BASED_NUMBER; }
\'[sS]?[dD][ \t]*[xzXZ?]_* { yylval.number = make_undef_highz_dec(yytext);
return BASED_NUMBER; }
\'[sS]?[bB][ \t]*[0-1xzXZ_\?]+ { yylval.number = make_unsized_binary(yytext);
return BASED_NUMBER; }
\'[sS]?[oO][ \t]*[0-7xzXZ_\?]+ { yylval.number = make_unsized_octal(yytext);
@@ -291,6 +272,7 @@ W [ \t\b\f\r]+
[0-9][0-9_]* {
yylval.number = make_unsized_dec(yytext);
based_size = yylval.number->as_ulong();
return DEC_NUMBER; }
[0-9][0-9_]*\.[0-9][0-9_]*([Ee][+-]?[0-9][0-9_]*)? {
@@ -355,7 +337,7 @@ W [ \t\b\f\r]+
error_count += 1;
}
pform_set_default_nettype(net_type, yylloc.text, yylloc.first_line);
}
}
<PPDEFAULT_NETTYPE>\n {
yylloc.first_line += 1;
BEGIN(0); }
@@ -409,8 +391,9 @@ W [ \t\b\f\r]+
error_count += 1; }
/* Final catchall. something got lost or mishandled. */
/* XXX Should we tell the luser something about the lexical state? */
. { cerr << yylloc.text << ":" << yylloc.first_line
<*>.|\n { cerr << yylloc.text << ":" << yylloc.first_line
<< ": error: unmatched character (";
if (isgraph(yytext[0]))
cerr << yytext[0];
@@ -459,6 +442,9 @@ static verinum*make_unsized_binary(const char*txt)
for (const char*idx = ptr ; *idx ; idx += 1)
if (*idx != '_') size += 1;
if ((based_size > 0) && (size > based_size)) yywarn(yylloc,
"extra digits given for sized binary constant.");
verinum::V*bits = new verinum::V[size];
unsigned idx = size;
@@ -514,6 +500,13 @@ static verinum*make_unsized_octal(const char*txt)
for (const char*idx = ptr ; *idx ; idx += 1)
if (*idx != '_') size += 3;
if (based_size > 0) {
int rem = based_size % 3;
if (rem != 0) based_size += 3 - rem;
if (size > based_size) yywarn(yylloc,
"extra digits given for sized octal constant.");
}
verinum::V*bits = new verinum::V[size];
unsigned idx = size;
@@ -573,6 +566,13 @@ static verinum*make_unsized_hex(const char*txt)
for (const char*idx = ptr ; *idx ; idx += 1)
if (*idx != '_') size += 4;
if (based_size > 0) {
int rem = based_size % 4;
if (rem != 0) based_size += 4 - rem;
if (size > based_size) yywarn(yylloc,
"extra digits given for sized hex constant.");
}
verinum::V*bits = new verinum::V[size];
unsigned idx = size;
@@ -671,6 +671,53 @@ static int dec_buf_div2(char *buf)
return partial;
}
/* Support a single x, z or ? as a decimal constant (from 1364-2005). */
static verinum* make_undef_highz_dec(const char* ptr)
{
bool signed_flag = false;
assert(*ptr == '\'');
/* The number may have decorations of the form 'sd<code>,
possibly with space between the d and the <code>.
Also, the 's' is optional, and marks the number as signed. */
ptr += 1;
if (tolower(*ptr) == 's') {
signed_flag = true;
ptr += 1;
}
assert(tolower(*ptr) == 'd');
ptr += 1;
while (*ptr && ((*ptr == ' ') || (*ptr == '\t')))
ptr += 1;
/* Process the code. */
verinum::V* bits = new verinum::V[1];
switch (*ptr) {
case 'x':
case 'X':
bits[0] = verinum::Vx;
break;
case 'z':
case 'Z':
case '?':
bits[0] = verinum::Vz;
break;
default:
assert(0);
}
ptr += 1;
while (*ptr == '_') ptr += 1;
assert(*ptr == 0);
verinum*out = new verinum(bits, 1, false);
out->has_sign(signed_flag);
delete[]bits;
return out;
}
/*
* Making a decimal number is much easier then the other base numbers
* because there are no z or x values to worry about. It is much
@@ -753,6 +800,10 @@ static verinum*make_unsized_dec(const char*ptr)
assert(size <= tmp_size);
}
/* Since we never have the real number of bits that a decimal
number represents we do not check for extra bits. */
// if (based_size > 0) { }
verinum*res = new verinum(bits, size, false);
res->has_sign(signed_flag);
@@ -926,11 +977,6 @@ void reset_lexor()
yyrestart(vl_input);
yylloc.first_line = 1;
/* Start the file_names list. From here on, as I get a file
name, I will add it to this list. Only add the name if it
is not already in the list. */
file_names = new struct file_name_cell;
file_names->text = strdup(vl_file.c_str());
file_names->next = 0;
yylloc.text = file_names->text;
/* Announce the first file name. */
yylloc.text = set_file_name(strdup(vl_file.c_str()));
}
+5 -37
View File
@@ -30,7 +30,6 @@ VPATH = $(srcdir)
bindir = @bindir@
libdir = @libdir@
libdir64 = @libdir64@
includedir = $(prefix)/include
CC = @CC@
@@ -58,12 +57,6 @@ getlongp.o getp.o getsimtime.o io_print.o math.o mc_scan_plusargs.o \
nodeinfo.o nump.o putlongp.o putp.o spname.o typep.o workarea.o \
veriusertfs.o priv.o $A
ifeq (@enable_vvp32@,yes)
ALL32 = all32
INSTALL32 = install32
UNINSTALL32 = uninstall32
endif
all: dep libveriuser.a $(ALL32)
check: all
@@ -93,40 +86,15 @@ clean:
distclean: clean
rm -f Makefile config.status config.log config.cache config.h
install:: all installdirs $(libdir64)/libveriuser.a $(INSTALL32)
install:: all installdirs $(libdir)/libveriuser.a $(INSTALL32)
$(libdir64)/libveriuser.a: ./libveriuser.a
$(INSTALL_DATA) ./libveriuser.a $(libdir64)/libveriuser.a
$(libdir)/libveriuser.a: ./libveriuser.a
$(INSTALL_DATA) ./libveriuser.a $(libdir)/libveriuser.a
installdirs: mkinstalldirs
$(srcdir)/mkinstalldirs $(includedir) $(libdir64)
$(srcdir)/mkinstalldirs $(includedir) $(libdir)
uninstall::
rm -f $(libdir64)/libveriuser.a
ifeq (@enable_vvp32@,yes)
all32: bin32 bin32/libveriuser.a
bin32:
mkdir bin32
bin32/%.o: %.c
$(CC) -m32 $(CPPFLAGS) $(CFLAGS) -MD -c $< -o $@
bin32/libveriuser.o: $(addprefix bin32/,$O)
$(LD) -melf_i386 -r -o $@ $(addprefix bin32/,$O)
bin32/libveriuser.a: bin32/libveriuser.o
rm -f $@
ar cvq $@ bin32/libveriuser.o
$(RANLIB) $@
install32: $(libdir)/libveriuser.a
$(libdir)/libveriuser.a: bin32/libveriuser.a
$(INSTALL_DATA) bin32/libveriuser.a $(libdir)/libveriuser.a
-include $(patsubst bin32/%.o, bin32/%.d, $(addprefix bin32/,$O))
endif
rm -f $(libdir)/libveriuser.a
-include $(patsubst %.o, dep/%.d, $O)
+1 -1
View File
@@ -52,7 +52,7 @@ handle acc_next(PLI_INT32 *type, handle scope, handle prev)
/*
* The acc_next_* functions need to be reentrant, so we need to
* rescan all the items upto the previous one, then return
* rescan all the items up to the previous one, then return
* the next one.
*/
iter = vpi_iterate(vpiScope, scope); // ICARUS extension
-14
View File
@@ -10,10 +10,6 @@ AC_PROG_RANLIB
AC_EXEEXT
AX_CPP_IDENT
# vvp32 is by default disabled
#enable_vvp32=no
AC_SUBST(enable_vvp32)
AC_CHECK_HEADERS(malloc.h)
AC_CHECK_SIZEOF(unsigned long long)
@@ -29,14 +25,4 @@ AX_C_PICFLAG
AC_SUBST(EXEEXT)
AC_SUBST(EXTRALIBS)
# If not otherwise specified, set the libdir64 variable
# to the same as libdir.
AC_MSG_CHECKING(for libdir64 path)
if test x${libdir64} = x
then
libdir64="${libdir}"
fi
AC_SUBST(libdir64)
AC_MSG_RESULT(${libdir64})
AC_OUTPUT(Makefile)
+2 -2
View File
@@ -29,13 +29,13 @@
*/
int tf_dofinish(void)
{
vpi_sim_control(vpiFinish, 0);
vpi_control(vpiFinish, 0);
return 0;
}
int tf_dostop(void)
{
vpi_sim_control(vpiStop, 0);
vpi_control(vpiStop, 0);
return 0;
}
+1 -1
View File
@@ -24,7 +24,7 @@
#include <acc_user.h>
/*
* tf_getinstance implemented using equvalent acc_ routing
* tf_getinstance implemented using equivalent acc_ routing
*/
char *tf_getcstringp(int n)
{
+1 -1
View File
@@ -32,7 +32,7 @@
extern char* __acc_newstring(const char*txt);
/*
* Trace file for loggint ACC and TF calls.
* Trace file for logging ACC and TF calls.
*/
FILE* pli_trace;
+7 -13
View File
@@ -49,6 +49,9 @@ PLI_INT32 tf_typep(PLI_INT32 narg)
case vpiStringConst:
rtn = TF_STRING;
break;
case vpiRealConst:
rtn = TF_READONLYREAL;
break;
default:
rtn = TF_READONLY;
break;
@@ -61,6 +64,10 @@ PLI_INT32 tf_typep(PLI_INT32 narg)
rtn = TF_READWRITE;
break;
case vpiRealVar:
rtn = TF_READWRITEREAL;
break;
default:
rtn = TF_READONLY;
break;
@@ -69,16 +76,3 @@ PLI_INT32 tf_typep(PLI_INT32 narg)
vpi_free_object(argv);
return rtn;
}
/*
* $Log: typep.c,v $
* Revision 1.2 2003/03/13 05:07:46 steve
* Declaration warnings.
*
* Revision 1.1 2002/12/19 21:37:04 steve
* Add tf_message, tf_get/setworkarea, and
* ty_typep functions, along with defines
* related to these functions.
*
*/
+8 -70
View File
@@ -23,7 +23,7 @@
/*
* Contains the routines required to implement veriusertfs routines
* via VPI. This is extremly ugly, so don't look after eating dinner.
* via VPI. This is extremely ugly, so don't look after eating dinner.
*/
# include <string.h>
@@ -98,6 +98,11 @@ void veriusertfs_register_table(p_tfcell vtable)
tf_data.type = vpiSysTask;
break;
case userfunction:
tf_data.sysfunctype = vpiIntFunc;
tf_data.type = vpiSysFunc;
break;
case userrealfunction:
tf_data.sysfunctype = vpiRealFunc;
tf_data.type = vpiSysFunc;
break;
default:
@@ -109,7 +114,7 @@ void veriusertfs_register_table(p_tfcell vtable)
tf_data.tfname = tf->tfname;
tf_data.compiletf = compiletf;
tf_data.calltf = calltf;
tf_data.sizetf = tf->sizetf;
tf_data.sizetf = (PLI_INT32 (*)(PLI_BYTE8 *))tf->sizetf;
tf_data.user_data = (char *)data;
if (pli_trace) {
@@ -387,71 +392,4 @@ PLI_INT32 tf_setrealdelay(double dly)
{
return tf_isetrealdelay(dly, tf_getinstance());
}
/*
* $Log: veriusertfs.c,v $
* Revision 1.17 2007/05/08 22:01:26 steve
* Trace file line buffer must be static.
*
* Revision 1.16 2006/10/30 22:45:37 steve
* Updates for Cygwin portability (pr1585922)
*
* Revision 1.15 2004/09/10 23:13:05 steve
* Compile cleanup of C code.
*
* Revision 1.14 2003/06/25 04:04:19 steve
* Fix mingw portability problems.
*
* Revision 1.13 2003/06/17 22:09:45 steve
* Better trace of PLI1 registration.
*
* Revision 1.12 2003/06/17 16:55:08 steve
* 1) setlinebuf() for vpi_trace
* 2) Addes error checks for trace file opens
* 3) removes now extraneous flushes
* 4) fixes acc_next() bug
*
* Revision 1.11 2003/06/04 01:56:20 steve
* 1) Adds configure logic to clean up compiler warnings
* 2) adds acc_compare_handle, acc_fetch_range, acc_next_scope and
* tf_isetrealdelay, acc_handle_scope
* 3) makes acc_next reentrant
* 4) adds basic vpiWire type support
* 5) fills in some acc_object_of_type() and acc_fetch_{full}type()
* 6) add vpiLeftRange/RigthRange to signals
*
* Revision 1.10 2003/05/30 04:05:32 steve
* Add tf_rosynchronize and friends.
*
* Revision 1.9 2003/05/28 02:42:43 steve
* compiler warnings.
*
* Revision 1.8 2003/05/18 00:16:35 steve
* Add PLI_TRACE tracing of PLI1 modules.
*
* Add tf_isetdelay and friends, and add
* callback return values for acc_vcl support.
*
* Revision 1.7 2003/04/23 15:01:29 steve
* Add tf_synchronize and tf_multiply_long.
*
* Revision 1.6 2003/02/16 02:23:14 steve
* Change the IV veriusertfs_register to accept table pointers.
*
* Revision 1.5 2002/08/12 01:35:02 steve
* conditional ident string using autoconfig.
*
* Revision 1.4 2002/06/04 01:42:58 steve
* Add misctf support to libveriuser
*
* Revision 1.3 2002/06/03 00:08:42 steve
* Better typing for veriusertfs table.
*
* Revision 1.2 2002/05/31 18:21:39 steve
* Check for and don't dereference null pointers,
* Avoid copy of static objects.
* (mruff)
*
* Revision 1.1 2002/05/30 02:37:26 steve
* Add the veriusertf_register funciton.
*
*/
+2
View File
@@ -26,6 +26,8 @@
# include "compiler.h"
# include <iostream>
# include <map>
# include <cstdlib>
# include <cstring>
# include <string>
# include <sys/types.h>
# include <dirent.h>
+24 -6
View File
@@ -44,6 +44,7 @@ const char NOTICE[] =
# include <iostream>
# include <fstream>
# include <queue>
# include <cstring>
# include <list>
# include <map>
# include <unistd.h>
@@ -84,17 +85,18 @@ const char*target = "null";
/*
* These are the language support control flags. These support which
* language features (the generation) to support. The generation_flag
* is a major moce, and the gn_* flags control specifc sub-features.
* is a major mode, and the gn_* flags control specific sub-features.
*/
generation_t generation_flag = GN_DEFAULT;
bool gn_cadence_types_flag = true;
bool gn_specify_blocks_flag = true;
bool gn_io_range_error_flag = true;
map<string,const char*> flags;
char*vpi_module_list = 0;
map<perm_string,unsigned> missing_modules;
map<string,bool> library_file_map;
map<perm_string,bool> library_file_map;
list<const char*> library_suff;
@@ -134,6 +136,8 @@ unsigned integer_width = 32;
*/
StringHeapLex lex_strings;
StringHeapLex filename_strings;
/*
* In library searches, Windows file names are never case sensitive.
*/
@@ -143,6 +147,11 @@ const bool CASE_SENSITIVE = false;
const bool CASE_SENSITIVE = true;
#endif
/*
* Are we doing synthesis?
*/
bool synthesis = false;
extern void cprop(Design*des);
extern void synth(Design*des);
extern void synth2(Design*des);
@@ -211,6 +220,12 @@ static void process_generation_flag(const char*gen)
} else if (strcmp(gen,"no-specify") == 0) {
gn_specify_blocks_flag = false;
} else if (strcmp(gen,"io-range-error") == 0) {
gn_io_range_error_flag = true;
} else if (strcmp(gen,"no-io-range-error") == 0) {
gn_io_range_error_flag = false;
} else {
}
}
@@ -341,9 +356,9 @@ static void read_iconfig_file(const char*ipath)
basedir = strdup(cp);
} else if (strcmp(buf, "debug") == 0) {
if (strcmp(cp, "scope") == 0) {
if (strcmp(cp, "scopes") == 0) {
debug_scopes = true;
cerr << "debug: Enable scope debug" << endl;
cerr << "debug: Enable scopes debug" << endl;
} else if (strcmp(cp,"eval_tree") == 0) {
debug_eval_tree = true;
cerr << "debug: Enable eval_tree debug" << endl;
@@ -364,6 +379,9 @@ static void read_iconfig_file(const char*ipath)
parm_to_flagmap(parm);
} else if (strcmp(buf,"functor") == 0) {
if (strncmp(cp, "synth", 5) == 0) {
synthesis = true; // We are doing synthesis.
}
net_func tmp = name_to_net_func(cp);
if (tmp == 0) {
cerr << "No such design transform function ``"
@@ -383,7 +401,7 @@ static void read_iconfig_file(const char*ipath)
integer_width = strtoul(cp,0,10);
} else if (strcmp(buf, "library_file") == 0) {
const char* path = strdup(cp);
perm_string path = filename_strings.make(cp);
library_file_map[path] = true;
} else if (strcmp(buf,"module") == 0) {
@@ -710,7 +728,7 @@ int main(int argc, char*argv[])
des->set_flags(flags);
/* Done iwth all the pform data. Delete the modules. */
/* Done with all the pform data. Delete the modules. */
for (map<perm_string,Module*>::iterator idx = pform_modules.begin()
; idx != pform_modules.end() ; idx ++) {
+2 -2
View File
@@ -91,7 +91,7 @@ commands below.
The obvious step 2, then, is install the mingw compilers. These can be
found at the web page <http://www.mingw.org>. The Mingw-5.x.x package
is a convenient remote installer. Download this program and run
it. The installer will ask wich components you want to install. You
it. The installer will ask which components you want to install. You
need only the base C compiler and the C++ compiler. (You may install
other languages if you wish.)
@@ -150,7 +150,7 @@ You will need these gnuwin32 packages to compile Icarus Verilog:
I suggest creating a common directory for holding all your gnuwin32
packages. I use C:\gnuwin32. The download page at the gnuwin32 site
has a "setup" link for each of these packages. Click the setup to
download the installer for each of the desired programes, then execute
download the installer for each of the desired programs, then execute
the downloaded .exe files to invoke the installer. Install into the
c:\gunwin32 directory.
+16 -121
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2000-2003 Stephen Williams (steve@icarus.com)
* Copyright (c) 2000-2007 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: net_design.cc,v 1.54 2007/06/05 04:18:09 steve Exp $"
#endif
# include "config.h"
@@ -149,7 +146,8 @@ NetScope* Design::find_scope(const std::list<hname_t>&path) const
* I do not find the scope within the passed scope, start looking in
* parent scopes until I find it, or I run out of parent scopes.
*/
NetScope* Design::find_scope(NetScope*scope, const std::list<hname_t>&path) const
NetScope* Design::find_scope(NetScope*scope, const std::list<hname_t>&path,
NetScope::TYPE type) const
{
assert(scope);
if (path.empty())
@@ -162,7 +160,11 @@ NetScope* Design::find_scope(NetScope*scope, const std::list<hname_t>&path) cons
NetScope*cur = scope;
do {
hname_t key = tmp.front();
/* If we are looking for a module or we are not
* looking at the last path component check for
* a name match (second line). */
if (cur->type() == NetScope::MODULE
&& (type == NetScope::MODULE || tmp.size() > 1)
&& cur->module_name()==key.peek_name()) {
/* Up references may match module name */
@@ -218,14 +220,14 @@ void NetScope::run_defparams(Design*des)
is the current scope. */
NetScope*targ_scope = des->find_scope(this, eval_path);
if (targ_scope == 0) {
cerr << val->get_line() << ": warning: scope of " <<
cerr << val->get_fileline() << ": warning: scope of " <<
path << "." << perm_name << " not found." << endl;
continue;
}
bool flag = targ_scope->replace_parameter(perm_name, val);
if (! flag) {
cerr << val->get_line() << ": warning: parameter "
cerr << val->get_fileline() << ": warning: parameter "
<< perm_name << " not found in "
<< scope_path(targ_scope) << "." << endl;
}
@@ -275,7 +277,7 @@ void NetScope::evaluate_parameters(Design*des)
NetExpr*nexpr = expr->eval_tree();
if (nexpr == 0) {
cerr << (*cur).second.expr->get_line()
cerr << (*cur).second.expr->get_fileline()
<< ": internal error: "
<< "unable to evaluate msb expression "
<< "for parameter " << (*cur).first << ": "
@@ -306,7 +308,7 @@ void NetScope::evaluate_parameters(Design*des)
NetExpr*nexpr = expr->eval_tree();
if (nexpr == 0) {
cerr << (*cur).second.expr->get_line()
cerr << (*cur).second.expr->get_fileline()
<< ": internal error: "
<< "unable to evaluate lsb expression "
<< "for parameter " << (*cur).first << ": "
@@ -339,7 +341,7 @@ void NetScope::evaluate_parameters(Design*des)
NetExpr*nexpr = expr->eval_tree();
if (nexpr == 0) {
cerr << (*cur).second.expr->get_line()
cerr << (*cur).second.expr->get_fileline()
<< ": internal error: "
<< "unable to evaluate real parameter value: "
<< *expr << endl;
@@ -360,7 +362,7 @@ void NetScope::evaluate_parameters(Design*des)
// Try to evaluate the expression.
NetExpr*nexpr = expr->eval_tree();
if (nexpr == 0) {
cerr << (*cur).second.expr->get_line()
cerr << (*cur).second.expr->get_fileline()
<< ": internal error: "
<< "unable to evaluate parameter "
<< (*cur).first
@@ -383,7 +385,7 @@ void NetScope::evaluate_parameters(Design*des)
break;
default:
cerr << (*cur).second.expr->get_line()
cerr << (*cur).second.expr->get_fileline()
<< ": internal error: "
<< "unhandled expression type?" << endl;
des->errors += 1;
@@ -463,7 +465,7 @@ NetFuncDef* Design::find_function(NetScope*scope, const pform_name_t&name)
assert(scope);
std::list<hname_t> eval_path = eval_scope_path(this, scope, name);
NetScope*func = find_scope(scope, eval_path);
NetScope*func = find_scope(scope, eval_path, NetScope::FUNC);
if (func && (func->type() == NetScope::FUNC))
return func->func_def();
@@ -473,7 +475,7 @@ NetFuncDef* Design::find_function(NetScope*scope, const pform_name_t&name)
NetScope* Design::find_task(NetScope*scope, const pform_name_t&name)
{
std::list<hname_t> eval_path = eval_scope_path(this, scope, name);
NetScope*task = find_scope(scope, eval_path);
NetScope*task = find_scope(scope, eval_path, NetScope::TASK);
if (task && (task->type() == NetScope::TASK))
return task;
@@ -553,110 +555,3 @@ void Design::delete_process(NetProcTop*top)
delete top;
}
/*
* $Log: net_design.cc,v $
* Revision 1.54 2007/06/05 04:18:09 steve
* Upward names may reference modules by module_name.
*
* Revision 1.53 2007/06/02 03:42:13 steve
* Properly evaluate scope path expressions.
*
* Revision 1.52 2007/05/24 04:07:12 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.51 2007/04/26 03:06:22 steve
* Rework hname_t to use perm_strings.
*
* Revision 1.50 2006/08/08 05:11:37 steve
* Handle 64bit delay constants.
*
* Revision 1.49 2006/07/31 03:50:17 steve
* Add support for power in constant expressions.
*
* Revision 1.48 2005/11/27 05:56:20 steve
* Handle bit select of parameter with ranges.
*
* Revision 1.47 2005/09/14 02:53:14 steve
* Support bool expressions and compares handle them optimally.
*
* Revision 1.46 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.45 2004/10/04 01:10:54 steve
* Clean up spurious trailing white space.
*
* Revision 1.44 2004/02/20 06:22:56 steve
* parameter keys are per_strings.
*
* Revision 1.43 2004/02/18 17:11:56 steve
* Use perm_strings for named langiage items.
*
* Revision 1.42 2003/11/10 20:59:03 steve
* Design::get_flag returns const char* instead of string.
*
* Revision 1.41 2003/09/20 01:05:36 steve
* Obsolete find_symbol and find_event from the Design class.
*
* Revision 1.40 2003/09/19 03:50:12 steve
* Remove find_memory method from Design class.
*
* Revision 1.39 2003/09/19 03:30:05 steve
* Fix name search in elab_lval.
*
* Revision 1.38 2003/08/28 04:11:19 steve
* Spelling patch.
*
* Revision 1.37 2003/06/24 01:38:02 steve
* Various warnings fixed.
*
* Revision 1.36 2003/03/10 23:40:53 steve
* Keep parameter constants for the ivl_target API.
*
* Revision 1.35 2003/03/06 04:37:12 steve
* lex_strings.add module names earlier.
*
* Revision 1.34 2003/02/01 23:37:34 steve
* Allow parameter expressions to be type real.
*
* Revision 1.33 2003/01/27 05:09:17 steve
* Spelling fixes.
*
* Revision 1.32 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions.
*
* Revision 1.31 2003/01/14 21:16:18 steve
* Move strstream to ostringstream for compatibility.
*
* Revision 1.30 2002/12/07 02:49:24 steve
* Named event triggers can take hierarchical names.
*
* Revision 1.29 2002/11/02 03:27:52 steve
* Allow named events to be referenced by
* hierarchical names.
*
* Revision 1.28 2002/10/19 22:59:49 steve
* Redo the parameter vector support to allow
* parameter names in range expressions.
*
* Revision 1.27 2002/08/16 05:18:27 steve
* Fix intermix of node functors and node delete.
*
* Revision 1.26 2002/08/12 01:34:59 steve
* conditional ident string using autoconfig.
*
* Revision 1.25 2002/07/03 05:34:59 steve
* Fix scope search for events.
*
* Revision 1.24 2002/06/25 02:39:34 steve
* Fix mishandling of incorect defparam error message.
*
* Revision 1.23 2001/12/03 04:47:15 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
* Revision 1.22 2001/10/20 05:21:51 steve
* Scope/module names are char* instead of string.
*/
+22 -121
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
* Copyright (c) 2002-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,13 +16,11 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: net_expr.cc,v 1.27 2006/07/31 03:50:17 steve Exp $"
#endif
# include "config.h"
# include "netlist.h"
# include "compiler.h"
# include "netmisc.h"
# include <iostream>
/*
@@ -37,7 +35,7 @@ ivl_variable_type_t NetExpr::expr_type() const
* Create an add/sub node from the two operands. Make a best guess of
* the
*/
NetEBAdd::NetEBAdd(char op, NetExpr*l, NetExpr*r)
NetEBAdd::NetEBAdd(char op, NetExpr*l, NetExpr*r, bool lossless_flag)
: NetEBinary(op, l, r)
{
NetEConst* tmp;
@@ -48,14 +46,19 @@ NetEBAdd::NetEBAdd(char op, NetExpr*l, NetExpr*r)
one. This expands the expression to account for the largest
possible result.
Remember to handle the special case of an unsized constant,
which we define to be at least "integer_width" bits.
The set_width applied to a constant value will only
truncate the constant so far as it can still hold its
logical value, so this is safe to do. */
if ( (tmp = dynamic_cast<NetEConst*>(r))
&& (! tmp->has_width())
&& (tmp->expr_width() > l->expr_width()) ) {
&& (tmp->expr_width() > l->expr_width() || integer_width > l->expr_width()) ) {
unsigned target_width = l->expr_width() + 1;
if (target_width < integer_width)
target_width = integer_width;
r->set_width(target_width);
/* Note: This constant value will not gain a defined
@@ -64,9 +67,11 @@ NetEBAdd::NetEBAdd(char op, NetExpr*l, NetExpr*r)
} else if ( (tmp = dynamic_cast<NetEConst*>(l))
&& (! tmp->has_width())
&& (tmp->expr_width() > r->expr_width()) ) {
&& (tmp->expr_width() > r->expr_width() || integer_width > r->expr_width()) ) {
unsigned target_width = r->expr_width() + 1;
if (target_width < integer_width)
target_width = integer_width;
l->set_width(target_width);
/* Note: This constant value will not gain a defined
@@ -75,14 +80,16 @@ NetEBAdd::NetEBAdd(char op, NetExpr*l, NetExpr*r)
}
unsigned pad_width = lossless_flag? 1 : 0;
/* Now that we have the operand sizes the way we like, or as
good as we are going to get them, set the size of myself. */
if (r->expr_width() > l->expr_width()) {
expr_width(r->expr_width());
expr_width(r->expr_width() + pad_width);
} else {
expr_width(l->expr_width());
expr_width(l->expr_width() + pad_width);
}
cast_signed(l->has_sign() && r->has_sign());
@@ -252,7 +259,8 @@ NetEBPow::NetEBPow(char op, NetExpr*l, NetExpr*r)
: NetEBinary(op, l, r)
{
assert(op == 'p');
expr_width(l->expr_width());
/* This is incorrect! a * (2^b - 1) is close. */
expr_width(l->expr_width()+r->expr_width());
cast_signed(l->has_sign() || r->has_sign());
}
@@ -359,24 +367,16 @@ unsigned NetEConcat::repeat()
if (repeat_calculated_)
return repeat_value_;
assert(repeat_);
if (! dynamic_cast<NetEConst*>(repeat_)) {
NetExpr*tmp = repeat_->eval_tree();
if (tmp != 0) {
delete repeat_;
repeat_ = tmp;
}
}
eval_expr(repeat_);
NetEConst*repeat_const = dynamic_cast<NetEConst*>(repeat_);
/* This should not be possible, as it was checked earlier to
assure that this is a constant expression. */
if (repeat_const == 0) {
cerr << get_line() << ": internal error: repeat expression "
cerr << get_fileline() << ": internal error: repeat expression "
<< "is not a compile time constant." << endl;
cerr << get_line() << ": : Expression is: "
cerr << get_fileline() << ": : Expression is: "
<< *repeat_ << endl;
repeat_calculated_ = true;
repeat_value_ = 1;
@@ -401,6 +401,7 @@ unsigned NetEConcat::repeat() const
NetECReal::NetECReal(const verireal&val)
: value_(val)
{
expr_width(1);
}
NetECReal::~NetECReal()
@@ -557,103 +558,3 @@ ivl_variable_type_t NetESFunc::expr_type() const
{
return type_;
}
/*
* $Log: net_expr.cc,v $
* Revision 1.27 2006/07/31 03:50:17 steve
* Add support for power in constant expressions.
*
* Revision 1.26 2005/11/26 00:35:43 steve
* More precise about r-value width of constants.
*
* Revision 1.25 2005/09/14 02:53:14 steve
* Support bool expressions and compares handle them optimally.
*
* Revision 1.24 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.23 2004/10/04 01:10:54 steve
* Clean up spurious trailing white space.
*
* Revision 1.22 2004/02/20 06:22:56 steve
* parameter keys are per_strings.
*
* Revision 1.21 2003/08/28 04:11:19 steve
* Spelling patch.
*
* Revision 1.20 2003/06/18 03:55:18 steve
* Add arithmetic shift operators.
*
* Revision 1.19 2003/06/15 18:53:20 steve
* Operands of unsigned multiply are unsigned.
*
* Revision 1.18 2003/05/30 02:55:32 steve
* Support parameters in real expressions and
* as real expressions, and fix multiply and
* divide with real results.
*
* Revision 1.17 2003/05/20 15:05:33 steve
* Do not try to set constants to width 0.
*
* Revision 1.16 2003/03/15 18:08:43 steve
* Comparison operators do have defined width.
*
* Revision 1.15 2003/03/15 04:46:29 steve
* Better organize the NetESFunc return type guesses.
*
* Revision 1.14 2003/03/01 06:25:30 steve
* Add the lex_strings string handler, and put
* scope names and system task/function names
* into this table. Also, permallocate event
* names from the beginning.
*
* Revision 1.13 2003/02/06 17:50:23 steve
* Real constants have no defined vector width
*
* Revision 1.12 2003/01/27 00:14:37 steve
* Support in various contexts the $realtime
* system task.
*
* Revision 1.11 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions.
*
* Revision 1.10 2002/11/09 01:40:19 steve
* Postpone parameter width check to evaluation.
*
* Revision 1.9 2002/11/06 02:25:13 steve
* No need to keep excess width from an
* unsigned constant value, if it can
* be trimmed safely.
*
* Revision 1.8 2002/10/19 22:59:49 steve
* Redo the parameter vector support to allow
* parameter names in range expressions.
*
* Revision 1.7 2002/09/01 03:01:48 steve
* Properly cast signedness of parameters with ranges.
*
* Revision 1.6 2002/08/12 01:34:59 steve
* conditional ident string using autoconfig.
*
* Revision 1.5 2002/06/06 18:57:18 steve
* Use standard name for iostream.
*
* Revision 1.4 2002/05/25 16:51:37 steve
* include iostream for gcc 3.1
*
* Revision 1.3 2002/05/05 21:11:50 steve
* Put off evaluation of concatenation repeat expresions
* until after parameters are defined. This allows parms
* to be used in repeat expresions.
*
* Add the builtin $signed system function.
*
* Revision 1.2 2002/01/29 22:36:31 steve
* include config.h to eliminate warnings.
*
* Revision 1.1 2002/01/28 01:39:45 steve
* Add ne_expr.cc
*
*/
+25 -42
View File
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: net_func.cc,v 1.10 2007/06/02 03:42:13 steve Exp $"
#endif
# include "config.h"
# include "netlist.h"
@@ -52,6 +49,24 @@ NetUserFunc::~NetUserFunc()
{
}
ivl_variable_type_t NetUserFunc::data_type(unsigned port) const
{
NetFuncDef*def = def_->func_def();
/* Port 0 is the return port. */
if (port == 0) {
const NetNet*sig = def->return_sig();
assert(sig);
return sig->data_type();
}
port -= 1;
assert(port < def->port_count());
const NetNet*port_sig = def->port(port);
return port_sig->data_type();
}
unsigned NetUserFunc::port_width(unsigned port) const
{
NetFuncDef*def = def_->func_def();
@@ -94,14 +109,14 @@ bool PECallFunction::check_call_matches_definition_(Design*des, NetScope*dscope)
parms_count = 0;
if (dscope->type() != NetScope::FUNC) {
cerr << get_line() << ": error: Attempt to call scope "
cerr << get_fileline() << ": error: Attempt to call scope "
<< scope_path(dscope) << " as a function." << endl;
des->errors += 1;
return false;
}
if (parms_count != dscope->func_def()->port_count()) {
cerr << get_line() << ": error: Function " << scope_path(dscope)
cerr << get_fileline() << ": error: Function " << scope_path(dscope)
<< " expects " << (dscope->func_def()->port_count())
<< " arguments, you passed " << parms_count << "."
<< endl;
@@ -141,45 +156,13 @@ const char*NetSysFunc::func_name() const
return def_->name;
}
ivl_variable_type_t NetSysFunc::data_type() const
{
return def_->type;
}
unsigned NetSysFunc::vector_width() const
{
return def_->wid;
}
/*
* $Log: net_func.cc,v $
* Revision 1.10 2007/06/02 03:42:13 steve
* Properly evaluate scope path expressions.
*
* Revision 1.9 2007/04/17 04:17:47 steve
* Fix argument count in function error message.
*
* Revision 1.8 2006/06/18 04:15:50 steve
* Add support for system functions in continuous assignments.
*
* Revision 1.7 2005/03/18 02:56:03 steve
* Add support for LPM_UFUNC user defined functions.
*
* Revision 1.6 2004/05/31 23:34:37 steve
* Rewire/generalize parsing an elaboration of
* function return values to allow for better
* speed and more type support.
*
* Revision 1.5 2004/02/18 17:11:56 steve
* Use perm_strings for named langiage items.
*
* Revision 1.4 2003/03/06 00:28:41 steve
* All NetObj objects have lex_string base names.
*
* Revision 1.3 2002/08/12 01:34:59 steve
* conditional ident string using autoconfig.
*
* Revision 1.2 2002/03/31 04:07:40 steve
* Update for gcc 3.0
*
* Revision 1.1 2002/03/09 02:10:22 steve
* Add the NetUserFunc netlist node.
*
*/
+19
View File
@@ -26,6 +26,7 @@
# include "netlist.h"
# include <sstream>
# include <cstring>
# include <string>
# include <typeinfo>
#ifdef HAVE_MALLOC_H
@@ -100,6 +101,11 @@ Link::DIR Link::get_dir() const
return dir_;
}
void Link::drivers_delays(NetExpr*rise, NetExpr*fall, NetExpr*decay)
{
nexus_->drivers_delays(rise, fall, decay);
}
void Link::drive0(Link::strength_t str)
{
drive0_ = str;
@@ -244,6 +250,19 @@ verinum::V Nexus::get_init() const
return verinum::Vz;
}
void Nexus::drivers_delays(NetExpr*rise, NetExpr*fall, NetExpr*decay)
{
for (Link*cur = list_ ; cur ; cur = cur->next_) {
if (cur->get_dir() != Link::OUTPUT)
continue;
NetObj*obj = cur->get_obj();
obj->rise_time(rise);
obj->fall_time(fall);
obj->decay_time(decay);
}
}
void Nexus::unlink(Link*that)
{
if (name_) {
+75 -140
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
* Copyright (c) 2002-2007 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: net_nex_input.cc,v 1.16 2007/01/16 05:44:15 steve Exp $"
#endif
# include "config.h"
@@ -29,36 +26,36 @@
# include "netlist.h"
# include "netmisc.h"
NexusSet* NetExpr::nex_input()
NexusSet* NetExpr::nex_input(bool rem_out)
{
cerr << get_line()
cerr << get_fileline()
<< ": internal error: nex_input not implemented: "
<< *this << endl;
return 0;
}
NexusSet* NetProc::nex_input()
NexusSet* NetProc::nex_input(bool rem_out)
{
cerr << get_line()
cerr << get_fileline()
<< ": internal error: NetProc::nex_input not implemented"
<< endl;
return 0;
}
NexusSet* NetEBinary::nex_input()
NexusSet* NetEBinary::nex_input(bool rem_out)
{
NexusSet*result = left_->nex_input();
NexusSet*tmp = right_->nex_input();
NexusSet*result = left_->nex_input(rem_out);
NexusSet*tmp = right_->nex_input(rem_out);
result->add(*tmp);
delete tmp;
return result;
}
NexusSet* NetEConcat::nex_input()
NexusSet* NetEConcat::nex_input(bool rem_out)
{
NexusSet*result = parms_[0]->nex_input();
NexusSet*result = parms_[0]->nex_input(rem_out);
for (unsigned idx = 1 ; idx < parms_.count() ; idx += 1) {
NexusSet*tmp = parms_[idx]->nex_input();
NexusSet*tmp = parms_[idx]->nex_input(rem_out);
result->add(*tmp);
delete tmp;
}
@@ -68,12 +65,12 @@ NexusSet* NetEConcat::nex_input()
/*
* A constant has not inputs, so always return an empty set.
*/
NexusSet* NetEConst::nex_input()
NexusSet* NetEConst::nex_input(bool rem_out)
{
return new NexusSet;
}
NexusSet* NetECReal::nex_input()
NexusSet* NetECReal::nex_input(bool rem_out)
{
return new NexusSet;
}
@@ -82,45 +79,45 @@ NexusSet* NetECReal::nex_input()
* A parameter by definition has no inputs. It represents a constant
* value, even if that value is a constant expression.
*/
NexusSet* NetEParam::nex_input()
NexusSet* NetEParam::nex_input(bool rem_out)
{
return new NexusSet;
}
NexusSet* NetEEvent::nex_input()
NexusSet* NetEEvent::nex_input(bool rem_out)
{
return new NexusSet;
}
NexusSet* NetEScope::nex_input()
NexusSet* NetEScope::nex_input(bool rem_out)
{
return new NexusSet;
}
NexusSet* NetESelect::nex_input()
NexusSet* NetESelect::nex_input(bool rem_out)
{
NexusSet*result = base_? base_->nex_input() : new NexusSet();
NexusSet*tmp = expr_->nex_input();
NexusSet*result = base_? base_->nex_input(rem_out) : new NexusSet();
NexusSet*tmp = expr_->nex_input(rem_out);
result->add(*tmp);
delete tmp;
return result;
}
NexusSet* NetESFunc::nex_input()
NexusSet* NetESFunc::nex_input(bool rem_out)
{
if (nparms_ == 0)
return new NexusSet;
NexusSet*result = parms_[0]->nex_input();
NexusSet*result = parms_[0]->nex_input(rem_out);
for (unsigned idx = 1 ; idx < nparms_ ; idx += 1) {
NexusSet*tmp = parms_[idx]->nex_input();
NexusSet*tmp = parms_[idx]->nex_input(rem_out);
result->add(*tmp);
delete tmp;
}
return result;
}
NexusSet* NetESignal::nex_input()
NexusSet* NetESignal::nex_input(bool rem_out)
{
NexusSet*result = new NexusSet;
for (unsigned idx = 0 ; idx < net_->pin_count() ; idx += 1)
@@ -129,27 +126,27 @@ NexusSet* NetESignal::nex_input()
return result;
}
NexusSet* NetETernary::nex_input()
NexusSet* NetETernary::nex_input(bool rem_out)
{
NexusSet*tmp;
NexusSet*result = cond_->nex_input();
NexusSet*result = cond_->nex_input(rem_out);
tmp = true_val_->nex_input();
tmp = true_val_->nex_input(rem_out);
result->add(*tmp);
delete tmp;
tmp = false_val_->nex_input();
tmp = false_val_->nex_input(rem_out);
result->add(*tmp);
delete tmp;
return result;
}
NexusSet* NetEUFunc::nex_input()
NexusSet* NetEUFunc::nex_input(bool rem_out)
{
NexusSet*result = new NexusSet;
for (unsigned idx = 0 ; idx < parms_.count() ; idx += 1) {
NexusSet*tmp = parms_[idx]->nex_input();
NexusSet*tmp = parms_[idx]->nex_input(rem_out);
result->add(*tmp);
delete tmp;
}
@@ -157,21 +154,21 @@ NexusSet* NetEUFunc::nex_input()
return result;
}
NexusSet* NetEUnary::nex_input()
NexusSet* NetEUnary::nex_input(bool rem_out)
{
return expr_->nex_input();
return expr_->nex_input(rem_out);
}
NexusSet* NetAssign_::nex_input()
NexusSet* NetAssign_::nex_input(bool rem_out)
{
NexusSet*result = new NexusSet;
if (word_) {
NexusSet*tmp = word_->nex_input();
NexusSet*tmp = word_->nex_input(rem_out);
result->add(*tmp);
delete tmp;
}
if (base_) {
NexusSet*tmp = base_->nex_input();
NexusSet*tmp = base_->nex_input(rem_out);
result->add(*tmp);
delete tmp;
}
@@ -179,15 +176,15 @@ NexusSet* NetAssign_::nex_input()
return result;
}
NexusSet* NetAssignBase::nex_input()
NexusSet* NetAssignBase::nex_input(bool rem_out)
{
NexusSet*result = rval_->nex_input();
NexusSet*result = rval_->nex_input(rem_out);
/* It is possible that the lval_ can hav nex_input values. In
/* It is possible that the lval_ can have nex_input values. In
particular, index expressions are statement inputs as well,
so should be addressed here. */
for (NetAssign_*cur = lval_ ; cur ; cur = cur->more) {
NexusSet*tmp = cur->nex_input();
NexusSet*tmp = cur->nex_input(rem_out);
result->add(*tmp);
delete tmp;
}
@@ -212,13 +209,13 @@ NexusSet* NetAssignBase::nex_input()
* In this example, "t" should not be in the input set because it is
* used by the sequence as a temporary value.
*/
NexusSet* NetBlock::nex_input()
NexusSet* NetBlock::nex_input(bool rem_out)
{
if (last_ == 0)
return new NexusSet;
if (type_ == PARA) {
cerr << get_line() << ": internal error: Sorry, "
cerr << get_fileline() << ": internal error: Sorry, "
<< "I don't know how to synthesize fork/join blocks."
<< endl;
return 0;
@@ -232,24 +229,24 @@ NexusSet* NetBlock::nex_input()
do {
/* Get the inputs for the current statement. */
NexusSet*tmp = cur->nex_input();
NexusSet*tmp = cur->nex_input(rem_out);
/* Remove from the input set those bits that are outputs
from previous statements. They aren't really inputs
to the block, just internal intermediate values. */
tmp->rem(*prev);
/* Add the corrected set to the accumulated input set. */
/* Add the current input set to the accumulated input set. */
result->add(*tmp);
delete tmp;
/* Add the current outputs to the accumulated output
set, for processing of later statements. */
/* Add the current outputs to the accumulated output set,
so they can be removed from the input set below. */
cur->nex_output(*prev);
cur = cur->next_;
} while (cur != last_->next_);
/* Remove from the input set those bits that are outputs
from other statements. They aren't really inputs
to the block, just internal intermediate values. */
if (rem_out) result->rem(*prev);
return result;
}
@@ -258,9 +255,9 @@ NexusSet* NetBlock::nex_input()
* the inputs to all the guards, and the inputs to all the guarded
* statements.
*/
NexusSet* NetCase::nex_input()
NexusSet* NetCase::nex_input(bool rem_out)
{
NexusSet*result = expr_->nex_input();
NexusSet*result = expr_->nex_input(rem_out);
if (result == 0)
return 0;
@@ -270,7 +267,7 @@ NexusSet* NetCase::nex_input()
if (items_[idx].statement == 0)
continue;
NexusSet*tmp = items_[idx].statement->nex_input();
NexusSet*tmp = items_[idx].statement->nex_input(rem_out);
assert(tmp);
result->add(*tmp);
delete tmp;
@@ -279,7 +276,7 @@ NexusSet* NetCase::nex_input()
case is special and is identified by a null
guard. The default guard obviously has no input. */
if (items_[idx].guard) {
tmp = items_[idx].guard->nex_input();
tmp = items_[idx].guard->nex_input(rem_out);
assert(tmp);
result->add(*tmp);
delete tmp;
@@ -289,24 +286,24 @@ NexusSet* NetCase::nex_input()
return result;
}
NexusSet* NetCAssign::nex_input()
NexusSet* NetCAssign::nex_input(bool rem_out)
{
cerr << get_line() << ": internal warning: NetCAssign::nex_input()"
cerr << get_fileline() << ": internal warning: NetCAssign::nex_input()"
<< " not implemented." << endl;
return new NexusSet;
}
NexusSet* NetCondit::nex_input()
NexusSet* NetCondit::nex_input(bool rem_out)
{
NexusSet*result = expr_->nex_input();
NexusSet*result = expr_->nex_input(rem_out);
if (if_ != 0) {
NexusSet*tmp = if_->nex_input();
NexusSet*tmp = if_->nex_input(rem_out);
result->add(*tmp);
delete tmp;
}
if (else_ != 0) {
NexusSet*tmp = else_->nex_input();
NexusSet*tmp = else_->nex_input(rem_out);
result->add(*tmp);
delete tmp;
}
@@ -314,16 +311,16 @@ NexusSet* NetCondit::nex_input()
return result;
}
NexusSet* NetForce::nex_input()
NexusSet* NetForce::nex_input(bool rem_out)
{
cerr << get_line() << ": internal warning: NetForce::nex_input()"
cerr << get_fileline() << ": internal warning: NetForce::nex_input()"
<< " not implemented." << endl;
return new NexusSet;
}
NexusSet* NetForever::nex_input()
NexusSet* NetForever::nex_input(bool rem_out)
{
NexusSet*result = statement_->nex_input();
NexusSet*result = statement_->nex_input(rem_out);
return result;
}
@@ -336,29 +333,29 @@ NexusSet* NetForever::nex_input()
* include the input set of the <expr> because it does not affect the
* result.
*/
NexusSet* NetPDelay::nex_input()
NexusSet* NetPDelay::nex_input(bool rem_out)
{
NexusSet*result = statement_->nex_input();
NexusSet*result = statement_->nex_input(rem_out);
return result;
}
NexusSet* NetRepeat::nex_input()
NexusSet* NetRepeat::nex_input(bool rem_out)
{
NexusSet*result = statement_->nex_input();
NexusSet*tmp = expr_->nex_input();
NexusSet*result = statement_->nex_input(rem_out);
NexusSet*tmp = expr_->nex_input(rem_out);
result->add(*tmp);
delete tmp;
return result;
}
NexusSet* NetSTask::nex_input()
NexusSet* NetSTask::nex_input(bool rem_out)
{
if (parms_.count() == 0)
return new NexusSet;
NexusSet*result = parms_[0]->nex_input();
NexusSet*result = parms_[0]->nex_input(rem_out);
for (unsigned idx = 1 ; idx < parms_.count() ; idx += 1) {
NexusSet*tmp = parms_[idx]->nex_input();
NexusSet*tmp = parms_[idx]->nex_input(rem_out);
result->add(*tmp);
delete tmp;
}
@@ -371,79 +368,17 @@ NexusSet* NetSTask::nex_input()
* parameters to consider, because the compiler already removed them
* and converted them to blocking assignments.
*/
NexusSet* NetUTask::nex_input()
NexusSet* NetUTask::nex_input(bool rem_out)
{
return new NexusSet;
}
NexusSet* NetWhile::nex_input()
NexusSet* NetWhile::nex_input(bool rem_out)
{
NexusSet*result = proc_->nex_input();
NexusSet*tmp = cond_->nex_input();
NexusSet*result = proc_->nex_input(rem_out);
NexusSet*tmp = cond_->nex_input(rem_out);
result->add(*tmp);
delete tmp;
return result;
}
/*
* $Log: net_nex_input.cc,v $
* Revision 1.16 2007/01/16 05:44:15 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.15 2006/04/16 00:15:43 steve
* Fix part selects in l-values.
*
* Revision 1.14 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.13 2005/01/24 05:28:30 steve
* Remove the NetEBitSel and combine all bit/part select
* behavior into the NetESelect node and IVL_EX_SELECT
* ivl_target expression type.
*
* Revision 1.12 2004/09/04 04:24:15 steve
* PR1026: assignment statements can have sensitivities in the l-values.
*
* Revision 1.11 2003/10/26 04:50:46 steve
* Case with empty statements has no inputs.
*
* Revision 1.10 2003/07/26 03:34:42 steve
* Start handling pad of expressions in code generators.
*
* Revision 1.9 2003/04/22 04:48:29 steve
* Support event names as expressions elements.
*
* Revision 1.8 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions.
*
* Revision 1.7 2002/11/16 05:45:41 steve
* Handle default: case in net_inputs for NetCase.
*
* Revision 1.6 2002/08/18 22:07:16 steve
* Detect temporaries in sequential block synthesis.
*
* Revision 1.5 2002/08/12 01:34:59 steve
* conditional ident string using autoconfig.
*
* Revision 1.4 2002/07/14 23:47:58 steve
* Infinite loop in nex_input of NetBlock objects.
*
* Revision 1.3 2002/06/05 03:44:25 steve
* Add support for memory words in l-value of
* non-blocking assignments, and remove the special
* NetAssignMem_ and NetAssignMemNB classes.
*
* Revision 1.2 2002/04/21 17:43:12 steve
* implement nex_input for behavioral statements.
*
* Revision 1.1 2002/04/21 04:59:08 steve
* Add support for conbinational events by finding
* the inputs to expressions and some statements.
* Get case and assignment statements working.
*
*/
+5 -57
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2002 Stephen Williams (steve@icarus.com)
* Copyright (c) 2002-2007 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,9 +16,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: net_nex_output.cc,v 1.14 2007/04/17 04:34:23 steve Exp $"
#endif
# include "config.h"
@@ -31,10 +28,10 @@
void NetProc::nex_output(NexusSet&out)
{
cerr << get_line()
cerr << get_fileline()
<< ": internal error: NetProc::nex_output not implemented"
<< endl;
cerr << get_line()
cerr << get_fileline()
<< ": : on object type " << typeid(*this).name()
<< endl;
}
@@ -53,7 +50,7 @@ void NetAssignBase::nex_output(NexusSet&out)
* "This is not a node because memory objects can only be
* accessed by behavioral code."
*/
cerr << get_line() << ": internal error: "
cerr << get_fileline() << ": internal error: "
<< "NetAssignBase::nex_output on unsupported lval ";
dump_lval(cerr);
cerr << endl;
@@ -108,7 +105,7 @@ void NetPDelay::nex_output(NexusSet&out)
/*
* For the purposes of synthesis, system task calls have no output at
* all. This is OK because most system tasks are not synthesizeable in
* all. This is OK because most system tasks are not synthesizable in
* the first place.
*/
void NetSTask::nex_output(NexusSet&out)
@@ -129,52 +126,3 @@ void NetWhile::nex_output(NexusSet&out)
if (proc_ != 0)
proc_->nex_output(out);
}
/*
* $Log: net_nex_output.cc,v $
* Revision 1.14 2007/04/17 04:34:23 steve
* Fix handling calls to tasks in combinational always block
*
* Revision 1.13 2007/04/05 01:53:52 steve
* Probe of case statement inputs can skip nul statements.
*
* Revision 1.12 2005/02/14 04:58:50 steve
* l-value input may be a vector.
*
* Revision 1.11 2004/09/16 03:17:33 steve
* net_output handles l-value concatenations.
*
* Revision 1.10 2004/08/28 16:23:05 steve
* Fix use of system tasks in AT_STAR statements.
*
* Revision 1.9 2004/06/30 15:32:18 steve
* nex_output for NetPDelay statements.
*
* Revision 1.8 2003/12/20 00:59:31 steve
* Synthesis debug messages.
*
* Revision 1.7 2003/10/26 04:51:39 steve
* Output of While is output of while substatement.
*
* Revision 1.6 2002/09/17 04:39:20 steve
* Account for part select in l-value.
*
* Revision 1.5 2002/08/12 01:34:59 steve
* conditional ident string using autoconfig.
*
* Revision 1.4 2002/07/29 00:00:28 steve
* Asynchronous synthesis of sequential blocks.
*
* Revision 1.3 2002/07/07 22:32:15 steve
* Asynchronous synthesis of case statements.
*
* Revision 1.2 2002/07/01 00:54:21 steve
* synth_asych of if/else requires redirecting the target
* if sub-statements. Use NetNet objects to manage the
* situation.
*
* Revision 1.1 2002/06/30 02:21:32 steve
* Add structure for asynchronous logic synthesis.
*
*/
+26 -118
View File
@@ -24,6 +24,7 @@
# include "compiler.h"
# include "netlist.h"
# include <cstring>
# include <sstream>
/*
@@ -90,6 +91,24 @@ NetExpr* NetScope::set_parameter(perm_string key, NetExpr*expr,
return res;
}
bool NetScope::auto_name(const char*prefix, char pad, const char* suffix)
{
char tmp[32];
int pad_pos = strlen(prefix);
int max_pos = sizeof(tmp) - strlen(suffix) - 1;
strncpy(tmp, prefix, sizeof(tmp));
while (pad_pos <= max_pos) {
strcat(tmp + pad_pos, suffix);
hname_t new_name(lex_strings.make(tmp));
if (!up_->child(new_name)) {
name_ = new_name;
return true;
}
tmp[pad_pos++] = pad;
}
return false;
}
/*
* Return false if this creates a new parameter.
*/
@@ -190,6 +209,10 @@ NetFuncDef* NetScope::func_def()
assert( type_ == FUNC );
return func_;
}
bool NetScope::in_func()
{
return (type_ == FUNC) ? true : false;
}
const NetFuncDef* NetScope::func_def() const
{
@@ -272,10 +295,10 @@ void NetScope::rem_event(NetEvent*ev)
}
NetEvent* NetScope::find_event(const char*name)
NetEvent* NetScope::find_event(perm_string name)
{
for (NetEvent*cur = events_; cur ; cur = cur->snext_)
if (strcmp(cur->name(), name) == 0)
if (cur->name() == name)
return cur;
return 0;
@@ -314,7 +337,7 @@ void NetScope::rem_signal(NetNet*net)
* is assumed to be the base name of the signal, so no sub-scopes are
* searched.
*/
NetNet* NetScope::find_signal(const char*key)
NetNet* NetScope::find_signal(perm_string key)
{
if (signals_ == 0)
return 0;
@@ -381,118 +404,3 @@ string NetScope::local_hsymbol()
}
#endif
/*
* $Log: net_scope.cc,v $
* Revision 1.38 2007/06/02 03:42:13 steve
* Properly evaluate scope path expressions.
*
* Revision 1.37 2007/04/26 03:06:22 steve
* Rework hname_t to use perm_strings.
*
* Revision 1.36 2007/01/16 05:44:15 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.35 2005/11/27 05:56:20 steve
* Handle bit select of parameter with ranges.
*
* Revision 1.34 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.33 2004/10/04 01:10:54 steve
* Clean up spurious trailing white space.
*
* Revision 1.32 2004/06/13 04:56:54 steve
* Add support for the default_nettype directive.
*
* Revision 1.31 2004/02/20 06:22:56 steve
* parameter keys are per_strings.
*
* Revision 1.30 2004/02/18 17:11:56 steve
* Use perm_strings for named langiage items.
*
* Revision 1.29 2003/09/13 01:30:07 steve
* Missing case warnings.
*
* Revision 1.28 2003/03/10 23:40:53 steve
* Keep parameter constants for the ivl_target API.
*
* Revision 1.27 2003/03/06 04:37:12 steve
* lex_strings.add module names earlier.
*
* Revision 1.26 2003/03/06 00:28:41 steve
* All NetObj objects have lex_string base names.
*
* Revision 1.25 2003/03/01 06:25:30 steve
* Add the lex_strings string handler, and put
* scope names and system task/function names
* into this table. Also, permallocate event
* names from the beginning.
*
* Revision 1.24 2003/01/27 05:09:17 steve
* Spelling fixes.
*
* Revision 1.23 2003/01/26 21:15:58 steve
* Rework expression parsing and elaboration to
* accommodate real/realtime values and expressions.
*
* Revision 1.22 2003/01/14 21:16:18 steve
* Move strstream to ostringstream for compatibility.
*
* Revision 1.21 2002/12/07 02:49:24 steve
* Named event triggers can take hierarchical names.
*
* Revision 1.20 2002/10/19 22:59:49 steve
* Redo the parameter vector support to allow
* parameter names in range expressions.
*
* Revision 1.19 2002/08/12 01:34:59 steve
* conditional ident string using autoconfig.
*
* Revision 1.18 2002/08/05 04:18:45 steve
* Store only the base name of memories.
*
* Revision 1.17 2002/07/22 21:07:08 steve
* Initialize the lcounter_ to 0.
*
* Revision 1.16 2001/12/03 04:47:15 steve
* Parser and pform use hierarchical names as hname_t
* objects instead of encoded strings.
*
* Revision 1.15 2001/11/08 05:15:50 steve
* Remove string paths from PExpr elaboration.
*
* Revision 1.14 2001/10/20 05:21:51 steve
* Scope/module names are char* instead of string.
*
* Revision 1.13 2001/07/25 03:10:49 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.12 2001/07/04 04:34:06 steve
* Scope-locals use _s instead of _l.
*
* Revision 1.11 2000/12/16 01:45:48 steve
* Detect recursive instantiations (PR#2)
*
* Revision 1.10 2000/10/06 23:46:50 steve
* ivl_target updates, including more complete
* handling of ivl_nexus_t objects. Much reduced
* dependencies on pointers to netlist objects.
*
* Revision 1.9 2000/08/27 15:51:50 steve
* t-dll iterates signals, and passes them to the
* target module.
*
* Some of NetObj should return char*, not string.
*
* Revision 1.8 2000/07/30 18:25:44 steve
* Rearrange task and function elaboration so that the
* NetTaskDef and NetFuncDef functions are created during
* signal enaboration, and carry these objects in the
* NetScope class instead of the extra, useless map in
* the Design class.
*/
+96 -165
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 1998-2004 Stephen Williams (steve@icarus.com)
* Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,15 +16,13 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: netlist.cc,v 1.258 2007/06/02 03:42:13 steve Exp $"
#endif
# include "config.h"
# include <iostream>
# include <typeinfo>
# include <cstdlib>
# include "compiler.h"
# include "netlist.h"
# include "netmisc.h"
@@ -201,9 +199,9 @@ const NetScope* NetObj::scope() const
Link& NetObj::pin(unsigned idx)
{
if (idx >= npins_) {
cerr << get_line() << ": internal error: pin("<<idx<<")"
cerr << get_fileline() << ": internal error: pin("<<idx<<")"
<< " out of bounds("<<npins_<<")" << endl;
cerr << get_line() << ": : typeid="
cerr << get_fileline() << ": : typeid="
<< typeid(*this).name() << endl;
}
@@ -404,6 +402,7 @@ NetNet::NetNet(NetScope*s, perm_string n, Type t, unsigned npins)
local_flag_(false), eref_count_(0), lref_count_(0)
{
assert(s);
assert(npins>0);
verinum::V init_value = verinum::Vz;
Link::DIR dir = Link::PASSIVE;
@@ -525,14 +524,14 @@ NetNet::NetNet(NetScope*s, perm_string n, Type t,
NetNet::~NetNet()
{
if (eref_count_ > 0) {
cerr << get_line() << ": internal error: attempt to delete "
cerr << get_fileline() << ": internal error: attempt to delete "
<< "signal ``" << name() << "'' which has "
<< "expression references." << endl;
dump_net(cerr, 4);
}
assert(eref_count_ == 0);
if (lref_count_ > 0) {
cerr << get_line() << ": internal error: attempt to delete "
cerr << get_fileline() << ": internal error: attempt to delete "
<< "signal ``" << name() << "'' which has "
<< "assign references." << endl;
dump_net(cerr, 4);
@@ -1134,6 +1133,9 @@ NetArrayDq::NetArrayDq(NetScope*s, perm_string n, NetNet*mem, unsigned awid)
pin(0).set_name(perm_string::literal("Result"), 0);
pin(1).set_dir(Link::INPUT);
pin(1).set_name(perm_string::literal("Address"), 0);
// Increment the expression reference count for the target
// memory so that it is not deleted underneath me.
mem->incr_eref();
}
NetArrayDq::~NetArrayDq()
@@ -1555,6 +1557,78 @@ const Link& NetMult::pin_DataB() const
return pin(2);
}
NetPow::NetPow(NetScope*sc, perm_string n, unsigned wr,
unsigned wa, unsigned wb)
: NetNode(sc, n, 3),
signed_(false), width_r_(wr), width_a_(wa), width_b_(wb)
{
pin(0).set_dir(Link::OUTPUT);
pin(0).set_name(perm_string::literal("Result"), 0);
pin(1).set_dir(Link::INPUT);
pin(1).set_name(perm_string::literal("DataA"), 0);
pin(2).set_dir(Link::INPUT);
pin(2).set_name(perm_string::literal("DataB"), 0);
}
NetPow::~NetPow()
{
}
void NetPow::set_signed(bool flag)
{
signed_ = flag;
}
bool NetPow::get_signed() const
{
return signed_;
}
unsigned NetPow::width_r() const
{
return width_r_;
}
unsigned NetPow::width_a() const
{
return width_a_;
}
unsigned NetPow::width_b() const
{
return width_b_;
}
Link& NetPow::pin_Result()
{
return pin(0);
}
const Link& NetPow::pin_Result() const
{
return pin(0);
}
Link& NetPow::pin_DataA()
{
return pin(1);
}
const Link& NetPow::pin_DataA() const
{
return pin(1);
}
Link& NetPow::pin_DataB()
{
return pin(2);
}
const Link& NetPow::pin_DataB() const
{
return pin(2);
}
/*
* The NetMux class represents an LPM_MUX device. The pinout is assigned
* like so:
@@ -1844,8 +1918,9 @@ const NetExpr* NetSTask::parm(unsigned idx) const
return parms_[idx];
}
NetEUFunc::NetEUFunc(NetScope*def, NetESignal*res, svector<NetExpr*>&p)
: func_(def), result_sig_(res), parms_(p)
NetEUFunc::NetEUFunc(NetScope*scope, NetScope*def, NetESignal*res,
svector<NetExpr*>&p)
: scope_(scope), func_(def), result_sig_(res), parms_(p)
{
expr_width(result_sig_->expr_width());
}
@@ -2002,7 +2077,7 @@ NetEBLogic* NetEBLogic::dup_expr() const
NetEConst::NetEConst(const verinum&val)
: NetExpr(val.len()), value_(val)
{
cast_signed(value_.has_sign());
cast_signed_base_(value_.has_sign());
}
NetEConst::~NetEConst()
@@ -2188,6 +2263,16 @@ ivl_variable_type_t NetETernary::expr_type() const
if (tru == IVL_VT_BOOL && fal == IVL_VT_LOGIC)
return IVL_VT_LOGIC;
if (tru == IVL_VT_REAL && (fal == IVL_VT_LOGIC || fal == IVL_VT_BOOL))
return IVL_VT_REAL;
if (fal == IVL_VT_REAL && (tru == IVL_VT_LOGIC || tru == IVL_VT_BOOL))
return IVL_VT_REAL;
if (tru != fal) {
cerr << get_fileline() << ": internal error:"
<< " Unexpected ?: type clash:"
<< " tru=" << tru << ", fal=" << fal << endl;
}
ivl_assert(*this, tru == fal);
return tru;
}
@@ -2332,157 +2417,3 @@ const NetProc*NetTaskDef::proc() const
{
return proc_;
}
/*
* $Log: netlist.cc,v $
* Revision 1.258 2007/06/02 03:42:13 steve
* Properly evaluate scope path expressions.
*
* Revision 1.257 2007/04/02 01:12:34 steve
* Seperate arrayness from word count
*
* Revision 1.256 2007/03/02 06:13:22 steve
* Add support for edge sensitive spec paths.
*
* Revision 1.255 2007/03/01 06:19:38 steve
* Add support for conditional specify delay paths.
*
* Revision 1.254 2007/02/20 05:58:36 steve
* Handle unary minus of real valued expressions.
*
* Revision 1.253 2007/02/14 05:59:46 steve
* Handle type of ternary expressions properly.
*
* Revision 1.252 2007/01/19 04:25:37 steve
* Fix missing passive setting for array word pins.
*
* Revision 1.251 2007/01/16 05:44:15 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.250 2006/11/10 04:54:26 steve
* Add test_width methods for PETernary and PEString.
*
* Revision 1.249 2006/09/23 04:57:19 steve
* Basic support for specify timing.
*
* Revision 1.248 2005/09/14 02:53:14 steve
* Support bool expressions and compares handle them optimally.
*
* Revision 1.247 2005/08/06 17:58:16 steve
* Implement bi-directional part selects.
*
* Revision 1.246 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.245 2005/07/07 16:22:49 steve
* Generalize signals to carry types.
*
* Revision 1.244 2005/05/24 01:44:28 steve
* Do sign extension of structuran nets.
*
* Revision 1.243 2005/05/08 23:44:08 steve
* Add support for variable part select.
*
* Revision 1.242 2005/04/24 23:44:02 steve
* Update DFF support to new data flow.
*
* Revision 1.241 2005/04/08 04:51:16 steve
* All memory addresses are signed.
*
* Revision 1.240 2005/04/06 05:29:08 steve
* Rework NetRamDq and IVL_LPM_RAM nodes.
*
* Revision 1.239 2005/03/09 05:52:04 steve
* Handle case inequality in netlists.
*
* Revision 1.238 2005/02/19 02:43:38 steve
* Support shifts and divide.
*
* Revision 1.237 2005/02/12 06:25:40 steve
* Restructure NetMux devices to pass vectors.
* Generate NetMux devices from ternary expressions,
* Reduce NetMux devices to bufif when appropriate.
*
* Revision 1.236 2005/02/08 00:12:36 steve
* Add the NetRepeat node, and code generator support.
*
* Revision 1.235 2005/02/03 04:56:20 steve
* laborate reduction gates into LPM_RED_ nodes.
*
* Revision 1.234 2005/01/28 05:39:33 steve
* Simplified NetMult and IVL_LPM_MULT.
*
* Revision 1.233 2005/01/24 05:28:30 steve
* Remove the NetEBitSel and combine all bit/part select
* behavior into the NetESelect node and IVL_EX_SELECT
* ivl_target expression type.
*
* Revision 1.232 2005/01/22 18:16:01 steve
* Remove obsolete NetSubnet class.
*
* Revision 1.231 2005/01/22 01:06:55 steve
* Change case compare from logic to an LPM node.
*
* Revision 1.230 2005/01/16 04:20:32 steve
* Implement LPM_COMPARE nodes as two-input vector functors.
*
* Revision 1.229 2005/01/09 20:16:01 steve
* Use PartSelect/PV and VP to handle part selects through ports.
*
* Revision 1.228 2004/12/29 23:55:43 steve
* Unify elaboration of l-values for all proceedural assignments,
* including assing, cassign and force.
*
* Generate NetConcat devices for gate outputs that feed into a
* vector results. Use this to hande gate arrays. Also let gate
* arrays handle vectors of gates when the outputs allow for it.
*
* Revision 1.227 2004/12/11 02:31:26 steve
* Rework of internals to carry vectors through nexus instead
* of single bits. Make the ivl, tgt-vvp and vvp initial changes
* down this path.
*
* Revision 1.226 2004/10/04 01:10:54 steve
* Clean up spurious trailing white space.
*
* Revision 1.225 2004/06/30 02:16:26 steve
* Implement signed divide and signed right shift in nets.
*
* Revision 1.224 2004/06/13 04:56:54 steve
* Add support for the default_nettype directive.
*
* Revision 1.223 2004/05/31 23:34:37 steve
* Rewire/generalize parsing an elaboration of
* function return values to allow for better
* speed and more type support.
*
* Revision 1.222 2004/02/20 06:22:56 steve
* parameter keys are per_strings.
*
* Revision 1.221 2004/02/18 17:11:56 steve
* Use perm_strings for named langiage items.
*
* Revision 1.220 2003/11/10 19:44:30 steve
* Fix return value warnings.
*
* Revision 1.219 2003/09/03 23:32:10 steve
* Oops, missing pin_Sset implementation.
*
* Revision 1.218 2003/08/15 02:23:52 steve
* Add synthesis support for synchronous reset.
*
* Revision 1.217 2003/07/05 20:42:08 steve
* Fix some enumeration warnings.
*
* Revision 1.216 2003/06/18 03:55:18 steve
* Add arithmetic shift operators.
*
* Revision 1.215 2003/05/01 01:13:57 steve
* More complete bit range internal error message,
* Better test of part select ranges on non-zero
* signal ranges.
*/
+140 -325
View File
@@ -1,7 +1,7 @@
#ifndef __netlist_H
#define __netlist_H
/*
* Copyright (c) 1998-2006 Stephen Williams (steve@icarus.com)
* Copyright (c) 1998-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: netlist.h,v 1.380 2007/06/02 03:42:13 steve Exp $"
#endif
/*
* The netlist types, as described in this header file, are intended
@@ -151,6 +148,9 @@ class Link {
void set_dir(DIR d);
DIR get_dir() const;
// Set the delay for all the drivers to this nexus.
void drivers_delays(NetExpr*rise, NetExpr*fall, NetExpr*decay);
// A link has a drive strength for 0 and 1 values. The drive0
// strength is for when the link has the value 0, and drive1
// strength is for when the link has a value 1.
@@ -258,6 +258,8 @@ class Nexus {
const char* name() const;
verinum::V get_init() const;
void drivers_delays(NetExpr*rise, NetExpr*fall, NetExpr*decay);
Link*first_nlink();
const Link* first_nlink()const;
@@ -432,9 +434,9 @@ class NetDelaySrc : public NetObj {
/*
* NetNet is a special kind of NetObj that doesn't really do anything,
* but carries the properties of the wire/reg/trireg, including its
* name. Scalers and vectors are all the same thing here, a NetNet
* with a single pin. The difference between a scaler and vector is
* the video of the atomic vector datum it carries.
* name. Scalars and vectors are all the same thing here, a NetNet
* with a single pin. The difference between a scalar and vector is
* the width of the atomic vector datum it carries.
*
* NetNet objects can also appear as side effects of synthesis or
* other abstractions.
@@ -504,7 +506,7 @@ class NetNet : public NetObj {
unsigned long vector_width() const;
/* This method converts a signed index (the type that might be
found in the verilog source) to a pin number. It accounts
found in the Verilog source) to a pin number. It accounts
for variation in the definition of the reg/wire/whatever. */
unsigned sb_to_idx(long sb) const;
@@ -513,7 +515,7 @@ class NetNet : public NetObj {
the pin# from the index. */
bool sb_is_valid(long sb) const;
/* This method returns 0 for scalers and vectors, and greater
/* This method returns 0 for scalars and vectors, and greater
for arrays. The value is the number of array
indices. (Currently only one array index is supported.) */
unsigned array_dimensions() const;
@@ -586,7 +588,7 @@ class NetAddSub : public NetNode {
~NetAddSub();
// Get the width of the device (that is, the width of the
// operands and results.)
// operands and results).
unsigned width() const;
Link& pin_Aclr();
@@ -740,7 +742,7 @@ class NetCompare : public NetNode {
* with pin-1 at the LSB, pin-2 next, and so on. This node is most
* like the NetLogic node, as it has one output at pin 0 and the
* remaining pins are the input that are combined to make the
* output. It is seperated out because it it generally a special case
* output. It is separated out because it it generally a special case
* for the code generators.
*
* When constructing the node, the width is the vector_width of the
@@ -983,17 +985,62 @@ class NetMux : public NetNode {
};
/*
* This class implements a basic LPM_POW combinational power. It
* is used as a structural representation of the ** operator. The
* device has inputs A and B and output Result all with independent
* widths.
*
* NOTE: Check this width thing. I think that the independence of the
* widths is not necessary or even useful.
*/
class NetPow : public NetNode {
public:
NetPow(NetScope*sc, perm_string n, unsigned width,
unsigned wa, unsigned wb);
~NetPow();
bool get_signed() const;
void set_signed(bool);
// Get the width of the device bussed inputs. There are these
// parameterized widths:
unsigned width_r() const; // Result
unsigned width_a() const; // DataA
unsigned width_b() const; // DataB
Link& pin_DataA();
Link& pin_DataB();
Link& pin_Result();
const Link& pin_DataA() const;
const Link& pin_DataB() const;
const Link& pin_Result() const;
virtual void dump_node(ostream&, unsigned ind) const;
virtual bool emit_node(struct target_t*) const;
virtual void functor_node(Design*des, functor_t*fun);
private:
bool signed_;
unsigned width_r_;
unsigned width_a_;
unsigned width_b_;
};
/*
* The NetReplicate node takes a vector input and makes it into a larger
* vector by repeating the input vector some number of times. The
* repeat count is a fixed value. This is just like the repeat
* concatenation of Verilog: {<repeat>{<vector>}}.
*
* When construction this node, the wid is the vector width of the
* When constructing this node, the wid is the vector width of the
* output, and the rpt is the repeat count. The wid must be an even
* multiple of the cnt, and wid/cnt is the expected input width.
*
* The device has exacly 2 pins: pin(0) is the output and pin(1) the
* The device has exactly 2 pins: pin(0) is the output and pin(1) the
* input.
*/
class NetReplicate : public NetNode {
@@ -1024,6 +1071,7 @@ class NetUserFunc : public NetNode {
NetUserFunc(NetScope*s, perm_string n, NetScope*def);
~NetUserFunc();
ivl_variable_type_t data_type(unsigned port) const;
unsigned port_width(unsigned port) const;
const NetScope* def() const;
@@ -1047,6 +1095,7 @@ class NetSysFunc : public NetNode {
unsigned ports);
~NetSysFunc();
ivl_variable_type_t data_type() const;
unsigned vector_width() const;
const char* func_name() const;
@@ -1103,7 +1152,7 @@ class NetExpr : public LineInfo {
// This method returns true if the expression is
// signed. Unsigned expressions return false.
bool has_sign() const;
void cast_signed(bool flag);
virtual void cast_signed(bool flag);
// This returns true if the expression has a definite
// width. This is generally true, but in some cases the
@@ -1122,7 +1171,11 @@ class NetExpr : public LineInfo {
// constants.
//
// The prune_to_width is the maximum width that the result
// should be. If it is -1, then do not prune the result.
// should be. If it is 0 or -1, then do not prune the
// result. If it is -1, go through special efforts to preserve
// values that may expand. A width of 0 corresponds to a
// self-determined context, and a width of -1 corresponds to
// an infinitely wide context.
virtual NetExpr*eval_tree(int prune_to_width = -1);
// Make a duplicate of myself, and subexpressions if I have
@@ -1132,7 +1185,7 @@ class NetExpr : public LineInfo {
// Get the Nexus that are the input to this
// expression. Normally this descends down to the reference to
// a signal that reads from its input.
virtual NexusSet* nex_input() =0;
virtual NexusSet* nex_input(bool rem_out = true) =0;
// Return a version of myself that is structural. This is used
// for converting expressions to gates.
@@ -1141,6 +1194,7 @@ class NetExpr : public LineInfo {
protected:
void expr_width(unsigned w) { width_ = w; }
void cast_signed_base_(bool flag) {signed_flag_ = flag; }
private:
unsigned width_;
@@ -1165,7 +1219,7 @@ class NetEConst : public NetExpr {
const verinum&value() const;
virtual bool set_width(unsigned w, bool last_chance =false);
virtual void cast_signed(bool sign_flag);
virtual bool has_width() const;
virtual ivl_variable_type_t expr_type() const;
@@ -1174,7 +1228,7 @@ class NetEConst : public NetExpr {
virtual NetEConst* dup_expr() const;
virtual NetNet*synthesize(Design*);
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
private:
verinum value_;
@@ -1227,7 +1281,7 @@ class NetECReal : public NetExpr {
virtual NetECReal* dup_expr() const;
virtual NetNet*synthesize(Design*);
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
private:
verireal value_;
@@ -1435,15 +1489,15 @@ class NetLiteral : public NetNode {
* of that value that is important.
*
* All these devices process vectors bitwise, so each bit can be
* logically seperated. The exception is the CONCAT gate, which is
* logically separated. The exception is the CONCAT gate, which is
* really an abstract gate that takes the inputs and turns it into a
* vector of bits.
*/
class NetLogic : public NetNode {
public:
enum TYPE { AND, BUF, BUFIF0, BUFIF1, NAND, NMOS, NOR, NOT,
NOTIF0, NOTIF1, OR, PULLDOWN, PULLUP, RNMOS, RPMOS,
enum TYPE { AND, BUF, BUFIF0, BUFIF1, CMOS, NAND, NMOS, NOR, NOT,
NOTIF0, NOTIF1, OR, PULLDOWN, PULLUP, RCMOS, RNMOS, RPMOS,
PMOS, XNOR, XOR };
explicit NetLogic(NetScope*s, perm_string n, unsigned pins,
@@ -1512,7 +1566,7 @@ class NetUReduce : public NetNode {
/*
* The UDP is a User Defined Primitive from the Verilog source. Do not
* expand it out any further then this in the netlist, as this can be
* expand it out any further than this in the netlist, as this can be
* used to represent target device primitives.
*
* The UDP can be combinational or sequential. The sequential UDP
@@ -1589,7 +1643,7 @@ class NetUDP : public NetNode {
/* =========
* A process is a behavioral-model description. A process is a
* statement that may be compound. the various statement types may
* statement that may be compound. The various statement types may
* refer to places in a netlist (by pointing to nodes) but is not
* linked into the netlist. However, elaborating a process may cause
* special nodes to be created to handle things like events.
@@ -1600,10 +1654,10 @@ class NetProc : public virtual LineInfo {
explicit NetProc();
virtual ~NetProc();
// Find the Nexa that are input by the statement. This is used
// Find the nexa that are input by the statement. This is used
// for example by @* to find the inputs to the process for the
// sensitivity list.
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
// Find the nexa that are set by the statement. Add the output
// values to the set passed as a parameter.
@@ -1625,7 +1679,7 @@ class NetProc : public virtual LineInfo {
// process. Most process types are not.
virtual bool is_synchronous();
// synthesize as asynchronous logic, and return true.
// Synthesize as asynchronous logic, and return true.
virtual bool synth_async(Design*des, NetScope*scope,
const NetBus&nex_map, NetBus&nex_out);
@@ -1694,7 +1748,7 @@ class NetAssign_ {
void set_part(NetExpr* loff, unsigned wid);
// Get the width of the r-value that this node expects. This
// method accounts for the presence of the mux, so it not
// method accounts for the presence of the mux, so it is not
// necessarily the same as the pin_count().
unsigned lwidth() const;
@@ -1712,7 +1766,7 @@ class NetAssign_ {
// being outputs. For example foo[idx] = ... is the l-value
// (NetAssign_ object) with a foo l-value and the input
// expression idx.
NexusSet* nex_input();
NexusSet* nex_input(bool rem_out = true);
// This pointer is for keeping simple lists.
NetAssign_* more;
@@ -1750,7 +1804,7 @@ class NetAssignBase : public NetProc {
void set_delay(NetExpr*);
const NetExpr* get_delay() const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void nex_output(NexusSet&o);
@@ -1837,7 +1891,7 @@ class NetBlock : public NetProc {
// for sequential blocks.
void emit_recurse(struct target_t*) const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void nex_output(NexusSet&);
virtual bool emit_proc(struct target_t*) const;
virtual int match_proc(struct proc_match_t*);
@@ -1851,7 +1905,7 @@ class NetBlock : public NetProc {
};
/*
* A CASE statement in the verilog source leads, eventually, to one of
* A CASE statement in the Verilog source leads, eventually, to one of
* these. This is different from a simple conditional because of the
* way the comparisons are performed. Also, it is likely that the
* target may be able to optimize differently.
@@ -1877,7 +1931,7 @@ class NetCase : public NetProc {
const NetExpr*expr(unsigned idx) const { return items_[idx].guard;}
const NetProc*stat(unsigned idx) const { return items_[idx].statement; }
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void nex_output(NexusSet&out);
bool synth_async(Design*des, NetScope*scope,
@@ -1911,7 +1965,7 @@ class NetCAssign : public NetAssignBase {
explicit NetCAssign(NetAssign_*lv, NetExpr*rv);
~NetCAssign();
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void dump(ostream&, unsigned ind) const;
virtual bool emit_proc(struct target_t*) const;
@@ -1944,7 +1998,7 @@ class NetCondit : public NetProc {
bool emit_recurse_if(struct target_t*) const;
bool emit_recurse_else(struct target_t*) const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void nex_output(NexusSet&o);
bool is_asynchronous();
@@ -2033,7 +2087,7 @@ class NetDisable : public NetProc {
* block and starts the associated statement.
*
* The NetEvTrig class represents trigger statements. Executing this
* statement causes the referenced event to be triggered, which it
* statement causes the referenced event to be triggered, which in
* turn awakens the waiting threads. Each NetEvTrig object references
* exactly one event object.
*
@@ -2221,7 +2275,7 @@ class NetForce : public NetAssignBase {
explicit NetForce(NetAssign_*l, NetExpr*r);
~NetForce();
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void dump(ostream&, unsigned ind) const;
virtual bool emit_proc(struct target_t*) const;
@@ -2239,7 +2293,7 @@ class NetForever : public NetProc {
void emit_recurse(struct target_t*) const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual bool emit_proc(struct target_t*) const;
virtual void dump(ostream&, unsigned ind) const;
@@ -2309,7 +2363,7 @@ class NetPDelay : public NetProc {
uint64_t delay() const;
const NetExpr*expr() const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void nex_output(NexusSet&);
virtual bool emit_proc(struct target_t*) const;
@@ -2335,7 +2389,7 @@ class NetRepeat : public NetProc {
const NetExpr*expr() const;
void emit_recurse(struct target_t*) const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual bool emit_proc(struct target_t*) const;
virtual void dump(ostream&, unsigned ind) const;
@@ -2381,7 +2435,7 @@ class NetSTask : public NetProc {
const NetExpr* parm(unsigned idx) const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void nex_output(NexusSet&);
virtual bool emit_proc(struct target_t*) const;
virtual void dump(ostream&, unsigned ind) const;
@@ -2438,7 +2492,7 @@ class NetTaskDef {
class NetEUFunc : public NetExpr {
public:
NetEUFunc(NetScope*, NetESignal*, svector<NetExpr*>&);
NetEUFunc(NetScope*, NetScope*, NetESignal*, svector<NetExpr*>&);
~NetEUFunc();
const NetESignal*result_sig() const;
@@ -2454,9 +2508,11 @@ class NetEUFunc : public NetExpr {
virtual void expr_scan(struct expr_scan_t*) const;
virtual NetEUFunc*dup_expr() const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual NetNet* synthesize(Design*des);
private:
NetScope*scope_;
NetScope*func_;
NetESignal*result_sig_;
svector<NetExpr*> parms_;
@@ -2481,7 +2537,7 @@ class NetUTask : public NetProc {
const NetScope* task() const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void nex_output(NexusSet&);
virtual bool emit_proc(struct target_t*) const;
virtual void dump(ostream&, unsigned ind) const;
@@ -2505,7 +2561,7 @@ class NetWhile : public NetProc {
void emit_proc_recurse(struct target_t*) const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void nex_output(NexusSet&);
virtual bool emit_proc(struct target_t*) const;
virtual void dump(ostream&, unsigned ind) const;
@@ -2576,8 +2632,8 @@ class NetProcTop : public LineInfo, public Attrib {
* p -- Arithmetic power (**)
* & -- Bit-wise AND
* | -- Bit-wise OR
* < -- Less then
* > -- Greater then
* < -- Less than
* > -- Greater than
* e -- Logical equality (==)
* E -- Case equality (===)
* L -- Less or equal
@@ -2612,7 +2668,7 @@ class NetEBinary : public NetExpr {
virtual bool has_width() const;
virtual NetEBinary* dup_expr() const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void expr_scan(struct expr_scan_t*) const;
virtual void dump(ostream&) const;
@@ -2622,7 +2678,6 @@ class NetEBinary : public NetExpr {
NetExpr* left_;
NetExpr* right_;
void eval_sub_tree_();
bool get_real_arguments_(verireal&lv, verireal&rv);
};
@@ -2636,7 +2691,7 @@ class NetEBinary : public NetExpr {
class NetEBAdd : public NetEBinary {
public:
NetEBAdd(char op, NetExpr*l, NetExpr*r);
NetEBAdd(char op, NetExpr*l, NetExpr*r, bool lossless_flag =false);
~NetEBAdd();
virtual ivl_variable_type_t expr_type() const;
@@ -2701,8 +2756,8 @@ class NetEBBits : public NetEBinary {
* this case the bit width of the expression is 1 bit, and the
* operands take their natural widths. The supported operators are:
*
* < -- Less then
* > -- Greater then
* < -- Less than
* > -- Greater than
* e -- Logical equality (==)
* E -- Case equality (===)
* L -- Less or equal (<=)
@@ -2727,10 +2782,12 @@ class NetEBComp : public NetEBinary {
virtual NetNet* synthesize(Design*);
private:
NetEConst* must_be_leeq_(NetExpr*le, const verinum&rv, bool eq_flag);
NetEConst*eval_eqeq_(bool ne_flag);
NetEConst*eval_less_();
NetEConst*eval_leeq_();
NetEConst*eval_leeq_real_();
NetEConst*eval_leeq_real_(NetExpr*le, NetExpr*ri, bool eq_flag);
NetEConst*eval_gt_();
NetEConst*eval_gteq_();
NetEConst*eval_eqeqeq_();
@@ -2782,7 +2839,7 @@ class NetEBMult : public NetEBinary {
};
/*
* Support the binary multiplication (*) operator.
* Support the binary power (**) operator.
*/
class NetEBPow : public NetEBinary {
@@ -2856,7 +2913,7 @@ class NetEConcat : public NetExpr {
unsigned nparms() const { return parms_.count() ; }
NetExpr* parm(unsigned idx) const { return parms_[idx]; }
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual bool has_width() const;
virtual bool set_width(unsigned w, bool last_chance =false);
virtual NetEConcat* dup_expr() const;
@@ -2888,7 +2945,7 @@ class NetEParam : public NetExpr {
NetEParam(class Design*des, NetScope*scope, perm_string name);
~NetEParam();
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual bool set_width(unsigned w, bool last_chance);
virtual bool has_width() const;
virtual void expr_scan(struct expr_scan_t*) const;
@@ -2927,7 +2984,7 @@ class NetESelect : public NetExpr {
const NetExpr*sub_expr() const;
const NetExpr*select() const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual bool set_width(unsigned w, bool last_chance =false);
virtual bool has_width() const;
virtual void expr_scan(struct expr_scan_t*) const;
@@ -2954,7 +3011,7 @@ class NetEEvent : public NetExpr {
virtual void expr_scan(struct expr_scan_t*) const;
virtual NetEEvent* dup_expr() const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void dump(ostream&os) const;
@@ -2977,7 +3034,7 @@ class NetEScope : public NetExpr {
virtual void expr_scan(struct expr_scan_t*) const;
virtual NetEScope* dup_expr() const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void dump(ostream&os) const;
@@ -3005,12 +3062,13 @@ class NetESFunc : public NetExpr {
const NetExpr* parm(unsigned idx) const;
virtual ivl_variable_type_t expr_type() const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual bool set_width(unsigned, bool last_chance);
virtual void dump(ostream&) const;
virtual void expr_scan(struct expr_scan_t*) const;
virtual NetESFunc*dup_expr() const;
virtual NetNet*synthesize(Design*);
private:
const char* name_;
@@ -3044,7 +3102,7 @@ class NetETernary : public NetExpr {
virtual NetExpr* eval_tree(int prune_to_width = -1);
virtual ivl_variable_type_t expr_type() const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void expr_scan(struct expr_scan_t*) const;
virtual void dump(ostream&) const;
virtual NetNet*synthesize(Design*);
@@ -3082,10 +3140,10 @@ class NetEUnary : public NetExpr {
virtual bool set_width(unsigned w, bool last_chance);
virtual NetEUnary* dup_expr() const;
virtual NetEConst* eval_tree(int prune_to_width = -1);
virtual NetExpr* eval_tree(int prune_to_width = -1);
virtual ivl_variable_type_t expr_type() const;
virtual NexusSet* nex_input();
virtual NexusSet* nex_input(bool rem_out = true);
virtual void expr_scan(struct expr_scan_t*) const;
virtual void dump(ostream&) const;
@@ -3093,7 +3151,8 @@ class NetEUnary : public NetExpr {
char op_;
NetExpr* expr_;
void eval_expr_();
private:
virtual NetExpr* eval_tree_real_();
};
class NetEUBits : public NetEUnary {
@@ -3104,7 +3163,7 @@ class NetEUBits : public NetEUnary {
virtual NetNet* synthesize(Design*);
virtual NetEConst* eval_tree(int prune_to_width = -1);
virtual NetExpr* eval_tree(int prune_to_width = -1);
virtual ivl_variable_type_t expr_type() const;
};
@@ -3143,7 +3202,7 @@ class NetESignal : public NetExpr {
virtual NetESignal* dup_expr() const;
NetNet* synthesize(Design*des);
NexusSet* nex_input();
NexusSet* nex_input(bool rem_out = true);
// This is the expression for selecting an array word, if this
// signal refers to an array.
@@ -3185,6 +3244,12 @@ class NetScope : public Attrib {
NetScope(NetScope*up, const hname_t&name, TYPE t);
~NetScope();
/* Rename the scope using the name generated by inserting as
many pad characters as required between prefix and suffix
to make the name unique in the parent scope. Return false
if a unique name couldn't be generated. */
bool auto_name(const char* prefix, char pad, const char* suffix);
/* Parameters exist within a scope, and these methods allow
one to manipulate the set. In these cases, the name is the
*simple* name of the parameter, the hierarchy is implicit in
@@ -3210,7 +3275,7 @@ class NetScope : public Attrib {
void add_event(NetEvent*);
void rem_event(NetEvent*);
NetEvent*find_event(const char*name);
NetEvent*find_event(perm_string name);
/* These methods manage signals. The add_ and rem_signal
@@ -3220,7 +3285,7 @@ class NetScope : public Attrib {
void add_signal(NetNet*);
void rem_signal(NetNet*);
NetNet* find_signal(const char*name);
NetNet* find_signal(perm_string name);
/* The parent and child() methods allow users of NetScope
objects to locate nearby scopes. */
@@ -3238,6 +3303,8 @@ class NetScope : public Attrib {
NetTaskDef* task_def();
NetFuncDef* func_def();
bool in_func();
const NetTaskDef* task_def() const;
const NetFuncDef* func_def() const;
@@ -3262,9 +3329,9 @@ class NetScope : public Attrib {
void default_nettype(NetNet::Type);
NetNet::Type default_nettype() const;
/* The name of the scope is the fully qualified hierarchical
name, whereas the basename is just my name within my parent
scope. */
/* The fullname of the scope is the hierarchical name
component (which includes the name and array index) whereas
the basename is just my name. */
perm_string basename() const;
const hname_t& fullname() const { return name_; }
@@ -3389,7 +3456,8 @@ class Design {
scope is located starting at the passed scope and working
up if needed. */
NetScope* find_scope(const std::list<hname_t>&path) const;
NetScope* find_scope(NetScope*, const std::list<hname_t>&path) const;
NetScope* find_scope(NetScope*, const std::list<hname_t>&path,
NetScope::TYPE type = NetScope::MODULE) const;
// PARAMETERS
@@ -3505,257 +3573,4 @@ inline __ScopePathManip scope_path(const NetScope*scope)
extern ostream& operator << (ostream&o, __ScopePathManip);
/*
* $Log: netlist.h,v $
* Revision 1.380 2007/06/02 03:42:13 steve
* Properly evaluate scope path expressions.
*
* Revision 1.379 2007/05/24 04:07:12 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.378 2007/04/26 03:06:22 steve
* Rework hname_t to use perm_strings.
*
* Revision 1.377 2007/04/17 04:34:23 steve
* Fix handling calls to tasks in combinational always block
*
* Revision 1.376 2007/04/07 04:46:18 steve
* Handle evaluate of addition of real valued constants.
*
* Revision 1.375 2007/04/02 01:12:34 steve
* Seperate arrayness from word count
*
* Revision 1.374 2007/03/26 18:17:50 steve
* Remove pretense of general use for t_cookie.
*
* Revision 1.373 2007/03/22 16:08:16 steve
* Spelling fixes from Larry
*
* Revision 1.372 2007/03/08 05:30:03 steve
* Limit the calculated widths of constants.
*
* Revision 1.371 2007/03/02 06:13:22 steve
* Add support for edge sensitive spec paths.
*
* Revision 1.370 2007/03/01 06:19:38 steve
* Add support for conditional specify delay paths.
*
* Revision 1.369 2007/02/20 05:58:36 steve
* Handle unary minus of real valued expressions.
*
* Revision 1.368 2007/02/14 05:59:46 steve
* Handle type of ternary expressions properly.
*
* Revision 1.367 2007/02/02 04:33:00 steve
* Use inttypes.h instead of stdint.h for portability.
*
* Revision 1.366 2007/01/16 05:44:15 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.365 2006/11/04 06:19:25 steve
* Remove last bits of relax_width methods, and use test_width
* to calculate the width of an r-value expression that may
* contain unsized numbers.
*
* Revision 1.364 2006/10/30 05:44:49 steve
* Expression widths with unsized literals are pseudo-infinite width.
*
* Revision 1.363 2006/10/03 05:06:00 steve
* Support real valued specify delays, properly scaled.
*
* Revision 1.362 2006/09/26 19:48:40 steve
* Missing PSpec.cc file.
*
* Revision 1.361 2006/09/23 04:57:19 steve
* Basic support for specify timing.
*
* Revision 1.360 2006/08/08 05:11:37 steve
* Handle 64bit delay constants.
*
* Revision 1.359 2006/07/31 03:50:17 steve
* Add support for power in constant expressions.
*
* Revision 1.358 2006/06/18 04:15:50 steve
* Add support for system functions in continuous assignments.
*
* Revision 1.357 2006/04/10 00:37:42 steve
* Add support for generate loops w/ wires and gates.
*
* Revision 1.356 2006/03/18 22:53:04 steve
* Properly handle signedness in compare.
*
* Revision 1.355 2006/02/02 02:43:58 steve
* Allow part selects of memory words in l-values.
*
* Revision 1.354 2006/01/02 05:33:19 steve
* Node delays can be more general expressions in structural contexts.
*
* Revision 1.353 2005/11/27 05:56:20 steve
* Handle bit select of parameter with ranges.
*
* Revision 1.352 2005/11/26 00:35:43 steve
* More precise about r-value width of constants.
*
* Revision 1.351 2005/09/19 21:45:36 steve
* Spelling patches from Larry.
*
* Revision 1.350 2005/09/14 02:53:14 steve
* Support bool expressions and compares handle them optimally.
*
* Revision 1.349 2005/09/01 04:11:37 steve
* Generate code to handle real valued muxes.
*
* Revision 1.348 2005/08/31 05:07:31 steve
* Handle memory references is continuous assignments.
*
* Revision 1.347 2005/07/14 23:34:19 steve
* gcc4 compile errors.
*
* Revision 1.346 2005/07/11 16:56:50 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.345 2005/07/07 16:22:49 steve
* Generalize signals to carry types.
*
* Revision 1.344 2005/05/24 01:44:28 steve
* Do sign extension of structuran nets.
*
* Revision 1.343 2005/05/17 20:56:55 steve
* Parameters cannot have their width changed.
*
* Revision 1.342 2005/05/08 23:44:08 steve
* Add support for variable part select.
*
* Revision 1.341 2005/04/24 23:44:02 steve
* Update DFF support to new data flow.
*
* Revision 1.340 2005/04/08 04:51:16 steve
* All memory addresses are signed.
*
* Revision 1.339 2005/04/06 05:29:08 steve
* Rework NetRamDq and IVL_LPM_RAM nodes.
*
* Revision 1.338 2005/03/18 02:56:03 steve
* Add support for LPM_UFUNC user defined functions.
*
* Revision 1.337 2005/03/12 06:43:36 steve
* Update support for LPM_MOD.
*
* Revision 1.336 2005/03/09 05:52:04 steve
* Handle case inequality in netlists.
*
* Revision 1.335 2005/02/19 02:43:38 steve
* Support shifts and divide.
*
* Revision 1.334 2005/02/12 06:25:40 steve
* Restructure NetMux devices to pass vectors.
* Generate NetMux devices from ternary expressions,
* Reduce NetMux devices to bufif when appropriate.
*
* Revision 1.333 2005/02/08 00:12:36 steve
* Add the NetRepeat node, and code generator support.
*
* Revision 1.332 2005/02/03 04:56:20 steve
* laborate reduction gates into LPM_RED_ nodes.
*
* Revision 1.331 2005/01/30 01:43:48 steve
* Clarify width argument to NetNet constructor.
*
* Revision 1.330 2005/01/28 05:39:33 steve
* Simplified NetMult and IVL_LPM_MULT.
*
* Revision 1.329 2005/01/24 05:28:31 steve
* Remove the NetEBitSel and combine all bit/part select
* behavior into the NetESelect node and IVL_EX_SELECT
* ivl_target expression type.
*
* Revision 1.328 2005/01/22 18:16:01 steve
* Remove obsolete NetSubnet class.
*
* Revision 1.327 2005/01/22 01:06:55 steve
* Change case compare from logic to an LPM node.
*
* Revision 1.326 2005/01/16 04:20:32 steve
* Implement LPM_COMPARE nodes as two-input vector functors.
*
* Revision 1.325 2005/01/12 03:17:37 steve
* Properly pad vector widths in pgassign.
*
* Revision 1.324 2005/01/09 20:16:01 steve
* Use PartSelect/PV and VP to handle part selects through ports.
*
* Revision 1.323 2004/12/29 23:55:43 steve
* Unify elaboration of l-values for all proceedural assignments,
* including assing, cassign and force.
*
* Generate NetConcat devices for gate outputs that feed into a
* vector results. Use this to hande gate arrays. Also let gate
* arrays handle vectors of gates when the outputs allow for it.
*
* Revision 1.322 2004/12/11 02:31:27 steve
* Rework of internals to carry vectors through nexus instead
* of single bits. Make the ivl, tgt-vvp and vvp initial changes
* down this path.
*
* Revision 1.321 2004/10/04 01:10:54 steve
* Clean up spurious trailing white space.
*
* Revision 1.320 2004/10/04 00:25:18 steve
* Remove inaccurate comment.
*
* Revision 1.319 2004/09/05 17:44:42 steve
* Add support for module instance arrays.
*
* Revision 1.318 2004/09/04 04:24:15 steve
* PR1026: assignment statements can have sensitivities in the l-values.
*
* Revision 1.317 2004/08/28 16:23:05 steve
* Fix use of system tasks in AT_STAR statements.
*
* Revision 1.316 2004/08/28 15:08:31 steve
* Do not change reg to wire in NetAssign_ unless synthesizing.
*
* Revision 1.315 2004/06/30 15:32:18 steve
* nex_output for NetPDelay statements.
*
* Revision 1.314 2004/06/30 02:16:26 steve
* Implement signed divide and signed right shift in nets.
*
* Revision 1.313 2004/06/13 04:56:55 steve
* Add support for the default_nettype directive.
*
* Revision 1.312 2004/05/31 23:34:38 steve
* Rewire/generalize parsing an elaboration of
* function return values to allow for better
* speed and more type support.
*
* Revision 1.311 2004/02/20 06:22:57 steve
* parameter keys are per_strings.
*
* Revision 1.310 2004/02/19 07:06:57 steve
* LPM, logic and Variables have perm_string names.
*
* Revision 1.309 2004/02/19 06:57:10 steve
* Memory and Event names use perm_string.
*
* Revision 1.308 2004/02/18 17:11:57 steve
* Use perm_strings for named langiage items.
*
* Revision 1.307 2003/12/17 16:52:39 steve
* Debug dumps for synth2.
*
* Revision 1.306 2003/11/10 20:59:03 steve
* Design::get_flag returns const char* instead of string.
*
* Revision 1.305 2003/11/08 20:06:21 steve
* Spelling fixes in comments.
*
* Revision 1.304 2003/10/31 02:47:11 steve
* NetEUReduce has its own dup_expr method.
*/
#endif
+106 -30
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2001-2003 Stephen Williams (steve@icarus.com)
* Copyright (c) 2001-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -16,12 +16,10 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: netmisc.cc,v 1.14 2007/06/02 03:42:13 steve Exp $"
#endif
# include "config.h"
# include <cstdlib>
# include "netlist.h"
# include "netmisc.h"
# include "PExpr.h"
@@ -73,7 +71,7 @@ NetNet* add_to_net(Design*des, NetNet*sig, long val)
return res;
#else
cerr << sig->get_line() << ": XXXX: Forgot how to implement add_to_net" << endl;
cerr << sig->get_fileline() << ": XXXX: Forgot how to implement add_to_net" << endl;
return 0;
#endif
}
@@ -129,17 +127,42 @@ NetExpr* elab_and_eval(Design*des, NetScope*scope,
const PExpr*pe, int expr_wid, int prune_width)
{
NetExpr*tmp = pe->elaborate_expr(des, scope, expr_wid, false);
if (tmp == 0)
return 0;
if (tmp == 0) return 0;
if (NetExpr*tmp2 = tmp->eval_tree(prune_width)) {
delete tmp;
tmp = tmp2;
}
eval_expr(tmp, prune_width);
return tmp;
}
void eval_expr(NetExpr*&expr, int prune_width)
{
assert(expr);
if (dynamic_cast<NetEConst*>(expr)) return;
if (dynamic_cast<NetECReal*>(expr)) return;
NetExpr*tmp = expr->eval_tree(prune_width);
if (tmp != 0) {
tmp->set_line(*expr);
delete expr;
expr = tmp;
}
}
bool eval_as_long(long&value, NetExpr*expr)
{
if (NetEConst*tmp = dynamic_cast<NetEConst*>(expr) ) {
value = tmp->value().as_long();
return true;
}
if (NetECReal*rtmp = dynamic_cast<NetECReal*>(expr)) {
value = rtmp->value().as_long();
return true;
}
return false;
}
std::list<hname_t> eval_scope_path(Design*des, NetScope*scope,
const pform_name_t&path)
{
@@ -165,6 +188,11 @@ std::list<hname_t> eval_scope_path(Design*des, NetScope*scope,
res.push_back(hname_t(comp.name, ctmp->value().as_long()));
delete ctmp;
continue;
} else {
cerr << index.msb->get_fileline() << ": error: "
<< "Scope index expression is not constant: "
<< *index.msb << endl;
des->errors += 1;
}
return res;
@@ -174,24 +202,72 @@ std::list<hname_t> eval_scope_path(Design*des, NetScope*scope,
}
/*
* $Log: netmisc.cc,v $
* Revision 1.14 2007/06/02 03:42:13 steve
* Properly evaluate scope path expressions.
*
* Revision 1.13 2007/03/08 05:30:03 steve
* Limit the calculated widths of constants.
*
* Revision 1.12 2006/06/02 04:48:50 steve
* Make elaborate_expr methods aware of the width that the context
* requires of it. In the process, fix sizing of the width of unary
* minus is context determined sizes.
*
* Revision 1.11 2005/04/08 04:50:31 steve
* Don not give to make_add express an unwanted width.
*
* Revision 1.10 2005/01/24 05:28:31 steve
* Remove the NetEBitSel and combine all bit/part select
* behavior into the NetESelect node and IVL_EX_SELECT
* ivl_target expression type.
* Human readable version of op. Used in elaboration error messages.
*/
const char *human_readable_op(const char op)
{
const char *type;
switch (op) {
case '~': type = "~"; break; // Negation
case '^': type = "^"; break; // XOR
case 'X': type = "~^"; break; // XNOR
case '&': type = "&"; break; // Bitwise AND
case 'A': type = "~&"; break; // NAND (~&)
case '|': type = "|"; break; // Bitwise OR
case 'O': type = "~|"; break; // NOR
case 'a': type = "&&"; break; // Logical AND
case 'o': type = "||"; break; // Logical OR
case 'E': type = "==="; break; // Case equality
case 'N': type = "!=="; break; // Case inequality
case 'l': type = "<<(<)"; break; // Left shifts
case 'r': type = ">>"; break; // Logical right shift
case 'R': type = ">>>"; break; // Arithmetic right shift
default: assert(0);
}
return type;
}
const_bool const_logical(const NetExpr*expr)
{
switch (expr->expr_type()) {
case IVL_VT_REAL: {
const NetECReal*val = dynamic_cast<const NetECReal*> (expr);
if (val == 0) return C_NON;
if (val->value().as_double() == 0.0) return C_0;
else return C_1;
}
case IVL_VT_BOOL:
case IVL_VT_LOGIC: {
const NetEConst*val = dynamic_cast<const NetEConst*> (expr);
if (val == 0) return C_NON;
verinum cval = val->value();
const_bool res = C_0;
for (unsigned idx = 0; idx < cval.len(); idx += 1) {
switch (cval.get(idx)) {
case verinum::V1:
res = C_1;
break;
case verinum::V0:
break;
default:
if (res == C_0) res = C_X;
break;
}
}
return res;
}
default:
break;
}
return C_NON;
}
+29 -91
View File
@@ -1,7 +1,7 @@
#ifndef __netmisc_H
#define __netmisc_H
/*
* Copyright (c) 1999-2000 Stephen Williams (steve@icarus.com)
* Copyright (c) 1999-2008 Stephen Williams (steve@icarus.com)
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
@@ -18,9 +18,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
#ifdef HAVE_CVS_IDENT
#ident "$Id: netmisc.h,v 1.31 2007/06/02 03:42:13 steve Exp $"
#endif
# include "netlist.h"
@@ -89,7 +86,7 @@ extern NetNet*add_to_net(Design*des, NetNet*sig, long val);
* make_add_expr
* Make a NetEBAdd expression with <expr> the first argument and
* <val> the second. This may get turned into a subtract if <val> is
* less then zero. If val is exactly zero, then return <expr> as is.
* less than zero. If val is exactly zero, then return <expr> as is.
*
* make_sub_expr
* Make a NetEBAdd(subtract) node that subtracts the given
@@ -122,96 +119,37 @@ class PExpr;
extern NetExpr* elab_and_eval(Design*des, NetScope*scope,
const PExpr*pe, int expr_wid,
int prune_width =-1);
/*
* This procedure elaborates an expression and if the elaboration is
* successful the original expression is replaced with the new one.
*/
void eval_expr(NetExpr*&expr, int prune_width =-1);
/*
* Get the long integer value for the passed in expression, if
* possible. If it is not possible (the expression is not evaluated
* down to a constant) then return false and leave value unchanged.
*/
bool eval_as_long(long&value, NetExpr*expr);
extern std::list<hname_t> eval_scope_path(Design*des, NetScope*scope,
const pform_name_t&path);
/*
* $Log: netmisc.h,v $
* Revision 1.31 2007/06/02 03:42:13 steve
* Properly evaluate scope path expressions.
*
* Revision 1.30 2007/05/24 04:07:12 steve
* Rework the heirarchical identifier parse syntax and pform
* to handle more general combinations of heirarch and bit selects.
*
* Revision 1.29 2007/03/08 05:30:03 steve
* Limit the calculated widths of constants.
*
* Revision 1.28 2007/02/26 19:49:49 steve
* Spelling fixes (larry doolittle)
*
* Revision 1.27 2007/01/16 05:44:15 steve
* Major rework of array handling. Memories are replaced with the
* more general concept of arrays. The NetMemory and NetEMemory
* classes are removed from the ivl core program, and the IVL_LPM_RAM
* lpm type is removed from the ivl_target API.
*
* Revision 1.26 2006/09/28 00:29:49 steve
* Allow specparams as constants in expressions.
*
* Revision 1.25 2006/06/02 04:48:50 steve
* Make elaborate_expr methods aware of the width that the context
* requires of it. In the process, fix sizing of the width of unary
* minus is context determined sizes.
*
* Revision 1.24 2005/11/27 05:56:20 steve
* Handle bit select of parameter with ranges.
*
* Revision 1.23 2005/07/11 16:56:51 steve
* Remove NetVariable and ivl_variable_t structures.
*
* Revision 1.22 2005/05/24 01:44:28 steve
* Do sign extension of structuran nets.
*
* Revision 1.21 2005/04/24 23:44:02 steve
* Update DFF support to new data flow.
*
* Revision 1.20 2005/01/24 05:28:31 steve
* Remove the NetEBitSel and combine all bit/part select
* behavior into the NetESelect node and IVL_EX_SELECT
* ivl_target expression type.
*
* Revision 1.19 2004/03/07 20:04:11 steve
* MOre thorough use of elab_and_eval function.
*
* Revision 1.18 2003/09/19 03:30:05 steve
* Fix name search in elab_lval.
*
* Revision 1.17 2003/01/30 16:23:08 steve
* Spelling fixes.
*
* Revision 1.16 2002/08/31 03:48:50 steve
* Fix reverse bit ordered bit select in continuous assignment.
*
* Revision 1.15 2002/08/12 01:35:00 steve
* conditional ident string using autoconfig.
*
* Revision 1.14 2002/06/25 01:33:22 steve
* Cache calculated driven value.
*
* Revision 1.13 2002/06/24 01:49:39 steve
* Make link_drive_constant cache its results in
* the Nexus, to improve cprop performance.
*
* Revision 1.12 2001/02/15 06:59:36 steve
* FreeBSD port has a maintainer now.
*
* Revision 1.11 2001/02/10 20:29:39 steve
* In the context of range declarations, use elab_and_eval instead
* of the less robust eval_const methods.
*
* Revision 1.10 2000/11/20 00:58:40 steve
* Add support for supply nets (PR#17)
*
* Revision 1.9 2000/09/20 02:53:15 steve
* Correctly measure comples l-values of assignments.
*
* Revision 1.8 2000/06/25 19:59:42 steve
* Redesign Links to include the Nexus class that
* carries properties of the connected set of links.
*
* Revision 1.7 2000/05/14 17:55:04 steve
* Support initialization of FF Q value.
* Return a human readable version of the operator.
*/
const char *human_readable_op(const char op);
/*
* Is the expression a constant value and if so what is its logical
* value.
*
* C_NON - the expression is not a constant value.
* C_0 - the expression is constant and it has a false value.
* C_1 - the expression is constant and it has a true value.
* C_X - the expression is constant and it has an 'bX value.
*/
enum const_bool { C_NON, C_0, C_1, C_X };
const_bool const_logical(const NetExpr*expr);
#endif
+2 -12
View File
@@ -25,6 +25,7 @@
# include "netlist.h"
# include "netmisc.h"
/*
* This function transforms an expression by padding the high bits
* with V0 until the expression has the desired width. This may mean
@@ -39,18 +40,7 @@ NetExpr*pad_to_width(NetExpr*expr, unsigned wid)
/* If the expression is a const, then replace it with a wider
const. This is a more efficient result. */
if (NetEConst*tmp = dynamic_cast<NetEConst*>(expr)) {
verinum eval = tmp->value();
bool signed_flag = eval.has_sign();
verinum::V pad = verinum::V0;
if (signed_flag)
pad = eval.get(eval.len()-1);
verinum oval (pad, wid, eval.has_len());
for (unsigned idx = 0 ; idx < eval.len() ; idx += 1)
oval.set(idx, eval.get(idx));
oval.has_sign(signed_flag);
verinum oval = pad_to_width(tmp->value(), wid);
tmp = new NetEConst(oval);
delete expr;
return tmp;
+644 -558
View File
File diff suppressed because it is too large Load Diff
+1 -1
View File
@@ -33,7 +33,7 @@ class PUdp;
/*
* These are maps of the modules and primitives parsed from the
* Verilog source into pform for elaboration. The parser adds modules
* to these maps as it compiles modules in the verilog source.
* to these maps as it compiles modules in the Verilog source.
*/
extern map<perm_string,Module*> pform_modules;
extern map<perm_string,PUdp*> pform_primitives;
+2 -30
View File
@@ -28,6 +28,7 @@
extern const char*vl_file;
unsigned error_count = 0;
unsigned warn_count = 0;
unsigned long based_size = 0;
void VLerror(const char*msg)
{
@@ -42,6 +43,7 @@ void VLerror(const YYLTYPE&loc, const char*msg)
cerr << loc.text << ":";
cerr << loc.first_line << ": " << msg << endl;
based_size = 0; /* Clear the base information if we have an error. */
}
void yywarn(const YYLTYPE&loc, const char*msg)
@@ -58,33 +60,3 @@ int VLwrap()
return -1;
}
/*
* $Log: parse_misc.cc,v $
* Revision 1.7 2002/08/12 01:35:00 steve
* conditional ident string using autoconfig.
*
* Revision 1.6 2002/06/06 18:57:18 steve
* Use standard name for iostream.
*
* Revision 1.5 2001/07/25 03:10:49 steve
* Create a config.h.in file to hold all the config
* junk, and support gcc 3.0. (Stephan Boettcher)
*
* Revision 1.4 2000/02/23 02:56:55 steve
* Macintosh compilers do not support ident.
*
* Revision 1.3 1999/09/29 21:15:31 steve
* Standardize formatting of warning messages.
*
* Revision 1.2 1998/11/07 17:05:05 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:29:02 steve
* Introduce verilog to CVS.
*
*/
+1 -28
View File
@@ -55,33 +55,6 @@ extern void VLerror(const YYLTYPE&loc, const char*msg);
extern void VLwarn(const YYLTYPE&loc, const char*msg);
extern unsigned error_count, warn_count;
extern unsigned long based_size;
/*
* $Log: parse_misc.h,v $
* Revision 1.7 2003/03/08 20:58:18 steve
* More C-like use of vlltype.
*
* Revision 1.6 2002/11/03 20:36:53 steve
* Support old/new bison yylloc.
*
* Revision 1.5 2002/08/12 01:35:00 steve
* conditional ident string using autoconfig.
*
* Revision 1.4 2000/02/23 02:56:55 steve
* Macintosh compilers do not support ident.
*
* Revision 1.3 1999/07/10 01:03:18 steve
* remove string from lexical phase.
*
* Revision 1.2 1998/11/07 17:05:05 steve
* Handle procedural conditional, and some
* of the conditional expressions.
*
* Elaborate signals and identifiers differently,
* allowing the netlist to hold signal information.
*
* Revision 1.1 1998/11/03 23:29:03 steve
* Introduce verilog to CVS.
*
*/
#endif
+329 -468
View File
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