9448c5939c
Always user Ternary_* support functions for ternary assignments
...
Previously the code generator expanded ternary assignments to
and `if' statement. This patch replaces that with a single assignment
and a call to a Ternary_* support function. This will make it
much easier to support multiple lvals later.
2008-08-02 15:46:36 +01:00
8b32096e2a
Convert std_logic to Boolean in loop tests
2008-07-27 18:39:16 +01:00
39c9c54760
Add repeat statement
2008-07-24 14:52:06 +01:00
8bee5b1108
Add `forever' statement type
2008-07-24 14:30:10 +01:00
e4c2400eb2
Refactor the expression->time code into a single function
2008-07-23 16:18:49 +01:00
7b311b6adb
Translate internal delays in assignments
2008-07-18 14:47:35 +01:00
e9637f6d11
Generate synthesisable code for sequential processes
...
Whilst adding `wait until ...' at the end of every
process is a valid translation of the input, it is not
actually synthesisable in at least one commercial
synthesiser (XST). According to the XST manual the
correct template is to use `wait until ...' at the
start of sequential processes and `wait on ...'
(equivalent to `wait until ...' with 'Event on all
the signals) at the end of combinatorial processes.
This patch implements that.
2008-07-17 17:36:42 +01:00
1f9ed2c5ec
VHDL AST element for `wait on' statement
2008-07-17 17:23:21 +01:00
2a791bfb38
Assignment to arrays
2008-07-17 13:41:44 +01:00
be67cae29f
Add translation for IVL_ST_CASEX
2008-07-16 16:42:44 +01:00
4504c2bceb
Fix initialisation order bug with `if' statements
...
If an assignment appears inside an if statement branch
it could be incorrectly used as the signal's initial
value.
2008-07-16 12:11:00 +01:00
b5e12077b2
Fix assignment to lval slice
...
It was broken in yeserday's refactoring
2008-07-15 18:40:30 +01:00
a9c98ad5f2
Handle `if' with empty cond_true part
...
Fixes assertion failure with following statement:
if (foo)
begin
end
else
...
2008-07-15 14:26:19 +01:00
b8e758edf0
Refactor LPM code
2008-07-15 14:09:24 +01:00
0b48f69b4e
Tidy up blocking assignment code
2008-07-15 10:44:48 +01:00
d1e7e325b7
Remove redundant edge_detector function
2008-07-14 21:34:48 +01:00
75b1db0add
Fix assignment with ternary RHS
...
This was also broken in the last commit
2008-07-14 21:27:21 +01:00
6e965523a1
Fix PV assignment (was broken in last commit)
2008-07-14 21:09:19 +01:00
8589c0691b
Refactor assignment code
2008-07-14 21:04:09 +01:00
99ef8ec4f1
Simplify edge detector code
...
Now generates a `wait until' statement rather than a
sensitivity list.
2008-07-14 20:29:49 +01:00
d22c9a8b05
Simplify blocking assignment
...
Now generates 'wait for 0 ns' after non-blocking assignment
2008-07-14 19:54:45 +01:00
4777966b4c
Bit select bug fixes
2008-07-07 21:19:59 +01:00
0348664512
Correctly determine VHDL type of LHS of part select
2008-07-07 16:35:39 +01:00
b0de1a8d7e
Implement part select for LHS of assignment
2008-07-07 16:11:45 +01:00
bdf5ee7ab7
Concat LPM
2008-07-07 14:48:57 +01:00
ebaa4c7d5d
Implement assignment to part select properly
...
Previously the base of the lval was ignored, this ensures
the correct assignment is generated.
2008-07-07 11:00:27 +01:00
85d2cc78d6
Finish ternary operator expansion
2008-07-06 17:56:48 +01:00
18071562ba
Partially implement ternary expressions
...
This handles the case where the expression appears as the
right hand side of an assignment. The expression is converted
into a regular if statement.
2008-07-04 21:55:51 +01:00
5aeff6d47d
Merge blocking and non-blocking assignment code
2008-07-04 20:07:38 +01:00
19871efd5a
Fix bug where sensitivity might reference undefined signals
2008-07-04 11:58:33 +01:00
409fc4dc19
Check if case expression variable is already defined
...
Verilog_Case_Ex is used as a temporary to store the result of
any non-static case expression. This fixes a bug where it would
be declared multiple times if there were multiple case statements
in a block.
2008-07-04 11:15:34 +01:00
c54b36c902
Add logical AND operator
2008-07-04 11:10:20 +01:00
19cbab78b2
Tidy up code to generate default branch of case
2008-07-03 20:04:47 +01:00
1736cd9bc8
Fix uneccessarily complicated generated case statement
...
No need to generate separate case test variable if the
test in the VL source is a simple variable reference.
2008-07-03 16:27:36 +01:00
a5264e9995
Make sure all choices are covered in case statement
2008-07-03 16:17:56 +01:00
6868127ba3
Make sure case expression has the correct type
2008-07-03 16:14:17 +01:00
dbbadbc309
Make sure the renamed signal is used in the sensitivity list
2008-07-03 16:13:02 +01:00
500442e5c5
Working function calls
2008-06-25 22:15:57 +01:00
899a70908e
Fix small bug with initialisation and ammend comments
2008-06-24 20:13:18 +01:00
bf95d77562
Finish replacing vhdl_process with vhdl_procedural
2008-06-24 20:01:06 +01:00
75631bd8f1
Move is_inital code out of vhdl_process into vhdl_scope
...
Part of tidy up before implementing functions
2008-06-24 19:06:06 +01:00
63b1887ff2
Refactor code to use the new vhdl_scope class
2008-06-24 18:52:25 +01:00
4188fbecee
Add XOR operator and catch default case branch
2008-06-24 10:55:45 +01:00
f261bf7e97
Fix bug where variables could be declared twice
2008-06-23 15:13:10 +01:00
f81129aa68
Fix some bugs with blocking assignment
2008-06-23 13:36:28 +01:00
469036990a
Output blocking assignments in the right place
2008-06-23 12:30:48 +01:00
d5cdb91d55
Handle complex expressions in case statement
2008-06-23 11:36:12 +01:00
75f7c9ae0c
Only move constant assignments into initialisation
2008-06-21 16:40:18 +01:00
5cfe7ea0aa
Tidy up output
2008-06-21 16:28:07 +01:00
ec23b70bb7
While loops
2008-06-21 15:13:44 +01:00
0caf4fd9d0
Add case statement
2008-06-21 15:03:36 +01:00
204862ac3c
Implement $write
2008-06-20 19:00:07 +01:00
404c22ac86
Improved implementation of $display
2008-06-20 11:51:13 +01:00
d7bb5658f2
Translate IVL_ST_DELAYX statements
2008-06-19 12:16:19 +01:00
e0f41198d6
Blocking assignment working correctly
2008-06-18 13:49:03 +01:00
fb31a88c51
Blocking assignment nearly working
2008-06-18 13:30:19 +01:00
254ccb9ccb
First passing at blocking assignment
2008-06-18 13:06:27 +01:00
d2bebee9d9
Refactor before adding blocking assignment
2008-06-18 12:51:11 +01:00
af8c08e6a7
Allow optional VHPI $finish implementation
2008-06-17 20:16:16 +01:00
01249000c3
Temporarily treat blocking assignment as non-blocking
2008-06-17 14:07:36 +01:00
1debbc3100
Simplify edge_detector() a bit
2008-06-16 20:06:06 +01:00
92c823680a
Fix crash when `if' statement had no `else'
2008-06-16 12:13:01 +01:00
0ea64ad8ab
Correct misleading comment
2008-06-13 14:47:06 +01:00
be3c4cf268
Generate signal initial values from `initial' processes
2008-06-13 14:10:28 +01:00
0a8fd50c4a
Find assignments that could be initializers
2008-06-13 13:59:48 +01:00
70db096b6d
Clean up the edge detector code a bit
2008-06-13 12:52:20 +01:00
005df31a0d
Use renamed signal in expressions, if there is one
2008-06-13 12:39:18 +01:00
8fe2211e2b
Generate `after' modifier instead of `wait' statements
2008-06-12 11:24:43 +01:00
46991aa65c
Generate process bodies in the right place
2008-06-12 10:47:52 +01:00
7eb41304e6
Generate rising/falling edge detectors
2008-06-12 10:36:38 +01:00
19e60b698f
Translate if statements
2008-06-11 14:20:05 +01:00
a7cfdc3a87
Add VHDL if statement to AST types
2008-06-11 14:11:37 +01:00
b010b8e3ca
Use `assert false' as initial translation of $finish
2008-06-11 13:37:21 +01:00
7560b29fb9
Find signals to map together
2008-06-10 12:21:48 +01:00
191187ed1b
Cosmetic change to avoid useless `null' statement after delay
2008-06-09 16:40:32 +01:00
2f5dcda3b6
Delay statements now translated correctly
2008-06-09 12:49:38 +01:00
d762253f74
Wait statements
2008-06-09 12:40:59 +01:00
110a1b2ac7
Replace type classes with enumeration
2008-06-08 12:48:56 +01:00
79558910d1
Catch case where NULL return wasn't detected
2008-06-07 16:44:01 +01:00
fbf85398da
Support converting bit strings to std_logic
2008-06-07 16:19:10 +01:00
1e4b96aa0a
Simplify code a bit as rval type is never needed
2008-06-07 14:57:20 +01:00
c064ae6bc3
Generate VHDL for non-blocking assignments
2008-06-07 14:54:00 +01:00
39228f3495
VHDL AST element for non-blocking assignment
2008-06-07 14:31:33 +01:00
12e2237131
Add Type'Image cast to $display parameters
2008-06-07 14:21:50 +01:00
cdb180e1d4
Associate a type with each VHDL expression node
2008-06-07 13:23:21 +01:00
8c3461f0ff
Generate sensitivity lists properly and add signal declarations
2008-06-07 11:48:38 +01:00
305f448d05
Generate code for signal references
2008-06-07 11:24:09 +01:00
5f90a3e48c
Translate sub-statement of @{..}
2008-06-06 18:22:03 +01:00
96cf190720
Generate signals and sensitivity list for @(..) statement
2008-06-06 17:56:52 +01:00
373832ba22
Specify correct sensitivity list
2008-06-06 17:36:15 +01:00
4f472e451e
Stubs for statement types in mux2.v test
2008-06-06 16:55:45 +01:00
d36bbec5b5
Generate VHDL for no-op statements
2008-06-05 13:16:35 +01:00
e258058cf1
Fully qualify std.textio.Output to avoid name collisions
2008-06-04 21:58:51 +01:00
c3ac1aac8c
Remove debugging messages from output
2008-06-04 21:07:50 +01:00
f49dd97d24
Add support for blocks and make hello1.v test pass
2008-06-04 20:57:15 +01:00
7bd1565cfb
$display now (mostly) working
2008-06-04 20:42:44 +01:00
6e448da90d
Emit Write() calls for parameters of $display
2008-06-04 15:19:44 +01:00
4bf2e1669d
Store packages required with entity rather than globally
...
Add parent link to architecture and process so code generators can push things higher up
$display now prints blank lines
2008-06-04 13:52:56 +01:00
dd30c1b39d
Support procedure call generation for $display
2008-06-04 13:27:42 +01:00
94006cb44c
Working on code generation for $display task
2008-06-03 19:46:10 +01:00
Nick Gasson