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OpenRAM
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196 Commits

Author SHA1 Message Date
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
mrg fc12ea24e9 Add boundary to every module and pgate for visual debug. 2019-06-03 15:27:37 -07:00
Hunter Nichols d8617acff2 Merged with dev 2019-05-15 18:48:00 -07:00
Hunter Nichols d54074d68e Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based. 2019-05-07 00:52:27 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 0439b129bb Some pgates are designs since not a fixed height 2019-04-26 12:33:53 -07:00
Matt Guthaus 05ad4285af Cleanup pgate code. 
Moved create_netlist and create_layout to the pgate class
from which everything is derived. Modified all pgates
to have consistent debug output and order of init function.
 2019-04-26 12:30:42 -07:00
Hunter Nichols e292767166 Added graph creation and functions in base class and lower level modules. 2019-04-24 14:23:22 -07:00
Hunter Nichols 4f28295e20 Added initial graph for correct naming 2019-04-19 01:27:06 -07:00
Matt Guthaus 25bc3a66ed Add far left option for contact placement in pgates. 2019-04-17 13:41:35 -07:00
Matt Guthaus be20408fb2 Rewrite add_contact to use layer directions. 2019-04-15 18:00:36 -07:00
Hunter Nichols 25c034f85d Added more accurate bitline delay capacitance estimations 2019-04-09 01:56:32 -07:00
Hunter Nichols 1438519495 Added check to pdriver for 0 fanout which can break compute_sizes. 2019-04-03 17:53:28 -07:00
Hunter Nichols f6eefc1728 Added updated analytical characterization with combined models 2019-04-02 01:09:31 -07:00
Hunter Nichols 97777475b4 Added additions to account for custom delay chains. 2019-03-28 17:16:23 -07:00
Hunter Nichols 80a325fe32 Added corner information for analytical power estimation. 2019-03-04 19:27:53 -08:00
Hunter Nichols 0e96648211 Added linear corner factors in analytical delay model. 2019-03-04 00:42:18 -08:00
Hunter Nichols 5f01a52113 Fixed some delay model bugs. 2019-02-05 21:15:12 -08:00
Hunter Nichols d1218778b1 Fixed merge conflicts 2019-01-28 22:33:08 -08:00
Matt Guthaus 18805423e3 Simplify pdriver code. 2019-01-25 17:18:12 -08:00
Matt Guthaus beceb3fb60 Fix buggy analytical delay in pdriver 2019-01-25 16:22:59 -08:00
Matt Guthaus 09d6a63861 Change path to wire_path for Anaconda package conflict 2019-01-25 15:07:56 -08:00
Matt Guthaus 6f32bac1a2 Use rx of last pdriver instance after placing instances 2019-01-25 14:17:37 -08:00
Matt Guthaus 614aa54f17 Move clkbuf output lower to avoid dff outputs 2019-01-25 14:03:52 -08:00
Matt Guthaus ddf734891a Fix pdriver width error 2019-01-25 10:26:31 -08:00
Matt Guthaus 091b4e4c62 Add size commments to spize. Change pdriver stage effort. 2019-01-23 17:27:15 -08:00
Matt Guthaus b58fd03083 Change pbuf/pinv to pdriver in control logic. 2019-01-23 12:03:52 -08:00
Matt Guthaus 91636be642 Convert all contacts to use the sram_factory 2019-01-16 16:56:06 -08:00
Matt Guthaus 5192a01f2d Convert pgates to use ptx through the factory 2019-01-16 16:30:31 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Hunter Nichols 6152ec7ec5 Merge branch 'dev' into multiport_characterization 2019-01-15 16:33:39 -08:00
Hunter Nichols 8eb4812e16 Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model. 2018-12-17 23:32:02 -08:00
Jennifer Eve Sowash 4a5c18b6cc Removed line to skip pdriver_test 2018-12-13 19:10:38 -08:00
Jennifer Eve Sowash bc44c80d40 Added height to init in pdriver.py 2018-12-13 19:03:31 -08:00
Hunter Nichols 0510aeb3ec Merged with dev, removed commented out code. 2018-12-12 16:02:16 -08:00
Jennifer Eve Sowash a51aacfa90 Added corner case for 1 inv pos polarity and renamed variables. 2018-12-07 19:42:11 -08:00
Jennifer Eve Sowash a6eec10f41 Passed freepdk45 tests with pdriver.py 2018-12-07 12:58:05 -08:00
Jennifer Eve Sowash a24e5229cb Fixed method of determining inverter number. 2018-12-07 10:19:18 -08:00
Jennifer Eve Sowash 653ab3eda4 Changed method of determining number of inverters. 2018-12-06 19:34:19 -08:00
Jennifer Eve Sowash 8ea85e3e65 Merge branch 'dev' into pdriver 2018-12-06 14:38:08 -08:00
Jennifer Eve Sowash 5e19cf1e24 Updated naming, added compute_sizes(), and fixed sizing function. 2018-12-06 14:36:01 -08:00
Hunter Nichols ea55bda493 Changed s_en delay calculation based recent control logic changes. 2018-12-05 17:10:11 -08:00
Jennifer Eve Sowash 2534a32e20 pdriver.py passes resgression tests. Size and number of inverters has been added. 2018-12-03 12:55:48 -08:00
Jennifer Sowash 887674aa85 Added pdriver.py for testing. 2018-12-03 09:11:12 -08:00
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
Matt Guthaus 2ed8fc1506 pgate inputs and outputs are all on M1 for flexible via placement when using gates. 2018-11-28 12:42:29 -08:00
Matt Guthaus d2ca2efdbe Limit ps, pd, as, ad precision in ptx. 2018-11-28 09:47:54 -08:00
Matt Guthaus c45f990413 Change en to en_bar in precharge. Fix logic for inverted p_en_bar. 2018-11-27 14:17:55 -08:00
Matt Guthaus 9e0b31d685 Make pand2 and pbuf derive pgate. Initial DRC wrong layout. 2018-11-26 16:19:18 -08:00
Matt Guthaus b440031855 Add netlist only mode to new pgates 2018-11-26 15:29:42 -08:00
Matt Guthaus 2eff166527 Rotate vias in pand2 2018-11-26 14:05:04 -08:00
Matt Guthaus 5209619987 Move pnand2 output to allow input pin access on M2 2018-11-26 13:59:53 -08:00
Matt Guthaus 8fba32ca12 Add pand2 draft 2018-11-26 13:45:22 -08:00
Jennifer Eve Sowash bb7773ca7f Editted pbuf.py to pass regression. 2018-11-20 14:39:11 -08:00
Hunter Nichols 6e47de3f9b Separated relative delay into rise/fall. 2018-11-14 23:34:53 -08:00
Jennifer Sowash b6f1409fb9 Testing to ensure branch is up to date with dev. Added 04_pbuf_test.py and made changes to pbuf.py to align with comments. 2018-11-12 13:24:27 -08:00
Jennifer Sowash b366d88041 Merge branch 'dev' into pdriver 2018-11-12 11:30:37 -08:00
Jennifer Sowash 82abd32785 Added pbuf.py to create a single buffer. 2018-11-12 09:53:21 -08:00
Hunter Nichols bad55cfd05 Merged with dev. Fixed merge conflict. 2018-11-09 17:18:19 -08:00
Matt Guthaus c01effc819 Adjust ptx positions in precharge to be under the bl rail 2018-11-09 10:26:15 -08:00
Matt Guthaus ac7229f8d3 Move vdd pin in precharge inside cell 2018-11-09 10:11:24 -08:00
Matt Guthaus 21f5fb0870 precharge bl is on metal2 only. simplify via position code. 2018-11-09 09:11:00 -08:00
Hunter Nichols 8957c556db Added sense amp enable delay calculation. 2018-11-08 23:54:18 -08:00
Hunter Nichols b8061d3a4e Added initial code for determining the logical effort delay of the wordline. 2018-11-08 23:54:18 -08:00
Matt Guthaus 31eff6f24e Merge branch 'dev' into multiport_layout 2018-11-08 18:00:28 -08:00
Matt Guthaus 5dfba21acc Change tx mux size back to 8. Document why it was chosen. 2018-11-07 16:03:48 -08:00
Matt Guthaus 3d2abc0873 Change default col mux size to 2. Add some comments. 2018-11-07 15:43:08 -08:00
Matt Guthaus ad7fe1be51 Clean up code formatting. 2018-11-07 14:52:03 -08:00
Matt Guthaus 4e232c49ad Update precharge cell for multiport. 
Comment out pbitcell tests.
Add bitcell_1rw_1r test.
Move bitcell horizontal routing to metal1.
Extend precharge height for stacking.
 2018-11-07 14:46:51 -08:00
Michael Timothy Grimes 6711630463 Altering the routing slightly in the column mux to give the gnd contacts a wider berth. This prevents drc errors when the bitlines are close to the edge of the cell. 2018-11-02 05:59:47 -07:00
Matt Guthaus 4bf1e206e2 Merge branch 'dev' into supply_routing 2018-10-17 09:47:18 -07:00
Michael Timothy Grimes e60deddfea adding 6T transistor size parameters to tech files for use in pbitcell. 2018-10-17 07:28:56 -07:00
Michael Timothy Grimes 69a1560186 Changing the location of the vdd contact in precharge to avoid drc errors when the bitlines are close to the edge of the cell. Correcting replica bitcell function in pbitcell. 2018-10-16 06:57:53 -07:00
Michael Timothy Grimes c8c70401ae Redesign of pbitcell for newer process technolgies. 2018-10-15 06:29:51 -07:00
Matt Guthaus ce8c2d983d Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
Matt Guthaus 4932d83afc Add design rules classes for complex design rules 2018-10-12 09:44:36 -07:00
Matt Guthaus e22e658090 Converted all submodules to use _bit notation instead of [bit] 2018-10-11 09:53:08 -07:00
Matt Guthaus a2b1d025ab Merge multiport 2018-10-08 11:45:50 -07:00
Matt Guthaus 3244e01ca1 Add copy power pin function 2018-10-08 09:56:39 -07:00
Matt Guthaus 280488b3ad Add M3 supply to pinvbuf 2018-10-08 09:24:16 -07:00
Matt Guthaus 68b30d601e Move bitcells to their own directory in preparation for custom multiport cells. 2018-10-05 08:09:09 -07:00
Michael Timothy Grimes 5fd484ee5a Replacing replica_pbitcell module with a more effiecient verision. replica_pbitcell is now a wrapper for pbitcell in replica_bitcell mode. 2018-09-13 16:53:24 -07:00
Michael Timothy Grimes e0b9989d85 Adding replica_pbitcell and test for multi-ported purposes. Altering replica bitline and test to accomodate. 2018-09-13 01:42:06 -07:00
Michael Timothy Grimes 42719b8ec2 Fixing netlist_only errors. Removing netlist_only option from ptx because it must always generate layout for pbitcell. gds_write, drc check, and lvs check in local_check() are now in a 'if not OPTS.netlist_only' conditional. These functions will generate errors in netlist_only mode since there is no gds layout to write or check. 2018-09-12 01:53:41 -07:00
Michael Timothy Grimes bfc855b8b1 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-11 17:33:17 -07:00
Hunter Nichols 5dfa8bc2c6 Fixed known typos of the word transition. 2018-09-10 14:27:26 -07:00
Michael Timothy Grimes 27427d4192 Bank level layout now works with pbitcell and 1RW. Column mux and array have been altered to accomodate multiport. Multiport changes to wordline driver were removed because they were unnecessary. 2018-09-09 22:06:29 -07:00
Michael Timothy Grimes c91735b23b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-08 18:56:58 -07:00
Michael Timothy Grimes 1a340c9c85 Merging latest changes from multiport with changes made to pbitcell. Changing select code from other modules and tests to reflect changes made to pbitcell. 2018-09-06 19:36:50 -07:00
Michael Timothy Grimes 66a8a76fb0 Commiting changes to pbitcell that separate the routing into individual functions and rename. The bitlines and wordlines are also renamed. 2018-09-06 17:59:21 -07:00
Matt Guthaus 378993ca22 Found rotate bug in transformCoordinate. Cleaned up transFlags. 2018-09-04 16:35:40 -07:00
Matt Guthaus 6963a1092f Make bitcell width/height not static. Update modules to use it for pbitcell. 2018-09-04 11:55:22 -07:00
Matt Guthaus a346bddd88 Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
Matt Guthaus 563ff77d44 Add sram_config class. Rename port variables for better description. 2018-08-31 12:03:28 -07:00
Michael Timothy Grimes 29da8a5209 Further changes to pbitcell so that it passes unit tests for bitcell_array 2018-08-29 15:54:49 -07:00
Michael Timothy Grimes 807a4d7767 Fixed drcs error in magic. Pbitcell should now pass unit tests in calibre and magic. 2018-08-29 15:30:50 -07:00
Michael Timothy Grimes 1d5a41df2d fixed issue with read ports that caused extra transistors to appear 2018-08-29 08:52:45 -07:00
Matt Guthaus e17c69be3e Clean up new code for add_modules, add_pins and netlist/layouts. 2018-08-28 10:24:09 -07:00
Matt Guthaus 6401cbf2a6 Move place function to instance class rather than hierarchy. 2018-08-27 17:25:39 -07:00