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OpenRAM
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626 Commits

Author SHA1 Message Date
Bugra Onal fcfb9391f6 Code formatting 2022-09-01 16:19:14 -07:00
Bugra Onal d3753556c1 Pin generation instead of parsing 2022-08-18 21:09:48 -07:00
Bugra Onal eceb35f205 Skip graph exclusions on memchar 2022-08-18 20:38:09 -07:00
Bugra Onal efd6da5300 Parse pins from HTML 2022-08-18 12:54:39 -07:00
Bugra Onal f602c6b263 HTML parsing for fake_sram added 2022-08-12 23:29:33 -07:00
Bugra Onal aefe46394c Merge branch 'dev' into multibank 2022-08-12 21:45:26 -07:00
Bugra Onal dc1626879e Characterizer wmask check for write_size 2022-08-10 16:11:19 -07:00
Bugra Onal bd6621cb88 Increase random value range by 1 2022-08-10 14:21:54 -07:00
Bugra Onal 3f941d2fff Copy over the CSV read function to fake_sram 2022-08-10 12:59:54 -07:00
Bugra Onal c7975e3274 Use fake sram in memchar 2022-08-10 12:22:47 -07:00
Bugra Onal 219b29a833 Fake SRAM and Xyce RAW file option 2022-08-10 12:22:47 -07:00
samuelkcrow 8793dda40a characterizer and functional simulator working from command line 2022-08-10 12:06:18 -07:00
Bugra Onal 8f955207d3 Fixed write_size checks for characterizer 2022-07-28 16:47:29 -07:00
Bugra Onal 30f5638b9f Replaced instances of addr_size with bank_addr 2022-07-28 15:03:41 -07:00
Eren Dogan 03422be48c Fix carriage return 2022-07-22 19:54:35 +03:00
Eren Dogan e3fe8c3229 Remove line ending whitespace 2022-07-22 19:52:38 +03:00
samuelkcrow 1d0741baa4 temporariliy commenting out path code that's making simulation fail. 2022-07-21 19:35:01 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
samuelkcrow dfbf0ba6e1 Make git dependency visible and enforce it. 
resolves #87
 2021-10-04 14:43:14 -07:00
Hunter Nichols 39ae1270d7 Merge branch 'dev' into cacti_model 2021-09-20 17:01:50 -07:00
Hunter Nichols 116f102ebf Fixed units in LIB files when cacti is selected as the model. Changed model data gather to only use the extended config. 2021-09-20 16:35:16 -07:00
Hunter Nichols 1236a0773a Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage. 2021-09-07 15:56:27 -07:00
Hunter Nichols 12c03ddd9f Fixed issues with load capcitance units. Changed freepdk45 r and c wire values to be more in line with cacti. 2021-08-16 22:58:26 -07:00
Hunter Nichols 134bf573ec Removed windows EOL characters. 2021-08-04 16:09:04 -07:00
mrg 9694237dba Flip MSB and LSB in lib file due to bug report 2021-07-28 08:12:33 -07:00
Hunter Nichols 1e08005639 Merge branch 'dev' into cacti_model 2021-07-26 14:35:47 -07:00
Hunter Nichols 3e0a49e58d Added options for the model type in timing graph (cacti or elmore) 2021-07-25 22:28:23 -07:00
Hunter Nichols 5ad86538d4 Renamed graph_util to timing_graph to match the module name 2021-07-25 20:21:54 -07:00
Hunter Nichols 7fc4469b97 Converted input load to Farads for cacti module to fit other units. 2021-07-25 17:22:03 -07:00
Hunter Nichols 1acc10e9d5 Added name changes to on resistance params. Added input capacitance functions to relevant modules for CACTI input load functions. 2021-07-21 12:24:08 -07:00
Hunter Nichols ebc91814e5 Fixed various issues with imported code from CACTI, added CACTI as an option for analytical sim, added placeholder names in tech files for CACTI 2021-07-12 15:48:47 -07:00
Hunter Nichols c1efa2de59 Added delay function for cacti, moved cacti related delay functions to hierarchy_spice, and trimmed the functions to remove irrelevant options for OpenRAM. 2021-07-07 13:22:30 -07:00
mrg 2711093442 Improve signal debug output 2021-07-01 12:47:17 -07:00
mrg bbdc728ac5 Edits to functional simulation. 
Use correct .TRAN with max timestep.
Seed functional sim with a 3 writes to start for more read addresses.
Move formatting code to simulation module to share.
 2021-07-01 09:59:13 -07:00
Hunter Nichols 8c48520de6 Added cacti-like model and adapted several functions from cacti into python. 2021-06-30 15:50:54 -07:00
mrg 1ae68637ee Utilize same format for output 2021-06-29 17:04:32 -07:00
mrg 91603e7e01 Fix spare+value notation error 2021-06-29 16:44:52 -07:00
mrg 927de3a240 Debugging then disabling spare cols functional sim for now. 2021-06-29 15:47:53 -07:00
mrg 4a9f361ab9 Save raw file by default for Xyce. Change command debug level. 2021-06-29 11:27:33 -07:00
mrg ee1c2054d3 Add formatted debug output 2021-06-29 11:26:49 -07:00
mrg d2a1f6b654 Add num_rows/cols to sim 2021-06-29 09:35:33 -07:00
mrg c4aec6af8c Functional fixes. 
Off by one error of max address with redundant rows.
Select reads 3x more during functional sim.
 2021-06-29 09:33:44 -07:00
Hunter Nichols 294ccf602e Merged with dev, addressed conflict in port data 2021-06-21 17:23:32 -07:00
Hunter Nichols 470317eaa4 Changed bitcell exclusion to instead exclude array instances to prevent issues of module exclusion affecting other modules. 2021-06-21 17:20:25 -07:00
mrg d53bc98ff5 Exit with error when spice models not found. Use ngspice if no simulator defined. 2021-06-21 13:14:08 -07:00
Hunter Nichols 131ff8bcef Changed the regression test to only run models for the output being tested. 2021-06-16 23:50:20 -07:00
mrg b7f1c8e8fc Fix name for detecting single port 2021-06-16 19:07:56 -07:00
mrg c7c319c11f Use extra bitcell version tag only for single port in sky130 2021-06-16 19:06:12 -07:00
mrg d119a0e7ff Use sky130 bitcell in simulation for BLs 2021-06-16 18:45:53 -07:00
mrg 6ac082ce23 Only replace simulator if it is defined. 2021-06-16 10:44:13 -07:00
Hunter Nichols 74b55ea83b Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs. 2021-06-14 14:39:54 -07:00
Hunter Nichols 7df36a916b Added an exclusion for unused column mux paths to prevent multiple outputs paths in graph. 2021-06-14 13:51:52 -07:00
mrg 8964abc2b7 Change simulator based on one in use. 2021-06-09 16:02:32 -07:00
Hunter Nichols 4ec2e1240f Merge branch 'dev' into automated_analytical_model 2021-06-09 15:45:41 -07:00
Hunter Nichols ccf98ad5a6 Added accuracy check in regression model test. 2021-06-09 13:44:42 -07:00
Hunter Nichols b6b20c1f43 Removed level 0 debug statements for bitlines naming. 2021-06-09 12:53:31 -07:00
Hunter Nichols f25dcf1b63 Fixed issue with bitline name warning occuring when no issue is present. 2021-06-09 12:52:26 -07:00
Hunter Nichols 3d82718f5a Changed neural network model to be sklearn based 2021-06-07 12:26:45 -07:00
Hunter Nichols 331e6f8dd5 Added functions for testing accuracy of current regression model and associated test. 2021-06-04 15:04:52 -07:00
Hunter Nichols 54639bbb94 Added more data for regression models 2021-06-04 13:37:21 -07:00
mrg 537fd6eff9 Use None instead of empty string for tool names. 2021-06-01 16:41:14 -07:00
Hunter Nichols b3bcf48d2e Merge branch 'dev' into automated_analytical_model 2021-05-26 18:42:24 -07:00
Hunter Nichols a53c6c51ed Added sim data for freepdk45 and removed stale data 2021-05-26 18:40:46 -07:00
mrg e16f44cc81 Update lib file with external supply names 2021-05-26 15:34:32 -07:00
mrg 4a8e0cdabb Add top-level pin functionality 2021-05-26 15:04:52 -07:00
Hunter Nichols 2f4f8ca912 Fixed conflicts in delay and elmore modules on merge with dev. 2021-05-25 15:25:43 -07:00
Hunter Nichols 76f5578cc1 Removed path delays from characterization output to not disturb the current testing flow. 2021-05-25 15:19:27 -07:00
Hunter Nichols 23368c0fcf Updated tests and elmore model with load_slew lists. Changed naming on characterization output to not clash with testing. 2021-05-25 14:49:28 -07:00
Hunter Nichols 1488b31dce Adjusted model prediction to account for a single datafile. Adjusted unscaling data as well. 2021-05-24 12:53:51 -07:00
Hunter Nichols 53503f40d2 Changed util functions to expect multiple outputs in data. Changed train models to account for multiple outputs when reading in data. 2021-05-24 12:03:26 -07:00
mrg 9c01e22281 Prioritize Xyce. 2021-05-21 12:05:10 -07:00
mrg f856a44376 Restrict to direct KLU solver 2021-05-21 12:04:26 -07:00
mrg fc17a1ff45 Xyce can be capital or lower case 2021-05-21 12:04:26 -07:00
mrg eadf7eedc5 Prioritize Xyce to last until bugs resolved. 2021-05-21 10:01:37 -07:00
Hunter Nichols 41c8eeb23c Adjusted paths in makefile for generating data used in regression models 2021-05-20 13:05:16 -07:00
Hunter Nichols 0434e57609 Added target in makefile to run configs and store results in tech directory. 2021-05-17 14:03:32 -07:00
mrg 3abebe4068 Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
mrg 7534610cdd Add MPI capability for Xyce threading. 2021-05-14 11:45:37 -07:00
mrg 67a67111a6 Initial Xyce support. 2021-05-14 11:28:29 -07:00
mrg 3959cf73d1 Remove setup/hold measure and compute it directly. 2021-05-14 10:11:14 -07:00
mrg 9555b52aaa Remove setup/hold measure and compute it directly. 2021-05-14 10:01:10 -07:00
Hunter Nichols 16904496ac Made path delays write out to the extended OPTS file. 2021-05-05 01:14:54 -07:00
Hunter Nichols b8c7fcf182 Removed measurement check which conflicts with multiport memories 2021-04-21 15:53:27 -07:00
Hunter Nichols 5dad0f2c0e Merged with dev, fixed import conflict in lib 2021-04-18 23:59:35 -07:00
mrg 61b1b90dd3 Use built in binary conversion. Improve spare debug output. 2021-04-07 16:08:29 -07:00
mrg 5843aa037c Update functional test to use spare columns separately. 
Fix no spare columns data width error.
 2021-04-07 16:08:24 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg 014c95f761 Add accounting output to ngspice 2021-04-01 16:48:15 -07:00
mrg c7f99aef2c Add functional comment to aid debugging checks. 2021-03-31 12:14:20 -07:00
mrg 671470f5f2 Skywater changes. 
Default 1 thread and no temp subdirectory.
Add skywater setup/hold golden data
Add CLI option for simulation threads (-m)
Add compatibility mode option and nomodcheck for ngspice to speed up sky130 model loading.
Make subdir when using default /tmp dir.
Pass num_threads so temp subdirs are created.
 2021-03-22 15:48:14 -07:00
Hunter Nichols 6f01ab4792 Added simulation time modeling to regression model. 2021-03-22 12:55:29 -07:00
Hunter Nichols 208586a8e8 Added simulation time in the datasheet 2021-03-22 12:21:10 -07:00
Hunter Nichols 2cd3d28add linear regression model coefficients are now written to the extended config file 2021-03-02 13:14:56 -08:00
mrg 90cb9f581f Fixes to get hspice delay test to pass. 2021-03-02 09:28:41 -08:00
mrg 9e7c04a43a Merge lekez2005 changes WITHOUT control logic change. 2021-03-01 15:19:30 -08:00
mrg 4ab694033d Merge remote-tracking branch 'bvhoof/dev' into dev 2021-03-01 12:16:26 -08:00
Bob Vanhoof f5a9ab3b2c cleanup clutter 2021-03-01 15:23:57 +01:00
Bob Vanhoof fde8794282 calibre pex modifications to run hierarchical pex 2021-03-01 09:56:25 +01:00
ota2 9d025604ff Simulate calibre extracted netlists without requiring extra layout ports 2021-02-27 19:29:18 -05:00
ota2 9a2987ad07 Add spectre simulator 2021-02-27 19:25:00 -05:00