mirror of https://github.com/VLSIDA/OpenRAM.git
Use built in binary conversion. Improve spare debug output.
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mrg
parent
229b0059c4
commit
61b1b90dd3
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@ -9,6 +9,7 @@ import collections
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import debug
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import random
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import math
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from numpy import binary_repr
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from .stimuli import *
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from .charutils import *
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from globals import OPTS
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@ -53,7 +54,13 @@ class functional(simulation):
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self.max_data = 2 ** self.word_size - 1
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self.max_col_data = 2 ** self.num_spare_cols - 1
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self.words_per_row_bits = int(math.log(self.words_per_row) / math.log(2))
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if self.words_per_row>1:
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# This will truncate bits for word addressing in a row_addr_dff
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# This makes one set of spares per row by using top bits of the address
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self.addr_spare_index = -int(math.log(self.words_per_row) / math.log(2))
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else:
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# This will select the entire address when one word per row
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self.addr_spare_index = self.addr_size
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# If trim is set, specify the valid addresses
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self.valid_addresses = set()
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self.max_address = 2**self.addr_size - 1 + (self.num_spare_rows * self.words_per_row)
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@ -137,10 +144,11 @@ class functional(simulation):
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for port in self.write_ports:
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addr = self.gen_addr()
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(word, spare) = self.gen_data()
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comment = self.gen_cycle_comment("write", word, addr, "1" * self.num_wmasks, port, self.t_current)
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combined_word = "{}+{}".format(word, spare)
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comment = self.gen_cycle_comment("write", combined_word, addr, "1" * self.num_wmasks, port, self.t_current)
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self.add_write_one_port(comment, addr, word + spare, "1" * self.num_wmasks, port)
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self.stored_words[addr] = word
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self.stored_spares[addr[:-self.words_per_row_bits]] = spare
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self.stored_spares[addr[:self.addr_spare_index]] = spare
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# All other read-only ports are noops.
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for port in self.read_ports:
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@ -158,7 +166,9 @@ class functional(simulation):
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if port in self.write_ports:
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self.add_noop_one_port(port)
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else:
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comment = self.gen_cycle_comment("read", word, addr, "0" * self.num_wmasks, port, self.t_current)
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(addr, word, spare) = self.get_data()
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combined_word = "{}+{}".format(word, spare)
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comment = self.gen_cycle_comment("read", combined_word, addr, "0" * self.num_wmasks, port, self.t_current)
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self.add_read_one_port(comment, addr, port)
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self.add_read_check(word, port)
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self.cycle_times.append(self.t_current)
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@ -187,14 +197,15 @@ class functional(simulation):
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self.add_noop_one_port(port)
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else:
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(word, spare) = self.gen_data()
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comment = self.gen_cycle_comment("write", word, addr, "1" * self.num_wmasks, port, self.t_current)
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combined_word = "{}+{}".format(word, spare)
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comment = self.gen_cycle_comment("write", combined_word, addr, "1" * self.num_wmasks, port, self.t_current)
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self.add_write_one_port(comment, addr, word + spare, "1" * self.num_wmasks, port)
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self.stored_words[addr] = word
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self.stored_spares[addr[:-self.words_per_row_bits]] = spare
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self.stored_spares[addr[:self.addr_spare_index]] = spare
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w_addrs.append(addr)
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elif op == "partial_write":
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# write only to a word that's been written to
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(addr, old_word, old_spares) = self.get_data()
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(addr, old_word, old_spare) = self.get_data()
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# two ports cannot write to the same address
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if addr in w_addrs:
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self.add_noop_one_port(port)
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@ -202,15 +213,16 @@ class functional(simulation):
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(word, spare) = self.gen_data()
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wmask = self.gen_wmask()
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new_word = self.gen_masked_data(old_word, word, wmask)
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comment = self.gen_cycle_comment("partial_write", word, addr, wmask, port, self.t_current)
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combined_word = "{}+{}".format(word, spare)
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comment = self.gen_cycle_comment("partial_write", combined_word, addr, wmask, port, self.t_current)
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self.add_write_one_port(comment, addr, word + spare, wmask, port)
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self.stored_words[addr] = new_word
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self.stored_spares[addr[:-self.words_per_row_bits]] = spare
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self.stored_spares[addr[:self.addr_spare_index]] = spare
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w_addrs.append(addr)
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else:
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(addr, word) = random.choice(list(self.stored_words.items()))
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spare = self.stored_spares[addr[:-self.words_per_row_bits]]
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combined_word = word + spare
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spare = self.stored_spares[addr[:self.addr_spare_index]]
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combined_word = "{}+{}".format(word, spare)
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# The write driver is not sized sufficiently to drive through the two
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# bitcell access transistors to the read port. So, for now, we do not allow
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# a simultaneous write and read to the same address on different ports. This
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@ -220,7 +232,7 @@ class functional(simulation):
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else:
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comment = self.gen_cycle_comment("read", combined_word, addr, "0" * self.num_wmasks, port, self.t_current)
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self.add_read_one_port(comment, addr, port)
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self.add_read_check(combined_word, port)
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self.add_read_check(word + spare, port)
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self.cycle_times.append(self.t_current)
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self.t_current += self.period
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@ -286,7 +298,7 @@ class functional(simulation):
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def check_stim_results(self):
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for i in range(len(self.read_check)):
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if self.read_check[i][0] != self.read_results[i][0]:
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str = "FAILED: {0} value {1} does not match written value {2} read during cycle {3} at time {4}n"
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str = "FAILED: {0} read value {1} does not match written value {2} during cycle {3} at time {4}n"
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error = str.format(self.read_results[i][1],
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self.read_results[i][0],
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self.read_check[i][0],
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@ -321,10 +333,10 @@ class functional(simulation):
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def gen_data(self):
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""" Generates a random word to write. """
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random_value = random.randint(0, self.max_data)
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data_bits = self.convert_to_bin(random_value, self.word_size)
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data_bits = binary_repr(random_value, self.word_size)
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if self.num_spare_cols>0:
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random_value = random.randint(0, self.max_col_data)
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spare_bits = self.convert_to_bin(random_value, self.num_spare_cols)
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spare_bits = binary_repr(random_value, self.num_spare_cols)
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else:
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spare_bits = ""
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return data_bits, spare_bits
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@ -335,7 +347,7 @@ class functional(simulation):
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random_value = random.sample(self.valid_addresses, 1)[0]
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else:
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random_value = random.randint(0, self.max_address)
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addr_bits = self.convert_to_bin(random_value, self.addr_size)
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addr_bits = binary_repr(random_value, self.addr_size)
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return addr_bits
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def get_data(self):
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@ -343,15 +355,9 @@ class functional(simulation):
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# Used for write masks since they should be writing to previously written addresses
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addr = random.choice(list(self.stored_words.keys()))
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word = self.stored_words[addr]
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spare = self.stored_spares[addr[:-self.words_per_row_bits]]
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spare = self.stored_spares[addr[:self.addr_spare_index]]
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return (addr, word, spare)
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def convert_to_bin(self, value, size):
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new_value = str.replace(bin(value), "0b", "")
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for i in range(size - len(new_value)):
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new_value = "0" + new_value
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return new_value
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def write_functional_stimulus(self):
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""" Writes SPICE stimulus. """
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self.stim_sp = "functional_stim.sp"
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