mirror of https://github.com/VLSIDA/OpenRAM.git
Renamed graph_util to timing_graph to match the module name
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@ -10,7 +10,7 @@ import math
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import tech
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from globals import OPTS
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from sram_factory import factory
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import graph_util
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import timing_graph
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class simulation():
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@ -541,7 +541,7 @@ class simulation():
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self.sram.graph_exclude_column_mux(self.bitline_column, port)
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# Generate new graph every analysis as edges might change depending on test bit
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self.graph = graph_util.timing_graph()
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self.graph = timing_graph.timing_graph()
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self.sram_instance_name = "X{}".format(self.sram.name)
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self.sram.build_graph(self.graph, self.sram_instance_name, self.pins)
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