mirror of https://github.com/VLSIDA/OpenRAM.git
Remove setup/hold measure and compute it directly.
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parent
9555b52aaa
commit
3959cf73d1
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@ -170,11 +170,11 @@ class setup_hold():
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self.stim.run_sim(self.stim_sp)
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ideal_clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay"))
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# We use a 1/2 speed clock for some reason...
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setuphold_time = (feasible_bound - 2 * self.period) / 1e9
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setuphold_time = (feasible_bound - 2 * self.period)
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if mode == "SETUP": # SETUP is clk-din, not din-clk
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passing_setuphold_time = -1e9 * setuphold_time
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passing_setuphold_time = -1 * setuphold_time
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else:
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passing_setuphold_time = 1e9 * setuphold_time
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passing_setuphold_time = setuphold_time
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debug.info(2, "*** {0} CHECK: {1} Ideal Clk-to-Q: {2} Setup/Hold: {3}".format(mode,
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correct_value,
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ideal_clk_to_q,
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@ -208,11 +208,11 @@ class setup_hold():
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self.stim.run_sim(self.stim_sp)
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clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay"))
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# We use a 1/2 speed clock for some reason...
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setuphold_time = (target_time - 2 * self.period) / 1e9
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setuphold_time = (target_time - 2 * self.period)
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if mode == "SETUP": # SETUP is clk-din, not din-clk
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passing_setuphold_time = -1e9 * setuphold_time
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passing_setuphold_time = -1 * setuphold_time
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else:
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passing_setuphold_time = 1e9 * setuphold_time
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passing_setuphold_time = setuphold_time
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if type(clk_to_q) == float and (clk_to_q < 1.1 * ideal_clk_to_q):
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debug.info(2, "PASS Clk-to-Q: {0} Setup/Hold: {1}".format(clk_to_q, setuphold_time))
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feasible_bound = target_time
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