Added simulation time modeling to regression model.

This commit is contained in:
Hunter Nichols 2021-03-22 12:55:29 -07:00
parent 208586a8e8
commit 6f01ab4792
2 changed files with 14 additions and 5 deletions

View File

@ -26,6 +26,7 @@ class lib:
self.sram = sram
self.sp_file = sp_file
self.use_model = use_model
self.pred_time = None
self.set_port_indices()
self.prepare_tables()
@ -151,7 +152,10 @@ class lib:
self.corner_name = lib_name.replace(self.out_dir,"").replace(".lib","")
self.characterize()
self.lib.close()
total_time = time.time()-run_start
if self.pred_time == None:
total_time = time.time()-run_start
else:
total_time = self.pred_time
self.parse_info(self.corner,lib_name, is_first_corner, total_time)
is_first_corner = False
@ -637,7 +641,9 @@ class lib:
probe_data = self.sram.word_size - 1
char_results = self.d.analyze(probe_address, probe_data, self.load_slews)
self.char_sram_results, self.char_port_results = char_results
if 'sim_time' in self.char_sram_results:
self.pred_time = self.char_sram_results['sim_time']
def compute_setup_hold(self):
""" Do the analysis if we haven't characterized a FF yet """
# Do the analysis if we haven't characterized a FF yet

View File

@ -22,7 +22,8 @@ data_fnames = ["rise_delay.csv",
"write0_power.csv",
"read1_power.csv",
"read0_power.csv",
"leakage_data.csv"]
"leakage_data.csv",
"sim_time.csv"]
# Positions must correspond to data_fname list
lib_dnames = ["delay_lh",
"delay_hl",
@ -32,7 +33,8 @@ lib_dnames = ["delay_lh",
"write0_power",
"read1_power",
"read0_power",
"leakage_power"]
"leakage_power",
"sim_time"]
# Check if another data dir was specified
if OPTS.sim_data_path == None:
data_dir = OPTS.openram_tech+relative_data_path
@ -100,7 +102,8 @@ class regression_model(simulation):
# Estimate the period as double the delay with margin
period_margin = 0.1
sram_data = {"min_period": sram_vals['delay_lh'] * 2,
"leakage_power": sram_vals["leakage_power"]}
"leakage_power": sram_vals["leakage_power"],
"sim_time":sram_vals["sim_time"]}
debug.info(2, "SRAM Data:\n{}".format(sram_data))
debug.info(2, "Port Data:\n{}".format(port_data))