mirror of https://github.com/VLSIDA/OpenRAM.git
Remove setup/hold measure and compute it directly.
This commit is contained in:
mrg
parent
d43edd95e4
commit
9555b52aaa
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@ -76,10 +76,10 @@ class setup_hold():
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self.stim.write_supply()
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def write_data(self, mode, target_time, correct_value):
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"""Create the data signals for setup/hold analysis. First period is to
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"""
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Create the data signals for setup/hold analysis. First period is to
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initialize it to the opposite polarity. Second period is used for
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characterization.
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"""
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self.sf.write("\n* Generation of the data and clk signals\n")
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if correct_value == 1:
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@ -106,8 +106,11 @@ class setup_hold():
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setup=0)
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def write_clock(self):
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""" Create the clock signal for setup/hold analysis. First period initializes the FF
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while the second is used for characterization."""
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"""
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Create the clock signal for setup/hold analysis.
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First period initializes the FF
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while the second is used for characterization.
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"""
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self.stim.gen_pwl(sig_name="clk",
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# initial clk edge is right after the 0 time to initialize a flop
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@ -128,16 +131,6 @@ class setup_hold():
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else:
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dout_rise_or_fall = "FALL"
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# in SETUP mode, the input mirrors what the output should be
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if mode == "SETUP":
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din_rise_or_fall = dout_rise_or_fall
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else:
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# in HOLD mode, however, the input should be opposite of the output
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if correct_value == 1:
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din_rise_or_fall = "FALL"
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else:
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din_rise_or_fall = "RISE"
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self.sf.write("\n* Measure statements for pass/fail verification\n")
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trig_name = "clk"
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targ_name = "Q"
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@ -153,19 +146,6 @@ class setup_hold():
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trig_td=1.9 * self.period,
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targ_td=1.9 * self.period)
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targ_name = "D"
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# Start triggers right after initialize value is returned to normal
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# at one period
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self.stim.gen_meas_delay(meas_name="setup_hold_time",
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trig_name=trig_name,
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targ_name=targ_name,
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trig_val=trig_val,
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targ_val=targ_val,
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trig_dir="RISE",
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targ_dir=din_rise_or_fall,
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trig_td=1.2 * self.period,
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targ_td=1.2 * self.period)
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def bidir_search(self, correct_value, mode):
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""" This will perform a bidirectional search for either setup or hold times.
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It starts with the feasible priod and looks a half period beyond or before it
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@ -189,26 +169,29 @@ class setup_hold():
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correct_value=correct_value)
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self.stim.run_sim(self.stim_sp)
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ideal_clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay"))
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setuphold_time = convert_to_float(parse_spice_list("timing", "setup_hold_time"))
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debug.info(2,"*** {0} CHECK: {1} Ideal Clk-to-Q: {2} Setup/Hold: {3}".format(mode, correct_value,ideal_clk_to_q,setuphold_time))
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# We use a 1/2 speed clock for some reason...
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setuphold_time = (feasible_bound - 2 * self.period) / 1e9
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if mode == "SETUP": # SETUP is clk-din, not din-clk
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passing_setuphold_time = -1e9 * setuphold_time
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else:
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passing_setuphold_time = 1e9 * setuphold_time
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debug.info(2, "*** {0} CHECK: {1} Ideal Clk-to-Q: {2} Setup/Hold: {3}".format(mode,
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correct_value,
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ideal_clk_to_q,
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setuphold_time))
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if type(ideal_clk_to_q)!=float or type(setuphold_time)!=float:
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debug.error("Initial hold time fails for data value feasible bound {0} Clk-to-Q {1} Setup/Hold {2}".format(feasible_bound,
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ideal_clk_to_q,
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setuphold_time),
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if type(ideal_clk_to_q)!=float:
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debug.error("Initial hold time fails for data value feasible "
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"bound {0} Clk-to-Q {1} Setup/Hold {2}".format(feasible_bound,
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ideal_clk_to_q,
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setuphold_time),
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2)
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if mode == "SETUP": # SETUP is clk-din, not din-clk
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setuphold_time *= -1e9
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else:
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setuphold_time *= 1e9
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passing_setuphold_time = setuphold_time
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debug.info(2, "Checked initial {0} time {1}, data at {2}, clock at {3} ".format(mode,
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setuphold_time,
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feasible_bound,
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2 * self.period))
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#raw_input("Press Enter to continue...")
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# raw_input("Press Enter to continue...")
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while True:
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target_time = (feasible_bound + infeasible_bound) / 2
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@ -224,15 +207,14 @@ class setup_hold():
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self.stim.run_sim(self.stim_sp)
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clk_to_q = convert_to_float(parse_spice_list("timing", "clk2q_delay"))
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setuphold_time = convert_to_float(parse_spice_list("timing", "setup_hold_time"))
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if type(clk_to_q) == float and (clk_to_q < 1.1 * ideal_clk_to_q) and type(setuphold_time)==float:
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if mode == "SETUP": # SETUP is clk-din, not din-clk
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setuphold_time *= -1e9
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else:
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setuphold_time *= 1e9
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# We use a 1/2 speed clock for some reason...
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setuphold_time = (target_time - 2 * self.period) / 1e9
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if mode == "SETUP": # SETUP is clk-din, not din-clk
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passing_setuphold_time = -1e9 * setuphold_time
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else:
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passing_setuphold_time = 1e9 * setuphold_time
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if type(clk_to_q) == float and (clk_to_q < 1.1 * ideal_clk_to_q):
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debug.info(2, "PASS Clk-to-Q: {0} Setup/Hold: {1}".format(clk_to_q, setuphold_time))
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passing_setuphold_time = setuphold_time
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feasible_bound = target_time
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else:
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debug.info(2, "FAIL Clk-to-Q: {0} Setup/Hold: {1}".format(clk_to_q, setuphold_time))
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@ -242,7 +224,6 @@ class setup_hold():
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debug.info(3, "CONVERGE {0} vs {1}".format(feasible_bound, infeasible_bound))
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break
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debug.info(2, "Converged on {0} time {1}.".format(mode, passing_setuphold_time))
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return passing_setuphold_time
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