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Code formatting

This commit is contained in:
Bugra Onal 2022-09-01 16:19:14 -07:00
parent 05ab45f39b
commit fcfb9391f6
4 changed files with 51 additions and 51 deletions
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33
compiler/characterizer/delay.py
View File

@ -605,8 +605,8 @@ class delay(simulation):
return net
original_net = net
net = net[len(prefix):]
net = net.replace(".", "_").replace("[", "\[").replace("]", "\]")
for pattern in ["\sN_{}_[MXmx]\S+_[gsd]".format(net), net]:
net = net.replace(".", "_").replace("[", r"\[").replace("]", r"\]")
for pattern in [r"\sN_{}_[MXmx]\S+_[gsd]".format(net), net]:
try:
match = check_output(["grep", "-m1", "-o", "-iE", pattern, self.sp_file])
return prefix + match.decode().strip()
@ -616,8 +616,8 @@ class delay(simulation):
def load_all_measure_nets(self):
measurement_nets = set()
for port, meas in zip(self.targ_read_ports * len(self.read_meas_lists) +
self.targ_write_ports * len(self.write_meas_lists),
for port, meas in zip(self.targ_read_ports * len(self.read_meas_lists)
+ self.targ_write_ports * len(self.write_meas_lists),
self.read_meas_lists + self.write_meas_lists):
for measurement in meas:
visited = getattr(measurement, 'pex_visited', False)
@ -791,7 +791,7 @@ class delay(simulation):
for port in self.targ_write_ports:
if not self.check_bit_measures(self.write_bit_meas, port):
return(False, {})
return (False, {})
debug.info(2, "Checking write values for port {0}".format(port))
write_port_dict = {}
@ -805,7 +805,7 @@ class delay(simulation):
for port in self.targ_read_ports:
# First, check that the memory has the right values at the right times
if not self.check_bit_measures(self.read_bit_meas, port):
return(False, {})
return (False, {})
debug.info(2, "Checking read delay values for port {0}".format(port))
# Check sen timing, then bitlines, then general measurements.
@ -942,7 +942,7 @@ class delay(simulation):
if type(val) != float or val > self.period / 2:
debug.info(1, 'Failed measurement:{}={}'.format(meas.name, val))
value_dict[meas.name] = val
#debug.info(0, "value_dict={}".format(value_dict))
# debug.info(0, "value_dict={}".format(value_dict))
return value_dict
def run_power_simulation(self):
@ -1145,7 +1145,7 @@ class delay(simulation):
self.analysis_init(probe_address, probe_data)
loads = []
slews = []
for load,slew in load_slews:
for load, slew in load_slews:
loads.append(load)
slews.append(slew)
self.load=max(loads)
@ -1168,15 +1168,15 @@ class delay(simulation):
# 4) At the minimum period, measure the delay, slew and power for all slew/load pairs.
self.period = min_period
char_port_data = self.simulate_loads_and_slews(load_slews, leakage_offset)
if OPTS.use_specified_load_slew != None and len(load_slews) > 1:
if OPTS.use_specified_load_slew is not None and len(load_slews) > 1:
debug.warning("Path delay lists not correctly generated for characterizations of more than 1 load,slew")
# Get and save the path delays
bl_names, bl_delays, sen_names, sen_delays = self.get_delay_lists(self.path_delays)
# Removed from characterization output temporarily
#char_sram_data["bl_path_measures"] = bl_delays
#char_sram_data["sen_path_measures"] = sen_delays
#char_sram_data["bl_path_names"] = bl_names
#char_sram_data["sen_path_names"] = sen_names
# char_sram_data["bl_path_measures"] = bl_delays
# char_sram_data["sen_path_measures"] = sen_delays
# char_sram_data["bl_path_names"] = bl_names
# char_sram_data["sen_path_names"] = sen_names
# FIXME: low-to-high delays are altered to be independent of the period. This makes the lib results less accurate.
self.alter_lh_char_data(char_port_data)
@ -1185,7 +1185,7 @@ class delay(simulation):
def alter_lh_char_data(self, char_port_data):
"""Copies high-to-low data to low-to-high data to make them consistent on the same clock edge."""
# This is basically a hack solution which should be removed/fixed later.
# This is basically a hack solution which should be removed/fixed later.
for port in self.all_ports:
char_port_data[port]['delay_lh'] = char_port_data[port]['delay_hl']
char_port_data[port]['slew_lh'] = char_port_data[port]['slew_hl']
@ -1194,7 +1194,6 @@ class delay(simulation):
"""Simulate all specified output loads and input slews pairs of all ports"""
measure_data = self.get_empty_measure_data_dict()
path_dict = {}
# Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways.
self.targ_read_ports = self.read_ports
self.targ_write_ports = self.write_ports
@ -1352,9 +1351,9 @@ class delay(simulation):
# Get any available read/write port in case only a single write or read ports is being characterized.
cur_read_port = self.get_available_port(get_read_port=True)
cur_write_port = self.get_available_port(get_read_port=False)
debug.check(cur_read_port != None,
debug.check(cur_read_port is not None,
"Characterizer requires at least 1 read port")
debug.check(cur_write_port != None,
debug.check(cur_write_port is not None,
"Characterizer requires at least 1 write port")
# Create test cycles for specified target ports.

7
compiler/characterizer/functional.py
View File

@ -146,7 +146,6 @@ class functional(simulation):
comment = self.gen_cycle_comment("noop", "0" * self.word_size, "0" * self.addr_size, "0" * self.num_wmasks, 0, self.t_current)
self.add_noop_all_ports(comment)
# 1. Write all the write ports 2x to seed a bunch of locations.
for i in range(3):
for port in self.write_ports:
@ -268,7 +267,7 @@ class functional(simulation):
self.read_check.append([word,
"{0}{1}".format(self.dout_name, port),
self.t_current + self.period,
int(self.t_current/self.period)])
int(self.t_current / self.period)])
def read_stim_results(self):
# Extract dout values from spice timing.lis
@ -319,8 +318,8 @@ class functional(simulation):
cycle,
self.read_results[i][2],
check_name)
return(0, error)
return(1, "SUCCESS")
return (0, error)
return (1, "SUCCESS")
def gen_wmask(self):
wmask = ""

36
compiler/characterizer/measurements.py
View File

@ -11,16 +11,18 @@ from abc import ABC, abstractmethod
from .stimuli import *
from .charutils import *
class spice_measurement(ABC):
"""Base class for spice stimulus measurements."""
def __init__(self, measure_name, measure_scale=None, has_port=True):
#Names must be unique for correct spice simulation, but not enforced here.
# Names must be unique for correct spice simulation, but not enforced here.
self.name = measure_name
self.measure_scale = measure_scale
self.has_port = has_port #Needed for error checking
#Some meta values used externally. variables are added here for consistency accross the objects
self.has_port = has_port # Needed for error checking
# Some meta values used externally. variables are added here for consistency accross the objects
self.meta_str = None
self.meta_add_delay = False
@abstractmethod
def get_measure_function(self):
return None
@ -31,27 +33,27 @@ class spice_measurement(ABC):
def write_measure(self, stim_obj, input_tuple):
measure_func = self.get_measure_function()
if measure_func == None:
debug.error("Did not set measure function",1)
if measure_func is None:
debug.error("Did not set measure function", 1)
measure_vals = self.get_measure_values(*input_tuple)
measure_func(stim_obj, *measure_vals)
def retrieve_measure(self, port=None):
self.port_error_check(port)
if port != None:
if port is not None:
value = parse_spice_list("timing", "{0}{1}".format(self.name.lower(), port))
else:
value = parse_spice_list("timing", "{0}".format(self.name.lower()))
if type(value)!=float or self.measure_scale == None:
if type(value)!=float or self.measure_scale is None:
return value
else:
return value*self.measure_scale
return value * self.measure_scale
def port_error_check(self, port):
if self.has_port and port == None:
debug.error("Cannot retrieve measurement, port input was expected.",1)
elif not self.has_port and port != None:
debug.error("Unexpected port input received during measure retrieval.",1)
if self.has_port and port is None:
debug.error("Cannot retrieve measurement, port input was expected.", 1)
elif not self.has_port and port is not None:
debug.error("Unexpected port input received during measure retrieval.", 1)
class delay_measure(spice_measurement):
@ -90,7 +92,7 @@ class delay_measure(spice_measurement):
trig_val = self.trig_val_of_vdd * vdd_voltage
targ_val = self.targ_val_of_vdd * vdd_voltage
if port != None:
if port is not None:
# For dictionary indexing reasons, the name is formatted differently than the signals
meas_name = "{}{}".format(self.name, port)
trig_name = self.trig_name_no_port.format(port)
@ -120,7 +122,7 @@ class slew_measure(delay_measure):
self.trig_val_of_vdd = 0.9
self.targ_val_of_vdd = 0.1
else:
debug.error("Unrecognised slew measurement direction={}".format(slew_dir_str),1)
debug.error("Unrecognised slew measurement direction={}".format(slew_dir_str), 1)
self.trig_name_no_port = signal_name
self.targ_name_no_port = signal_name
@ -145,7 +147,7 @@ class power_measure(spice_measurement):
def get_measure_values(self, t_initial, t_final, port=None):
"""Constructs inputs to stimulus measurement function. Variant values are inputs here."""
self.port_error_check(port)
if port != None:
if port is not None:
meas_name = "{}{}".format(self.name, port)
else:
meas_name = self.name
@ -172,7 +174,7 @@ class voltage_when_measure(spice_measurement):
def get_measure_values(self, trig_td, vdd_voltage, port=None):
"""Constructs inputs to stimulus measurement function. Variant values are inputs here."""
self.port_error_check(port)
if port != None:
if port is not None:
# For dictionary indexing reasons, the name is formatted differently than the signals
meas_name = "{}{}".format(self.name, port)
trig_name = self.trig_name_no_port.format(port)
@ -203,7 +205,7 @@ class voltage_at_measure(spice_measurement):
def get_measure_values(self, time_at, port=None):
"""Constructs inputs to stimulus measurement function. Variant values are inputs here."""
self.port_error_check(port)
if port != None:
if port is not None:
# For dictionary indexing reasons, the name is formatted differently than the signals
meas_name = "{}{}".format(self.name, port)
targ_name = self.targ_name_no_port.format(port)

26
compiler/characterizer/simulation.py
View File

@ -235,7 +235,7 @@ class simulation():
self.add_wmask(wmask, port)
self.add_spare_wen("1" * self.num_spare_cols, port)
#Add noops to all other ports.
# Add noops to all other ports.
for unselected_port in self.all_ports:
if unselected_port != port:
self.add_noop_one_port(unselected_port)
@ -267,7 +267,7 @@ class simulation():
self.add_wmask("0" * self.num_wmasks, port)
self.add_spare_wen("0" * self.num_spare_cols, port)
#Add noops to all other ports.
# Add noops to all other ports.
for unselected_port in self.all_ports:
if unselected_port != port:
self.add_noop_one_port(unselected_port)
@ -356,14 +356,14 @@ class simulation():
self.add_noop_one_port(port)
#Add noops to all other ports.
# Add noops to all other ports.
for unselected_port in self.all_ports:
if unselected_port != port:
self.add_noop_one_port(unselected_port)
def append_cycle_comment(self, port, comment):
"""Add comment to list to be printed in stimulus file"""
#Clean up time before appending. Make spacing dynamic as well.
# Clean up time before appending. Make spacing dynamic as well.
time = "{0:.2f} ns:".format(self.t_current)
time_spacing = len(time) + 6
self.cycle_comments.append("Cycle {0:<6d} Port {1:<6} {2:<{3}}: {4}".format(len(self.cycle_times),
@ -388,7 +388,7 @@ class simulation():
split_word2 = [x + '_' * (n != 0 and n % 4 == 0) for n, x in enumerate(split_word)]
# Join the word unreversed back together
new_word = ''.join(reversed(split_word2))
return(new_word)
return (new_word)
# Split extra cols
if self.num_spare_cols > 0:
@ -414,9 +414,9 @@ class simulation():
comment = "\tWriting {0} to address {1} (from port {2}) during cycle {3} ({4}ns - {5}ns)".format(word,
addr,
port,
int(t_current/self.period),
int(t_current / self.period),
t_current,
t_current+self.period)
t_current + self.period)
elif op == "partial_write":
str = "\tWriting (partial) {0} to address {1} with mask bit {2} (from port {3}) during cycle {4} ({5}ns - {6}ns)"
comment = str.format(word,
@ -454,7 +454,7 @@ class simulation():
for i in range(abits):
pin_names.append("{0}{1}_{2}".format(addr_name, port, i))
#Control signals not finalized.
# Control signals not finalized.
for port in range(total_ports):
pin_names.append("CSB{0}".format(port))
for port in range(total_ports):
@ -516,9 +516,9 @@ class simulation():
self.sen_name = sen_with_port
debug.warning("Error occurred while determining SEN name. Can cause faults in simulation.")
column_addr = self.get_column_addr()
# column_addr = self.get_column_addr()
bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)
port_pos = -1 - len(str(column_addr)) - len(str(port))
# port_pos = -1 - len(str(column_addr)) - len(str(port))
if bl_name_port.endswith(str(port) + "_" + str(self.bitline_column)): # single port SRAM case, bl will not be numbered eg bl_0
self.bl_name = bl_name_port
@ -536,7 +536,7 @@ class simulation():
'{}{}_{}'.format(self.dout_name, port, self.probe_data))
self.sen_name = self.get_sen_name(self.graph.all_paths)
#debug.info(2, "s_en {}".format(self.sen_name))
# debug.info(2, "s_en {}".format(self.sen_name))
self.bl_name = "bl{0}_{1}".format(port, OPTS.word_size - 1)
self.br_name = "br{0}_{1}".format(port, OPTS.word_size - 1)
@ -564,10 +564,10 @@ class simulation():
Creates timing graph to generate the timing paths for the SRAM output.
"""
#Make exclusions dependent on the bit being tested.
# Make exclusions dependent on the bit being tested.
self.sram.clear_exclude_bits() # Removes previous bit exclusions
self.sram.graph_exclude_bits(self.wordline_row, self.bitline_column)
port=self.read_ports[0] #FIXME, port_data requires a port specification, assuming single port for now
port=self.read_ports[0] # FIXME, port_data requires a port specification, assuming single port for now
if self.words_per_row > 1:
self.sram.graph_clear_column_mux(port)
self.sram.graph_exclude_column_mux(self.bitline_column, port)