mirror of https://github.com/VLSIDA/OpenRAM.git
Pin generation instead of parsing
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parent
eceb35f205
commit
d3753556c1
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@ -48,7 +48,6 @@ class fake_sram(sram_config):
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self.words_per_row = words_per_row
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self.compute_sizes()
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self.pins = ['vdd', 'gnd', 'clk0'] # TODO: remove clk
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def setup_multiport_constants(self):
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"""
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@ -91,13 +90,6 @@ class fake_sram(sram_config):
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self.readonly_ports.append(port_number)
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port_number += 1
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def str_to_pins(self, s):
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pinsRE = re.compile(r'^(\w+)\[(\d+):(\d+)\]')
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match = pinsRE.match(s)
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port, start, end = match.group(1, 2, 3)
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pins = [port + '[' + str(p) + ']' for p in range(int(start) - int(end) + 1)]
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return pins
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def parse_html(self, filename):
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"""
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Parse the HTML file generated from previous SRAM generation
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@ -124,15 +116,42 @@ class fake_sram(sram_config):
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elif val.group(1) == 'Area (µm<sup>2</sup>)':
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self.height = int(val.group(2) ** 0.5)
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self.width = int(val.group(2) ** 0.5)
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if 'Timing Data' in line:
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timingRE = re.compile(r'<tr><td>([\w\[\]:]*) \w* \w*</td><td>[\w\.]*</td><td>[\w\.]*</td><td>\w*</td></tr>')
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values = timingRE.finditer(line)
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for val in values:
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if '[' in val.group(1):
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pins = self.str_to_pins(val.group(1))
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for pin in pins:
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if pin not in self.pins:
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self.pins.append(pin)
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else:
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if val.group(1) not in self.pins:
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self.pins.append(val.group(1))
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self.compute_sizes()
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def generate_pins(self):
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self.pins = ['vdd', 'gnd']
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self.pins.extend(['clk{}'.format(port) for port in range(
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self.num_rw_ports + self.num_r_ports + self.num_w_ports)])
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for port in range(self.num_rw_ports):
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self.pins.extend(['din{0}[{1}]]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['dout{0}[{1}]]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]]'.format(port, bit)
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for bit in range(self.addr_size)])
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if self.num_wmasks != 0:
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self.pins.extend(['wmask{0}[{1}]]'.format(port, bit)
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for bit in range(self.num_wmasks)])
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self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])
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start_port = self.num_rw_ports
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for port in range(start_port, start_port + self.num_r_ports):
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self.pins.extend(['dout{0}[{1}]]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]]'.format(port, bit)
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for bit in range(self.addr_size)])
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self.pins.extend(['csb{}'.format(port)])
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start_port += self.num_r_ports
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for port in range(start_port, start_port + self.num_w_ports):
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self.pins.extend(['din{0}[{1}]]'.format(port, bit)
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for bit in range(self.num_cols)])
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self.pins.extend(['addr{0}[{1}]]'.format(port, bit)
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for bit in range(self.addr_size)])
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if self.num_wmasks != 0:
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self.pins.extend(['wmask{0}[{1}]]'.format(port, bit)
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for bit in range(self.num_wmasks)])
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self.pins.extend(['csb{}'.format(port), 'web{}'.format(port)])
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@ -50,6 +50,7 @@ s = fake_sram(name=OPTS.output_name,
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num_spare_cols=OPTS.num_spare_cols)
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s.parse_html(args[1])
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s.generate_pins()
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s.setup_multiport_constants()
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OPTS.netlist_only = True
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@ -123,6 +123,8 @@ class options(optparse.Values):
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###################
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# Tool options
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###################
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# Top process that was ran (openram, memchar, memfunc)
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top_process = None
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# Variable to select the variant of spice
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spice_name = None
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# The spice executable being used which is derived from the user PATH.
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