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OpenRAM
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157 Commits

Author SHA1 Message Date
Hunter Nichols 53e64fb696 Merge branch 'dev' into characterizer_bug_fixes 2020-11-20 11:16:41 -08:00
Hunter Nichols 9fd473ce70 Fixed issue with selection of column address when checking bitline names. 2020-11-20 01:11:08 -08:00
mrg 033111a5f3 Default to no hierarchical word lines. 2020-11-19 10:48:35 -08:00
Hunter Nichols 35e1a523cc Changed named on delay chain sizing variable. Automatic sizing default is False. 2020-11-17 14:29:01 -08:00
Hunter Nichols df4c2bad1f Disabled debug measures that are WIP. 2020-11-17 13:30:18 -08:00
Hunter Nichols ac425643a0 Merge branch 'dev' into characterizer_bug_fixes 2020-11-17 13:22:56 -08:00
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
Hunter Nichols 84ba5c55d1 Merged with dev 2020-11-10 15:47:56 -08:00
mrg 2c76a2680f Adjust openram options. 
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
 2020-11-05 13:12:26 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
Hunter Nichols 12a8531248 Allowed for OPTS writeback of words_per_row if automatically generated during generation. 2020-10-21 03:02:39 -07:00
mrg 35c91168f7 Add load/slew scale option to config files 2020-10-16 13:52:36 -07:00
mrg cb35c0aff4 Add command line -j option for number of threads. 2020-10-05 15:49:00 -07:00
mrg da83824a70 Merge branch 'wlbuffer' into dev 2020-10-05 15:33:54 -07:00
mrg c06b02e6fc Rename single_level_column_mux to just column_mux 2020-10-05 08:56:51 -07:00
mrg aaa36bf5cf Default to 2 threads only 2020-10-01 09:55:17 -07:00
mrg d315ff18e5 Add num_threads to options. PEP8 cleanup. 2020-10-01 08:07:03 -07:00
Matt Guthaus 112d57d90a Enable riscv tests 2020-09-30 12:39:40 -07:00
mrg b147e8485c PEP8 formatting 2020-09-29 16:52:27 -07:00
mrg d65eb16513 Zjog the WL enable. Min driver is 1. 2020-09-28 12:24:55 -07:00
mrg c7d32089f3 Create RBL wordline buffer with correct polarity. 2020-09-17 14:45:49 -07:00
Hunter Nichols af22e438f1 Added option to output an extended configuration file that includes defaults. 2020-09-08 18:40:39 -07:00
mrg a3195c0827 Add words_per_row and others in config file. 2020-07-13 12:37:56 -07:00
jcirimel 59562f2b92 move accuracy_requirement from techfile to config 2020-06-25 06:44:07 -07:00
mrg 7dfc462ef6 Add magic filter before calibre for sky130 2020-06-15 13:58:26 -07:00
mrg 52ee7b0a19 Disable perimeter pins and make an option 2020-06-14 16:44:10 -07:00
Aditi Sinha d5041afebc Merge branch 'dev' into bisr 2020-06-07 16:27:25 +00:00
mrg 5514996708 Auto-generate port dependent cell names. 2020-06-05 15:09:22 -07:00
Joey Kunzler 001bf1b827 merge conflict - port data 2020-06-02 14:15:39 -07:00
mrg 4a67f7dc71 Thin-cell decoder changes. 
Add hard decoder gates (nand, inv, pnan)
Add conditions for routing using LI layer in s8.
Generalize bus layers for decoders.
Move custom cells to own directory.
Fixed via directions, etc.
Add 4x16 hierarchical decoder and test case
 2020-05-29 10:36:07 -07:00
Joey Kunzler 7505fa5aef update for end caps 2020-05-27 20:03:11 -07:00
Aditi Sinha 2661a42726 changes to support spare columns 2020-04-14 03:09:10 +00:00
Aditi Sinha a5afbfe0aa Fixed errors in extra rows characterization 2020-03-22 20:54:49 +00:00
Matt Guthaus 6ef1b6a4ec Blackbox option for DRC waivers 2019-11-29 15:50:32 -08:00
Matt Guthaus 0cdd3af1aa Change default nominal corners to false and enable in test config. 2019-11-29 12:08:53 -08:00
Matt Guthaus d511f648c6 Move DRC/LVS/PEX tools to tech file. 2019-11-29 12:01:33 -08:00
mrg d583695959 Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
Matt Guthaus e4532083da Increase stages and FO of fixed delay line. 2019-08-05 13:52:32 -07:00
Matt Guthaus 0c5cd2ced9 Merge branch 'dev' into rbl_revamp 2019-07-26 18:01:43 -07:00
jsowash 3bcb79d9d5 Removed code for RW ports to not precharge on writes. Previously, the entire bitline was written where part was an old value and part was the wmask value. 2019-07-24 15:01:20 -07:00
Matt Guthaus 3df8abd38c Clean up. Split class into own file. 2019-07-24 08:15:10 -07:00
jsowash ea2f786dcf Redefined write_size inrecompute_sizes() to take the new word_size() 2019-07-15 14:41:26 -07:00
mrg a189b325ed Merge remote-tracking branch 'origin/dev' into rbl_revamp 2019-07-12 11:10:07 -07:00
mrg 043018e8ba Functional tests working with new RBL. 2019-07-12 08:42:36 -07:00
mrg b9d993c88b Add dummy bitcell module. 
Modify bitcell logic to guess if bitcell is not "bitcell"
No longer need to specify replica (and dummy) bitcell explicitly
Add support for 1 or 2 port replica array.
 2019-07-05 12:58:52 -07:00
jsowash 242771f710 Merge branch 'dev' into add_wmask 2019-06-28 15:44:27 -07:00
jsowash 1f76afd294 Begin wmask functionality. Added wmask to verilog file and config parameters. 2019-06-28 15:43:09 -07:00
Hunter Nichols 4e08e2da87 Merged and fixed conflicts with dev 2019-06-25 16:55:50 -07:00
Hunter Nichols 33c17ac41c Moved manual delay chain declarations from tech files to options. 2019-06-25 15:45:02 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus 74f904a509 Cleanup options for front-end. Improve info output. 2019-04-01 10:35:17 -07:00
Matt Guthaus c3e074c069 Add option for routing supplies. Off by default, but enabled in unit test config files. 2019-04-01 09:58:59 -07:00
Matt Guthaus 95d96bd45d Add OPENRAM_TMP environment check 2019-03-08 11:12:30 -08:00
Hunter Nichols d1218778b1 Fixed merge conflicts 2019-01-28 22:33:08 -08:00
Matt Guthaus 91636be642 Convert all contacts to use the sram_factory 2019-01-16 16:56:06 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Hunter Nichols 51b1bd46da Added option to use delay chain size defined in tech.py 2018-12-14 18:02:19 -08:00
Matt Guthaus ce74827f24 Add new option to enable inline checks at each level of hierarchy. Default is off. 2018-11-13 16:51:19 -08:00
Michael Timothy Grimes 66933ed922 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-27 02:02:24 -07:00
Matt Guthaus a3f13d6eab Remove banks from test configs 2018-09-24 11:41:51 -07:00
Michael Timothy Grimes fc5f163828 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
Matt Guthaus 3539887ee4 Updating ms_flop removal. 
Updated characterizer for dff.
Added new setup/hold results for dff instead of ms_flop.
Removed ms_flop references in sram-base.
Fixed syntax errors in SCN3ME tech file.
 2018-09-13 11:40:24 -07:00
Michael Timothy Grimes f03cd7c3ba Removing multiport_check option that diabled multiport portion of unit tests. Adding multiport checks to several other modules. 2018-09-12 20:22:12 -07:00
Michael Timothy Grimes a7f03858e8 Adding 'multiport_check' option to OPTS. All of the unit tests that have multiport checks in them are now under this conditional. If you want to remove the multiport drc/lvs checks, you can set the option to False, and it will skip those portions. 2018-09-09 23:25:29 -07:00
Matt Guthaus a346bddd88 Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
Matt Guthaus 563ff77d44 Add sram_config class. Rename port variables for better description. 2018-08-31 12:03:28 -07:00
Matt Guthaus e804f36bec Add parameters to give preference to DRC/LVS/PEX tools like we do for spice. 2018-08-28 13:41:26 -07:00
Matt Guthaus 9f051df18d Added netlist only configuration option. 2018-08-27 14:33:02 -07:00
Matt Guthaus 7c6974dd08 Fix options so it is in /tmp in RAM drive 2018-07-05 16:33:26 -07:00
Michael Timothy Grimes b5df0cc30a Merging branch with PrivateRAM dev 2018-05-18 15:15:31 -07:00
Michael Timothy Grimes 683f5fb9fc adding variable for w_ports to be used in multiport design 2018-04-26 14:03:48 -07:00
Matt Guthaus 4c4cfb2a3c Add local dir for output. Will remove later. 2018-04-04 09:55:32 -07:00
Matt Guthaus 97c08bce95 Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. 
Shift s_en buffers even with other cells.
 2018-03-23 08:14:09 -07:00
Matt Guthaus 696433b1ec Add bank_sel to bank_select module as input. 
Remove reference to control in sram.
Add dff_buf_array to options.
Added inverted DFF
Add variable height pinvbuf
 2018-03-23 08:13:39 -07:00
Matt Guthaus 8ca9ba4244 Recreate delay chain and RBL to have vertical poly only. 2018-03-23 08:12:47 -07:00
Matt Guthaus ed8eaed54f Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array. 2018-03-23 08:12:47 -07:00
Matt Guthaus ba82222475 Add bank_select module option 2018-03-05 14:06:12 -08:00
Matt Guthaus 0804a1eceb Add new DFF. Create DFF module. Start dff_array, not tested. 2018-02-14 15:16:28 -08:00
mguthaus 636099c5e1 Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library. 2018-02-12 11:22:47 -08:00
Matt Guthaus 4d35972553 Get default corner options from tech file 2018-02-09 15:49:55 -08:00
Matt Guthaus f86985821a Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated. 2018-02-09 15:33:03 -08:00
Matt Guthaus d552d88f45 Add -d option to not delete temp directory on successful runs. 2018-02-01 11:53:02 -08:00
Matt Guthaus 95fab1ca71 Remove personalized temp dir. 2018-01-19 16:39:14 -08:00
Matt Guthaus 490a70dee9 Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file. 2018-01-19 16:38:19 -08:00
Matt Guthaus 1b30eb4b64 Initial DRC with Magic is done. 2018-01-12 14:39:42 -08:00
Matt Guthaus 7a172873a3 Update unit tests to load verify after config file. Start magic DRC. 2018-01-12 10:24:49 -08:00
Matt Guthaus 1701eac1a9 Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells. 2018-01-11 10:24:44 -08:00
Matt Guthaus 9a4b2b4341 Revised LEF and Verilog generation. Does not read GDS for speed improvements. 2017-12-19 09:01:24 -08:00
Matt Guthaus de5c736cb4 Remove temp directory change. 2017-11-29 16:15:22 -08:00
Matt Guthaus 7ff82a2aed Improved ptx code but removed internal active/poly positions. 2017-11-28 18:13:32 -08:00
mguthaus 09ca8ba17d Improve output format. Rename option to be more sensible. 2017-11-22 15:57:29 -08:00
Matt Guthaus 3e0f39cd8e Skeleton code for indirect DRC/LVS/PEX tools. 2017-11-14 14:59:14 -08:00
Matt Guthaus 29c5ab48f0 Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
Matt Guthaus 8071dcc0f3 Add customsim (xa) as optional simulator. Fix regex to support scientific notation. Go through list of preferred simulators in order. Always abort if command-line simulator not found. 2017-11-12 10:42:41 -08:00
Matt Guthaus 95f1a24f72 Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
mguthaus 6e90bf0d6d Enable output filename and path to be in config file. Command line will over-ride config file. 2017-06-12 14:37:15 -07:00
Matt Guthaus 424c7b7e64 Made back-annotation and analytical modelling boolean options. Default is false. 2017-05-31 08:12:17 -07:00