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OpenRAM
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Removed code for RW ports to not precharge on writes. Previously, the entire bitline was written where part was an old value and part was the wmask value.

This commit is contained in:
jsowash 2019-07-24 15:01:20 -07:00
parent 01493aab3e
commit 3bcb79d9d5
3 changed files with 13 additions and 18 deletions
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13
compiler/characterizer/functional.py
View File

@ -30,10 +30,7 @@ class functional(simulation):
# Seed the characterizer with a constant seed for unit tests
if OPTS.is_unit_test:
random.seed(91218)
#12364?
#12365
#91218
random.seed(12345)
if self.write_size is not None:
self.num_wmasks = int(self.word_size / self.write_size)
@ -136,7 +133,7 @@ class functional(simulation):
elif op == "write":
addr = self.gen_addr()
word = self.gen_data()
# print("w",self.t_current,addr,word)
# print("write",self.t_current,addr,word)
# two ports cannot write to the same address
if addr in w_addrs:
self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks, port)
@ -148,8 +145,6 @@ class functional(simulation):
elif op == "partial_write":
#write only to a word that's been written to
(addr,old_word) = self.get_data()
# rand = random.randint(0,len(w_addrs)-1)
# addr = w_addrs[rand]
word = self.gen_data()
wmask = self.gen_wmask()
new_word = word
@ -159,7 +154,7 @@ class functional(simulation):
lower = bit * self.write_size
upper = lower + self.write_size - 1
new_word = new_word[:lower] + old_word[lower:upper+1] + new_word[upper + 1:]
# print("partial_w",self.t_current,addr,wmask,word, "new", new_word)
# print("partial_w",self.t_current,addr,wmask,word, "partial_w_word:", new_word)
# two ports cannot write to the same address
if addr in w_addrs:
self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks, port)
@ -175,7 +170,7 @@ class functional(simulation):
if addr in w_addrs:
self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks, port)
else:
comment = self.gen_cycle_comment("read", word, addr, self.wmask, port, self.t_current)
# comment = self.gen_cycle_comment("read", word, addr, self.wmask, port, self.t_current)
self.add_read_one_port(comment, addr, rw_read_din_data, "1"*self.num_wmasks, port)
self.write_check.append([word, "{0}{1}".format(self.dout_name,port), self.t_current+self.period, check])
check += 1

16
compiler/modules/control_logic.py
View File

@ -628,14 +628,14 @@ class control_logic(design.design):
offset=out_pos)
def create_pen_row(self):
if self.port_type == "rw":
# input: gated_clk_bar, we_bar, output: pre_p_en
self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en",
mod=self.and2)
self.connect_inst(["gated_clk_buf", "we_bar", "pre_p_en", "vdd", "gnd"])
input_name = "pre_p_en"
else:
input_name = "gated_clk_buf"
# if self.port_type == "rw":
# # input: gated_clk_bar, we_bar, output: pre_p_en
# self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en",
# mod=self.and2)
# self.connect_inst(["gated_clk_buf", "we_bar", "pre_p_en", "vdd", "gnd"])
# input_name = "pre_p_en"
# else:
input_name = "gated_clk_buf"
# input: pre_p_en, output: p_en_bar
self.p_en_bar_inst=self.add_inst(name="inv_p_en_bar",

2
compiler/options.py
View File

@ -142,5 +142,5 @@ class options(optparse.Values):
wordline_driver = "wordline_driver"
write_driver_array = "write_driver_array"
write_driver = "write_driver"
write_mask_array = "write_mask_array"
write_mask_and_array = "write_mask_and_array"