 mrg
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532492d5ae
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Output functional stimulus to output directory.
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2020-11-09 12:00:25 -08:00 |
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mrg
|
10542d6cc3
|
Output DRC and LVS run files to output directory.
|
2020-11-09 11:12:31 -08:00 |
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|
mrg
|
66633a843b
|
Add PDK layer names to tech file
|
2020-11-09 09:10:43 -08:00 |
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|
mrg
|
2da9c307db
|
Disable 4x16 decoder test for now
|
2020-11-06 13:50:04 -08:00 |
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|
mrg
|
147649e142
|
Why was single port decoder test a dual port?
|
2020-11-06 12:21:30 -08:00 |
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|
mrg
|
493c9125f1
|
Read different modules overrides for different num ports
|
2020-11-06 11:09:50 -08:00 |
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mrg
|
8be1436d51
|
Use OPTS.bitcell everywhere
|
2020-11-05 16:55:08 -08:00 |
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|
mrg
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18d2987805
|
Cleanup
|
2020-11-05 16:30:15 -08:00 |
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|
mrg
|
a40716dd48
|
Cleanup imports
|
2020-11-05 14:32:08 -08:00 |
|
|
mrg
|
0118b73eec
|
Cleanup imports
|
2020-11-05 14:31:53 -08:00 |
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mrg
|
681b3a91aa
|
Drop to debug in debug module when -d
|
2020-11-05 13:20:54 -08:00 |
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mrg
|
2c76a2680f
|
Adjust openram options.
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
|
2020-11-05 13:12:26 -08:00 |
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mrg
|
a52aac5f31
|
Add gds flatten option for Magic
|
2020-11-05 13:12:08 -08:00 |
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mrg
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ce7be7466f
|
Model as subckt for Magic too
|
2020-11-05 13:11:36 -08:00 |
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|
mrg
|
b160c4a35d
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
|
2020-11-04 14:31:42 -08:00 |
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|
mrg
|
9a38f7a5f4
|
Enable gds readonly in Magic DRC/LVS
|
2020-11-04 10:50:53 -08:00 |
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|
mrg
|
fb0b285652
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
|
2020-11-04 10:40:20 -08:00 |
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|
mrg
|
6e12d4d46c
|
Skip tri gate array test
|
2020-11-04 06:57:51 -08:00 |
|
|
Matt Guthaus
|
844b850b74
|
Fix typo in 1w_1r bitcell
|
2020-11-03 17:14:45 -08:00 |
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|
mrg
|
3315fe32ba
|
Improve nominal corner message
|
2020-11-03 16:49:49 -08:00 |
|
|
mrg
|
45cdecdea9
|
Improve error message about missing DRC/LVS tools.
|
2020-11-03 15:47:04 -08:00 |
|
|
mrg
|
6335bc3784
|
Do not drop to pdb shell when verbose
|
2020-11-03 15:46:46 -08:00 |
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|
mrg
|
29f4ee492b
|
Fix missing imports in replica bitcells.
|
2020-11-03 15:24:44 -08:00 |
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|
mrg
|
2f12c77668
|
Create single port memory config examples.
|
2020-11-03 14:42:56 -08:00 |
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|
mrg
|
fb9956fe96
|
Fix missing include
|
2020-11-03 13:50:45 -08:00 |
|
|
mrg
|
d209e8d9a3
|
Disable perimeter pins for now
|
2020-11-03 13:35:34 -08:00 |
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|
mrg
|
1de545fc8e
|
Fix row and col cap custom names by adding default.
|
2020-11-03 13:32:15 -08:00 |
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|
mrg
|
29ac541b28
|
Refactor dynamic cell name to utilize base class
|
2020-11-03 13:18:46 -08:00 |
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|
mrg
|
a128e0501e
|
Use cell_name in col and row caps too.
|
2020-11-03 12:10:18 -08:00 |
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|
mrg
|
1890385be1
|
Use custom cells when needed.
|
2020-11-03 11:58:25 -08:00 |
|
|
mrg
|
87419bd640
|
Fix bitcell and pbitcell with different cell names
|
2020-11-03 11:30:40 -08:00 |
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|
mrg
|
cb3e9517bb
|
Use cell_properties to override cell names
|
2020-11-03 07:06:01 -08:00 |
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|
mrg
|
da721a677d
|
Remove EOL whitespace globally
|
2020-11-03 06:29:17 -08:00 |
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|
mrg
|
8c4584daa1
|
Missing import fix.
|
2020-11-03 06:09:42 -08:00 |
|
|
mrg
|
aec5865d71
|
Fix base class error
|
2020-11-02 17:41:14 -08:00 |
|
|
mrg
|
f9787eb878
|
Use bitcell_base for all bitcells. Fix missing setup_bitcell call
|
2020-11-02 17:00:15 -08:00 |
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|
mrg
|
fa89b73ef8
|
PR from mithro + other changable GDS file names
|
2020-11-02 16:00:16 -08:00 |
|
|
mrg
|
1caecf5a69
|
Undo version and traceback
|
2020-11-02 10:44:49 -08:00 |
|
 Tim 'mithro' Ansell
|
bb164d915d
|
Allow overriding the cell size layer name.
|
2020-11-02 10:03:52 -08:00 |
|
|
Tim 'mithro' Ansell
|
232f754c73
|
Adding traceback printing to tech file import.
|
2020-11-02 09:52:00 -08:00 |
|
|
Tim 'mithro' Ansell
|
95d77119c7
|
Add caches to GDS related functions in utils.py
* Cache the GDS reader.
* Cache the properties (size / pins / etc) measured from the GDS files.
Signed-off-by: Tim 'mithro' Ansell <[email protected]>
|
2020-11-02 09:52:00 -08:00 |
|
|
Tim 'mithro' Ansell
|
6514bcb4c1
|
Use default bitcell name if one isn't provided.
Signed-off-by: Tim 'mithro' Ansell <[email protected]>
|
2020-11-02 09:52:00 -08:00 |
|
|
Tim 'mithro' Ansell
|
5c1250191c
|
Fixup the bitcell.py to make subclassing work.
Read in the GDS properties inside the __init__ method.
Signed-off-by: Tim 'mithro' Ansell <[email protected]>
|
2020-11-02 09:51:54 -08:00 |
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|
mrg
|
029f655c1b
|
Merge remote-tracking branch 'private/dev' into dev
|
2020-10-30 16:01:38 -07:00 |
|
|
mrg
|
bd9bac6635
|
Fixed nominal_corner_only parameter.
|
2020-10-30 15:52:07 -07:00 |
|
|
mrg
|
da9ed5494c
|
Merge remote-tracking branch 'private/dev' into dev
|
2020-10-29 17:46:33 -07:00 |
|
|
mrg
|
857f5cb136
|
Fix copy pasta: decoder to predecode
|
2020-10-28 15:46:10 -07:00 |
|
|
mrg
|
ae0f4fe682
|
Fix spice model bin parameter error
|
2020-10-28 10:39:54 -07:00 |
|
|
mrg
|
00cb8a28d9
|
Fix supply layer query
|
2020-10-28 10:36:13 -07:00 |
|
|
mrg
|
f6c5f48b4c
|
Default channel route is true
|
2020-10-28 10:31:05 -07:00 |
|