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base
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Default channel route is true
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2020-10-28 10:31:05 -07:00 |
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bitcells
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Add ptx cell properties
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2020-10-28 09:54:15 -07:00 |
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characterizer
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Require either device models or device library. Remove sky130 flag.
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2020-10-23 14:07:26 -07:00 |
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custom
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move sky130 specific stuff to tech module lib
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2020-10-13 04:48:10 -07:00 |
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datasheet
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Convert capital names to lower case for consistency
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2019-08-21 13:45:34 -07:00 |
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drc
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PEP8 cleanup
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2020-04-15 11:24:28 -07:00 |
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example_configs
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Remove extraneous config files.
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2020-10-23 13:56:27 -07:00 |
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gdsMill
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Search all shapes for boundary rather than specify structure
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2020-10-08 14:04:19 -07:00 |
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modules
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Fix supply layer query
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2020-10-28 10:36:13 -07:00 |
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pgates
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Fix spice model bin parameter error
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2020-10-28 10:39:54 -07:00 |
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riscv
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single port progess
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2020-09-14 18:11:38 -07:00 |
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router
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Names in skiptests changed. Reduce grid router verbosity.
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2020-10-23 09:22:59 -07:00 |
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sram
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Allow 16-way column mux
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2020-10-06 16:27:02 -07:00 |
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tests
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Names in skiptests changed. Reduce grid router verbosity.
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2020-10-23 09:22:59 -07:00 |
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verify
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Initial pex sram test.
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2020-10-02 13:32:52 -07:00 |
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Makefile
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Clean up Makefile for unit tests
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2018-12-05 12:58:10 -08:00 |
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debug.py
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DRC/LVS and errors fixes.
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2020-06-30 07:16:05 -07:00 |
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gen_stimulus.py
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Fixed errors in extra rows characterization
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2020-03-22 20:54:49 +00:00 |
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globals.py
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Don't use single slew for nominal corner
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2020-10-16 16:51:28 -07:00 |
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openram.py
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Add words_per_row and others in config file.
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2020-07-13 12:37:56 -07:00 |
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options.py
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Add load/slew scale option to config files
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2020-10-16 13:52:36 -07:00 |
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run_profile.sh
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Convert pin map to a set for faster membership.
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2019-04-01 15:45:44 -07:00 |
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sram_factory.py
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Auto-generate port dependent cell names.
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2020-06-05 15:09:22 -07:00 |
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view_profile.py
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Remove some flake8 errors/warnings.
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2019-10-02 23:26:02 +00:00 |
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