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OpenRAM
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149 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low 8b33cb519f Merge branch 'dev' into custom_mod 2020-04-03 17:05:56 -07:00
mrg 2850b9efb5 Don't force check in lib characterization. PEP8 formatting. 2020-04-02 12:52:42 -07:00
mrg 67de7efd49 Fix syntax error. No DRC/LVS in netlist only mode. 2020-04-02 11:31:28 -07:00
mrg a9d3548be1 Refactor drc/lvs error output 2020-04-01 15:54:06 -07:00
Jesse Cirimelli-Low 6e2a5d7a1a set sram output cap in characterizer to be 4x dff input cap 2020-04-01 04:24:43 -07:00
Aditi Sinha a5afbfe0aa Fixed errors in extra rows characterization 2020-03-22 20:54:49 +00:00
Hunter Nichols df2f981a34 Adds checks to prevent characterization of redundant corners. 2020-02-19 15:59:26 -08:00
Matt Guthaus 46c2cbd2d9 Check nominal_corner_only in new corner creation routine 2019-11-29 14:47:02 -08:00
Matt Guthaus bedae87315 Only use max/min and typical corner 2019-11-29 13:31:44 -08:00
jsowash 496a9919b8 Added wmask as a type group to .lib. 2019-09-04 09:45:11 -07:00
jsowash 452cc5e443 Added wmask to lib.py. 2019-09-04 09:29:45 -07:00
Matt Guthaus d0f04405a6 Convert capital names to lower case for consistency 2019-08-21 13:45:34 -07:00
Matt d22d7de195 Reapply jsowash update without spice model file 2019-06-24 08:59:58 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Hunter Nichols ddeb40c9bf Added lib test which generates multiple corner models. Only does process currently. 2019-03-04 16:27:10 -08:00
Matt Guthaus 583dc4410b Revert bus bits back into pins 2019-02-22 16:22:27 -08:00
Jennifer Eve Sowash 1249dcc34d Merge branch 'dev' into pdriver 2019-02-20 13:00:58 -08:00
Jennifer Eve Sowash 6d3a29328c Fixed a bug with corner_name in lib.py remaining static. 2019-02-20 12:59:40 -08:00
Jesse Cirimelli-Low e3ff9b53e9 fixed area not being found 2019-02-14 07:01:35 -08:00
Jesse Cirimelli-Low 6cde6beafa added documetation to functions 2019-02-07 06:33:39 -08:00
Jesse Cirimelli-Low e131af2cc3 power added to datasheet (finally) 2019-02-06 20:31:22 -08:00
Jesse Cirimelli-Low c22025839c datasheet now indicates if analytical or characterizer is used 2019-01-31 08:28:51 -08:00
Jesse Cirimelli-Low 21868e1b60 removed expanded process names from corners 2019-01-31 08:09:00 -08:00
Jesse Cirimelli-Low ed901aba5f changed datetime to date 2019-01-28 10:29:27 -08:00
Jesse Cirimelli-Low 0556b86424 html datasheet no longer dependeds on sram 2019-01-16 14:52:01 -08:00
Matt Guthaus a7dd62b0e5 falling_edge not negative_edge 2019-01-11 15:17:27 -08:00
Matt Guthaus f0ab155172 Change dout to negative clock edge relative 2019-01-11 09:51:05 -08:00
Matt Guthaus 94a6cbc28b Remove extra bracket in pin blokc 2019-01-09 13:44:25 -08:00
Matt Guthaus 7e635d02be Remove indices from pins in lib file 2019-01-09 12:00:00 -08:00
Jesse Cirimelli-Low 6acc8c8902 removed print debug statement 2019-01-03 13:41:25 -08:00
Jesse Cirimelli-Low 53b7e46db4 fixed bug where retrieving git id would fail depending on cwd 2019-01-03 12:28:29 -08:00
Jesse Cirimelli-Low c69e5fdb18 added compile time to datasheet 2019-01-02 10:30:03 -08:00
Jesse Cirimelli-Low cc27736a45 moved DRC and LVS error reports to datasheet.info from datasheet.py 2019-01-02 10:14:45 -08:00
Jesse Cirimelli-Low cd0e763895 moved system call to datasheet.info generator 2018-12-05 17:35:35 -08:00
Jesse Cirimelli-Low 7e475b376e switch to git rev-parse solution for id parsing 2018-12-05 14:58:37 -08:00
Jesse Cirimelli-Low 7a20420030 get ORIG_HEAD with pre-commit hook 2018-12-05 13:38:09 -08:00
Jesse Cirimelli-Low 5646660765 added git id to datasheet 2018-12-03 10:53:50 -08:00
Jesse Cirimelli-Low 5c4ee911aa added another VLSI logo and fixed control port numbering 2018-11-11 07:22:13 -08:00
Jesse Cirimelli-Low 4ba07e4b94 Complete rewrite of parser, all ports (except clock) added on multiport sheets 2018-11-10 20:23:26 -08:00
Jesse Cirimelli-Low 62f8d26ec6 Merge branch 'dev' into datasheet_gen 2018-11-10 10:58:35 -08:00
Jesse Cirimelli-Low d6c0247ff2 added area to datasheet 2018-11-08 21:30:17 -08:00
Matt Guthaus 71177d0b70 Fixed small bugs with new port index stuff and layout. 2018-11-08 17:40:22 -08:00
Jesse Cirimelli-Low fe196c23a9 added FF timing information 2018-10-30 22:32:19 -07:00
Jesse Cirimelli-Low 2da90c4b6a fixed double counting of characterization tuple permutations 2018-10-27 12:04:10 -07:00
Hunter Nichols 98a00f985b Changed the analytical delay model to accept multiport options. Little substance to the values generated. 2018-10-26 00:08:13 -07:00
Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell. 2018-10-26 00:08:12 -07:00
Hunter Nichols da1b003d10 Fixed multiport lib files not generating the correct number of signals. Move setup time from DOUT to DIN in lib file. Altered golden files with these changes. 2018-10-24 00:17:08 -07:00
Hunter Nichols 016604f846 Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
Hunter Nichols 53cb4e7f5e Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working. 2018-10-22 23:33:01 -07:00
Jesse Cirimelli-Low ab6afb7ca8 fixed html typos, added logo, added placeholder timing and current, began ports section 2018-10-17 19:27:09 -07:00
Matt Guthaus 5d6944953b Fix char_result rename collision 2018-10-17 09:38:26 -07:00
Michael Timothy Grimes a27cdb4fbc Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-17 07:32:03 -07:00
Jesse Cirimelli-Low afba54a22d added analytical model support, added proper output with sram.py 2018-10-12 13:22:12 -07:00
Jesse Cirimelli-Low fa979e2d34 initial stages of html documentation generation 2018-10-06 21:15:54 -07:00
Hunter Nichols 371a57339f Fixed bugs to allow characterization of multiple read ports. Improved some debug messages. 2018-10-04 14:09:09 -07:00
Hunter Nichols 4586ed343f Edited lib to support port indexing. Edited tests in reaction to name dict name changes. Cleaned up measurement value generation in delay. 2018-10-04 14:04:08 -07:00
Hunter Nichols 91bbc556e8 Cleaned up control logic cycle creation in delay.py. Fixed bug which caused input data to be determined by the read ports. 2018-09-10 22:06:50 -07:00
Hunter Nichols da6843af5b Changed power logic in lib file writing. Syntax incorrect still for multiport. To be changed when top-level is done. 2018-09-10 19:33:59 -07:00
Hunter Nichols dd22f9acd5 Fixed issues with analytical sram test. Changed syntax errors in golden lib file. 2018-09-06 17:01:10 -07:00
Hunter Nichols 66c4782408 Fixed several syntax error regarding some multiport naming. Currently in debug mode. 2018-09-06 00:25:02 -07:00
Hunter Nichols ad235c02c6 Added debug code which skips characterization and goes straight to writing the lib. Fixed some syntax issues in the lib file. 2018-09-05 23:27:13 -07:00
Hunter Nichols 3bde83bdbe Added initial structure changes to lib. Crashes when writing to lib file. 2018-09-04 00:43:44 -07:00
Hunter Nichols 60088c2dfb Added changes to lib to allow the default to run. Will crash with multiport options. 2018-08-31 00:42:56 -07:00
Hunter Nichols 5989a3c952 Expanded run_delay_stimulas to multiport. Bug Fixes as well. 2018-08-30 17:08:34 -07:00
Hunter Nichols 4b515fe1ac Changed create_test_cycles to have targeted ports for characterization rather than all ports always. 2018-08-29 17:16:11 -07:00
Hunter Nichols 775fe7b57c Fixed measure statement stating times. This commit crashes if there are no readwrite ports. 2018-08-29 15:13:31 -07:00
Hunter Nichols 8fad81ff1e Changed delay measures to add additional measure based on # of ports. Measure times are not correct yet. 2018-08-29 00:43:27 -07:00
Hunter Nichols fa8434e5f0 Added debug checks for unsupported port options. 2018-08-28 13:01:35 -07:00
Hunter Nichols bd763fa1e3 Fixed naming issue between sram instance and PWL in stimulus 2018-08-28 12:09:02 -07:00
Matt Guthaus bc67ad5ead Fixed timing to be measured from positive clock edge since 
reading a 1 will be the precharge time.
Started modifying the lib file for DIN and DOUT ports, but did not
check the syntax yet.
 2018-07-26 13:58:50 -07:00
Matt Guthaus b88947ef5c Pass the sram design to lib instead of the sram wrapper 2018-07-18 11:51:42 -07:00
Matt Guthaus 0701fceb0b Use sram rather than new meta-sram class in the characterizer for delay 2018-07-18 10:39:29 -07:00
Matt Guthaus a2d8d16c7a Split DATA into DIN and DOUT in characterizer 2018-07-11 14:19:09 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
mguthaus f3efb5fb50 Fixed leakage and power unit test results. 2018-02-23 15:20:52 -08:00
Matt Guthaus d88ff01792 Change default operating conditions to OC 2018-02-23 13:38:55 -08:00
Matt Guthaus 29aa6002e6 Make period into p instead of remove it. Changes file names... 2018-02-23 12:50:02 -08:00
Matt Guthaus 9d1f31467e Move internal power to clock pin. Differentiate leakge power when CSb is high. 2018-02-23 12:21:32 -08:00
Matt Guthaus fcacd46866 UPdate tests with new delay and slew names and leakage power. 2018-02-21 15:45:49 -08:00
Matt Guthaus 4b9ea66a42 Change names of variables to indicate transistions for clarity. 2018-02-21 15:13:46 -08:00
Matt Guthaus 7d2f4386e2 Include leakage of non-trimmed array. Back out leakage of trimmed, add back leakage of nontrimmed. Reorgs simulation of delay and power a bit. 2018-02-21 13:38:43 -08:00
Matt Guthaus 4dd075c7b7 Add V and C to names of lib files. 2018-02-11 16:34:32 -08:00
Matt Guthaus f86985821a Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated. 2018-02-09 15:33:03 -08:00
Matt Guthaus 17716191c1 Clean up time statements in openram output 2018-02-08 13:11:18 -08:00
Matt Guthaus 5c4999d4cc Move delay-specific stimulus commands to delay.py. Keep stimuli.py generic. 2018-02-07 12:58:47 -08:00
Matt Guthaus 941094ce31 Return slews to 10-90 and 90-10 so I don't have to re-hardcode the results in unit tests. 2018-02-05 15:21:53 -08:00
Matt Guthaus a8e1abdce8 Use method=gear for ngspice to improve convergence. Split TD for trig and targ in measure statements. Start waiting for clk neg edge trigger at clk pos edge. 2018-02-05 11:36:46 -08:00
Matt Guthaus 88740c107f Improve global and code structure using modules. 
Comment and reorganize globals.py
Tests consistently use globals module for OPTions.
Add characterizer as module support.
Modify unit tests to reload new characterizer for ngspice/hspice.
Enable relative and absolute config file arguments so you can run
openram from anywhere on any config file.
 2017-11-16 13:52:58 -08:00
Matt Guthaus 29c5ab48f0 Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
Matt Guthaus 95f1a24f72 Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
Matt Guthaus 20d8c0bc45 Improved characterizer. 2017-07-06 08:42:25 -07:00
Matt Guthaus 34e180b901 Analytical delay model from Bin Wu. Unit test not passing. 2017-05-30 12:50:07 -07:00
mguthaus bd7958be28 Fixed format test. It was not performing checks due to moving of OPENRAM_HOME. Fixed some tabs and print statements. 2017-04-24 11:55:11 -07:00
Matt Guthaus 841532a52f Change characterizer to be one data structure. Add approximate diff for lib file. 2016-11-23 17:18:48 -08:00
Samira Ataei 233acc3fcc Added seprate return for power values of lib. 2016-11-20 11:16:19 -06:00
Samira Ataei d195df682d Added Power results to lib. 
Fixed min_period and min_pulse_width values.
  Updated lib golden files.
 2016-11-19 20:19:16 -06:00
Matt Guthaus f48272bde6 RELEASE 1.0 2016-11-08 09:57:35 -08:00