Version bump

Fix configure; always look for std=c++17 rather than by distro.
This backs out #606b35853b, which is believed no longer needed due to (#3881) being fixed. If this proves wrong and additional OS dependencies are needed, we should use a feature test macro so that the OS test doesn't need upkeep.
2026-10-03 08:33:21 +02:00 · 2023-01-22 11:52:21 -05:00 · 2023-01-22 09:53:55 -05:00 · 2023-01-22 09:44:50 -05:00 · 2023-01-22 08:59:06 -05:00 · 2023-01-22 10:55:03 +00:00
2354 changed files with 151633 additions and 66515 deletions
@@ -17,7 +17,7 @@ AllowShortLoopsOnASingleLine: true
 AlwaysBreakAfterDefinitionReturnType: None
 AlwaysBreakAfterReturnType: None
 AlwaysBreakBeforeMultilineStrings: false
-AlwaysBreakTemplateDeclarations: false
+AlwaysBreakTemplateDeclarations: true
 BinPackArguments: true
 BinPackParameters: true
 BraceWrapping:
@@ -56,18 +56,29 @@ DisableFormat:   false
 ExperimentalAutoDetectBinPacking: false
 FixNamespaceComments: true
 ForEachMacros:
-  - foreach
  - Q_FOREACH
  - BOOST_FOREACH
-IncludeBlocks:   Preserve
+
+# Include grouping/sorting
+SortIncludes:    true
+IncludeBlocks:   Regroup
 IncludeCategories:
-  - Regex:           '^"(llvm|llvm-c|clang|clang-c)/'
-    Priority:        2
-  - Regex:           '^(<|"(gtest|gmock|isl|json)/)'
-    Priority:        3
-  - Regex:           '.*'
-    Priority:        1
-IncludeIsMainRegex: '(Test)?$'
+  - Regex:           '"(config_build|verilated_config|verilatedos)\.h"'
+    Priority:        -1 # Sepecials before main header
+  - Regex:           '(<|")verilated.*'
+    Priority:        1 # Runtime headers
+  - Regex:           '"V3.*__gen.*\.h"'
+    Priority:        3 # Generated internal headers separately
+  - Regex:           '"V3.*"'
+    Priority:        2 # Internal header
+  - Regex:           '".*"'
+    Priority:        4 # Other non-system headers
+  - Regex:           '<[[:alnum:]_.]+>'
+    Priority:        5 # Simple system headers next
+  - Regex:           '<.*>'
+    Priority:        6 # Other system headers next
+IncludeIsMainRegex: '$'
+
 IndentCaseLabels: false
 IndentPPDirectives: None
 IndentWidth:     4
@@ -91,7 +102,6 @@ PenaltyExcessCharacter: 1000000
 PenaltyReturnTypeOnItsOwnLine: 60
 PointerAlignment: Left
 ReflowComments:  true
-SortIncludes:    false
 SortUsingDeclarations: true
 SpaceAfterCStyleCast: false
 SpaceAfterTemplateKeyword: true
@@ -1,6 +1,6 @@
 ---
 name: Bug report
-about: Something isn't working as expected, and it isn't "Unsupported." (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
+about: Use this to report that something isn't working as expected, and it isn't "Unsupported." (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
 title: ''
 labels: new
 assignees: ''
@@ -13,4 +13,6 @@ Can you attach an example that shows the issue?  (Must be openly licensed, ideal

 What 'verilator --version' are you using?  Did you try it with the git master version?

-Would you be willing to try to fix Verilator yourself with assistance?
+What OS and distribution are you using?
+
+May we assist you in trying to fix this in Verilator yourself?
@@ -1,6 +1,6 @@
 ---
 name: Feature Request
-about: Request something should be supported, or a new feature added. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
+about: Use this to request something should be supported, or a new feature added. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
 title: ''
 labels: new
 assignees: ''
@@ -13,4 +13,4 @@ What would you like added/supported?

 Can you attach an example that runs on other simulators?  (Must be openly licensed, ideally in test_regress format.)

-May we assist you in trying to fix this yourself?
+May we assist you in trying to fix this in Verilator yourself?
@@ -1,6 +1,6 @@
 ---
 name: Q and A, or Other
-about: Ask a question, not related to a specific bug or feature request. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
+about: Use this to ask a question, not related to a specific bug nor feature request. (Note our contributor agreement at https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst)
 title: ''
 labels: new
 assignees: ''
@@ -29,17 +29,24 @@ jobs:
    strategy:
      fail-fast: false
      matrix:
-        os: [ubuntu-20.04, ubuntu-18.04]
+        os: [ubuntu-22.04, ubuntu-20.04]
        compiler:
          - { cc: clang, cxx: clang++ }
          - { cc: gcc,   cxx: g++     }
        m32: [0, 1]
        exclude:
-          # Build pull requests only with ubuntu-20.04 and without m32
+          # Build pull requests only with ubuntu-22.04 and without m32
          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-18.04' || 'do-not-exclude' }}
+          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-20.04' || 'do-not-exclude' }}
          - m32: ${{ github.event_name == 'pull_request' && 1              || 'do-not-exclude' }}
-          # Build -m32 only on ubuntu-20.04
+          # Build -m32 only on ubuntu-22.04
          - {os: ubuntu-18.04, m32: 1}
+          - {os: ubuntu-20.04, m32: 1}
+        include:
+          # Build GCC 10 on ubuntu-20.04
+          - os: ubuntu-20.04
+            compiler: { cc: gcc-10, cxx: g++-10 }
+            m32: 0
    runs-on: ${{ matrix.os }}
    name: Build | ${{ matrix.os }} | ${{ matrix.compiler.cc }} ${{ matrix.m32 && '| -m32' || '' }}
    env:
@@ -54,12 +61,12 @@ jobs:
    steps:

    - name: Checkout
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
      with:
        path: repo

    - name: Cache $CCACHE_DIR
-      uses: actions/cache@v2
+      uses: actions/cache@v3
      env:
        CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache
      with:
@@ -79,7 +86,7 @@ jobs:
      run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo

    - name: Upload tar archive
-      uses: actions/upload-artifact@v2
+      uses: actions/upload-artifact@v3
      with:
        path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }}
        name: ${{ env.VERILATOR_ARCHIVE }}
@@ -90,18 +97,27 @@ jobs:
    strategy:
      fail-fast: false
      matrix:
-        os: [ubuntu-20.04, ubuntu-18.04]
+        os: [ubuntu-22.04, ubuntu-20.04]
        compiler:
          - { cc: clang, cxx: clang++ }
          - { cc: gcc,   cxx: g++     }
        m32: [0, 1]
        suite: [dist-vlt-0, dist-vlt-1, dist-vlt-2, vltmt-0, vltmt-1]
        exclude:
-          # Build pull requests only with ubuntu-20.04 and without m32
+          # Build pull requests only with ubuntu-22.04 and without m32
          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-18.04' || 'do-not-exclude' }}
+          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-20.04' || 'do-not-exclude' }}
          - m32: ${{ github.event_name == 'pull_request' && 1              || 'do-not-exclude' }}
-          # Build -m32 only on ubuntu-20.04
+          # Build -m32 only on ubuntu-22.04
          - {os: ubuntu-18.04, m32: 1}
+          - {os: ubuntu-20.04, m32: 1}
+        include:
+          # Test with GCC 10 on ubuntu-20.04 without m32
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: dist-vlt-0}
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: dist-vlt-1}
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: dist-vlt-2}
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: vltmt-0}
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: vltmt-1}
    runs-on: ${{ matrix.os }}
    name: Test | ${{ matrix.os }} | ${{ matrix.compiler.cc }} | ${{ matrix.suite }} ${{ matrix.m32 && '| -m32' || '' }}
    env:
@@ -110,13 +126,13 @@ jobs:
      CI_M32: ${{ matrix.m32 }}
      CC: ${{ matrix.compiler.cc }}
      CXX: ${{ matrix.compiler.cxx }}
-      CACHE_BASE_KEY: test-${{ matrix.os }}-${{ matrix.compiler.cc }}-m32=${{ matrix.m32 }}-${ matrix.suite }}
+      CACHE_BASE_KEY: test-${{ matrix.os }}-${{ matrix.compiler.cc }}-m32=${{ matrix.m32 }}-${{ matrix.suite }}
      CCACHE_MAXSIZE: 64M # Per build matrix entry (2160M in total)
      VERILATOR_ARCHIVE: verilator-${{ github.sha }}-${{ matrix.os }}-${{ matrix.compiler.cc }}${{ matrix.m32 && '-m32' || '' }}.tar.gz
    steps:

    - name: Download tar archive
-      uses: actions/download-artifact@v2
+      uses: actions/download-artifact@v3
      with:
        name: ${{ env.VERILATOR_ARCHIVE }}
        path: ${{ github.workspace }}
@@ -126,7 +142,7 @@ jobs:
      run: tar -x -z -f ${{ env.VERILATOR_ARCHIVE }}

    - name: Cache $CCACHE_DIR
-      uses: actions/cache@v2
+      uses: actions/cache@v3
      env:
        CACHE_KEY: ${{ env.CACHE_BASE_KEY }}-ccache
      with:
@@ -11,7 +11,7 @@ on:
 jobs:
  Test:
    name: "'docs/CONTRIBUTORS' was signed"
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-22.04
    steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v3
    - run: test_regress/t/t_dist_contributors.pl
@@ -24,14 +24,14 @@ jobs:


  Build:
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-22.04
    env:
      CI_BUILD_STAGE_NAME: build
-      CI_RUNS_ON: ubuntu-20.04
+      CI_RUNS_ON: ubuntu-22.04
    steps:

    - name: Checkout
-      uses: actions/checkout@v2
+      uses: actions/checkout@v3
      with:
        path: repo

@@ -46,7 +46,7 @@ jobs:
      run: tar --posix -c -z -f ${{ env.VERILATOR_ARCHIVE }} repo

    - name: Upload tar archive
-      uses: actions/upload-artifact@v2
+      uses: actions/upload-artifact@v3
      with:
        path: ${{ github.workspace }}/${{ env.VERILATOR_ARCHIVE }}
        name: ${{ env.VERILATOR_ARCHIVE }}
@@ -73,15 +73,15 @@ jobs:
        - 9
        include:
        - { test: dist, num: '' }
-    runs-on: ubuntu-20.04
+    runs-on: ubuntu-22.04
    name: test-${{ matrix.test }}${{ matrix.num }}
    env:
      CI_BUILD_STAGE_NAME: test
-      CI_RUNS_ON: ubuntu-20.04
+      CI_RUNS_ON: ubuntu-22.04
    steps:

    - name: Download tar archive
-      uses: actions/download-artifact@v2
+      uses: actions/download-artifact@v3
      with:
        name: ${{ env.VERILATOR_ARCHIVE }}
        path: ${{ github.workspace }}
@@ -10,16 +10,16 @@ on:

 jobs:
  format:
-    runs-on: ubuntu-20.04
-    name: Ubuntu 20.04 | format
+    runs-on: ubuntu-22.04
+    name: Ubuntu 22.04 | format
    env:
      CI_OS_NAME: linux
-      CI_RUNS_ON: ubuntu-20.04
+      CI_RUNS_ON: ubuntu-22.04
      CI_COMMIT: ${{ github.sha }}
      CI_M32: 0
    steps:
      - name: Checkout
-        uses: actions/checkout@v2
+        uses: actions/checkout@v3
        with:
          token: ${{ secrets.GITHUB_TOKEN }}
      - name: Install packages for build
@@ -27,14 +27,14 @@ jobs:
          CI_BUILD_STAGE_NAME: build
        run: |
          bash ci/ci-install.bash &&
-          sudo apt-get install clang-format-11 yapf3 &&
+          sudo apt-get install clang-format-14 yapf3 &&
          git config --global user.email "[email protected]" &&
          git config --global user.name "github action"
      - name: Format code
        run: |
          autoconf &&
          ./configure &&
-          make -j 2 format CLANGFORMAT=clang-format-11 &&
+          make -j 2 format CLANGFORMAT=clang-format-14 &&
          git status
      - name: Push
        run: |
@@ -0,0 +1,51 @@
+# DESCRIPTION: Github actions config
+# This name is key to badges in README.rst, so we use the name build
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+name: msbuild
+
+on:
+  push:
+  pull_request:
+  workflow_dispatch:
+  schedule:
+  - cron: '0 0 * * 0' # weekly
+
+env:
+  CI_OS_NAME: win
+  CI_COMMIT: ${{ github.sha }}
+  CCACHE_COMPRESS: 1
+  CCACHE_DIR: ${{ github.workspace }}/.ccache
+  CCACHE_LIMIT_MULTIPLE: 0.95
+
+defaults:
+  run:
+    working-directory: repo
+
+jobs:
+
+   windows:
+    name: run on windows
+    runs-on: windows-latest
+    steps:
+    - uses: actions/checkout@v3
+      with:
+        path: repo
+    - name: Cache $CCACHE_DIR
+      uses: actions/cache@v3
+      with:
+        path: ${{ env.CCACHE_DIR }}
+        key: msbuild-msvc-cmake
+    - name: compile
+      env:
+        WIN_FLEX_BISON: ${{ github.workspace }}/.ccache
+      run: ./ci/ci-win-compile.ps1
+    - name: test build
+      run: ./ci/ci-win-test.ps1
+    - name: Zip up repository
+      run: Compress-Archive -LiteralPath install -DestinationPath verilator.zip
+    - name: Upload zip archive
+      uses: actions/upload-artifact@v3
+      with:
+        path: ${{ github.workspace }}/repo/verilator.zip
+        name: verilator-win.zip
@@ -1,5 +1,6 @@
 \#*
 .#*
+.gdb_history
 .nfs*
 *~
 *.tidy
@@ -39,3 +40,4 @@ verilator-config-version.cmake
 **/__pycache__/*
 **/_build/*
 **/obj_dir/*
+/.vscode/
@@ -0,0 +1,123 @@
+#*****************************************************************************
+#
+# DESCRIPTION: Script for build tool cmake on both unix and windows
+#
+#*****************************************************************************
+#
+# Copyright 2003-2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+#
+#****************************************************************************/
+
+cmake_minimum_required(VERSION 3.15)
+cmake_policy(SET CMP0091 NEW) # Use MSVC_RUNTIME_LIBRARY to select the runtime
+project(Verilator
+    VERSION 5.003
+    HOMEPAGE_URL https://verilator.org
+    LANGUAGES CXX
+)
+
+option(DEBUG_AND_RELEASE_AND_COVERAGE
+    "Builds both the debug and release binaries, overriding CMAKE_BUILD_TYPE. Not supported under MSBuild.")
+
+set(PYTHON3 python)
+set(CMAKE_INSTALL_DATADIR ${CMAKE_INSTALL_PREFIX})
+include(GNUInstallDirs)
+include(CMakePackageConfigHelpers)
+include(CheckStructHasMember)
+include(ExternalProject)
+
+if (NOT WIN32)
+    message(WARNING "CMake support on Linux/OSX is experimental.")
+endif()
+
+if (MSVC)
+    if (DEFINED ENV{WIN_FLEX_BISON})
+        set(WIN_FLEX_BISON "$ENV{WIN_FLEX_BISON}")
+    endif()
+    if (EXISTS ${WIN_FLEX_BISON})
+        list(APPEND CMAKE_PREFIX_PATH ${WIN_FLEX_BISON})
+    endif()
+    if (NOT WIN_FLEX_BISON)
+        message(FATAL_ERROR "Please install https://github.com/lexxmark/winflexbison and set WIN_FLEX_BISON environment variable. Please use install cmake target after a successful build.")
+    endif()
+    set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} /std:c++20")
+else()
+    if (NOT DEFINED ENV{FLEX_INCLUDE})
+        message(FATAL_ERROR "Please set environment variable FLEX_INCLUDE to the directory containing FlexLexer.h")
+    endif()
+    set(WIN_FLEX_BISON "$ENV{FLEX_INCLUDE}")
+    if (WIN32 AND NOT MINGW)
+        set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++20")
+    endif()
+endif()
+
+find_package(BISON)
+find_package(FLEX)
+
+# Build
+#set_property(GLOBAL PROPERTY JOB_POOLS one_job=1)
+
+if (DEBUG_AND_RELEASE_AND_COVERAGE)
+    if (CMAKE_GENERATOR MATCHES "^Visual Studio ")
+        error("%Error: The DEBUG_AND_RELEASE_AND_COVERAGE option is not supported in MSBuild-based builds.")
+    endif()
+    set(saved_build_type ${CMAKE_BUILD_TYPE})
+    set(CMAKE_BUILD_TYPE Debug)
+    add_subdirectory(src build-Debug)
+    set(CMAKE_BUILD_TYPE Release)
+    add_subdirectory(src build-Release)
+    set(CMAKE_BUILD_TYPE Coverage)
+    add_subdirectory(src build-Coverage)
+    set(CMAKE_BUILD_TYPE ${saved_build_type})
+else()
+    add_subdirectory(src)
+endif()
+
+# Configuration and Installation
+
+set(PACKAGE_NAME ${PROJECT_NAME})
+set(PACKAGE_VERSION ${PROJECT_VERSION})
+
+configure_file(include/verilated_config.h.in include/verilated_config.h @ONLY)
+
+install(FILES ${CMAKE_CURRENT_BINARY_DIR}/include/verilated_config.h DESTINATION ${CMAKE_INSTALL_PREFIX}/include)
+
+configure_package_config_file(verilator-config.cmake.in verilator-config.cmake
+    INSTALL_DESTINATION ${CMAKE_INSTALL_PREFIX}
+)
+
+install(FILES ${CMAKE_CURRENT_BINARY_DIR}/verilator-config.cmake DESTINATION ${CMAKE_INSTALL_PREFIX})
+
+configure_package_config_file(verilator-config-version.cmake.in verilator-config-version.cmake
+    INSTALL_DESTINATION ${CMAKE_INSTALL_PREFIX}
+)
+
+install(FILES ${CMAKE_CURRENT_BINARY_DIR}/verilator-config-version.cmake DESTINATION ${CMAKE_INSTALL_PREFIX})
+
+foreach (program
+    verilator_gantt
+    verilator_ccache_report
+    verilator_difftree
+    verilator_profcfunc
+)
+    install(PROGRAMS bin/${program} TYPE BIN)
+endforeach()
+
+install(DIRECTORY examples TYPE DATA FILES_MATCHING
+    PATTERN "examples/*/*.[chv]*"
+    PATTERN "examples/*/Makefile*"
+    PATTERN "examples/*/CMakeLists.txt"
+)
+
+install(DIRECTORY include TYPE DATA FILES_MATCHING
+    PATTERN "include/verilated_config.h"
+    PATTERN "include/verilated.mk"
+    PATTERN "include/*.[chv]"
+    PATTERN "include/*.cpp"
+    PATTERN "include/gtkwave/*.[chv]*"
+    PATTERN "include/vltstd/*.[chv]*"
+)
@@ -0,0 +1,17 @@
+set noparent
+linelength=100
+filter=-build/c++11
+filter=-build/header_guard
+filter=-build/include_order
+filter=-build/include_subdir
+filter=-readability/inheritance
+filter=-readability/nolint
+filter=-readability/todo
+filter=-runtime/references
+filter=-whitespace/blank_line
+filter=-whitespace/empty_if_body
+filter=-whitespace/indent
+filter=-whitespace/newline
+filter=-whitespace/braces
+filter=-whitespace/parens
+filter=-whitespace/todo
@@ -8,10 +8,362 @@ The changes in each Verilator version are described below.  The
 contributors that suggested a given feature are shown in []. Thanks!


+Verilator 5.006 2022-01-22
+==========================
+
+**Minor:**
+
+* Support clocking blocks (#3674). [Krzysztof Bieganski, Antmicro Ltd]
+* Support packed structs (#3802). [Aleksander Kiryk, Antmicro Ltd]
+* Support Windows-native builds using cmake (#3814). [Kritik Bhimani]
+* Support p format for UnpackArray (#3877). [Aleksander Kiryk, Antmicro Ltd]
+* Support property calls without parenthesis (#3879) (#3893). [Ryszard Rozak, Antmicro Ltd]
+* Support import/export lists in modport (#3886). [Gökçe Aydos]
+* Support class queue equality (#3895). [Ilya Barkov]
+* Add IMPLICITSTATIC warning when a ftask/function is implicitly static (#3839). [Ryszard Rozak, Antmicro Ltd]
+* Add VL_VALUE_STRING_MAX_WORDS override (#3869). [Andrew Nolte]
+* Optimize expansion of extend operators.
+* Internal multithreading tests. [Mariusz Glebocki, et al, Antmicro Ltd]
+* Fix VPI one-time timed callbacks (#2778). [Marlon James, et al]
+* Fix initiation of function variables (#3815). [Dan Gisselquist]
+* Fix to zero possibly uninitialized bits in replications (#3815).
+* Fix crash in DFT due to width use after free (#3817) (#3820). [Jevin Sweval]
+* Fix signed/unsigned comparison compile warning (#3822). [Kamil Rakoczy]
+* Fix OS-X weak symbols with -U linker flag (#3823). [Jevin Sweval]
+* Fix wrong bit op tree optimization (#3824) (#3825). [Yutetsu TAKATSUKASA]
+* Fix self references when param class instantiated (#3833). [Ryszard Rozak, Antmicro Ltd]
+* Fix memory leak in V3Sched, etc. (#3834). [Geza Lore]
+* Fix compatibility with musl libc / Alpine Linux (#3845). [Sören Tempel]
+* Fix empty case items crash (#3851). [rporter]
+* Fix VL_CPU_RELAX on MIPS/Armel/s390/sparc (#3843) (#3891). [Kamil Rakoczy]
+* Fix module parameter name collision (#3854) (#3855). [James Shi]
+* Fix unpacked array expansion (#3861). [Joey Liu]
+* Fix signed/unsigned parameter types (#3866). [James Shi]
+* Fix chain call of abstract class constructor (#3868) (#3883). [Ilya Barkov]
+* Fix to use same std in Verilator and Verilated compile (#3881). [Kamil Rakoczy, Antmicro Ltd]
+* Fix foreach unnamedblk duplicate error (#3885). [Ilya Barkov]
+* Fix elaboration of member selected classes (#3890). [Ilya Barkov]
+* Fix mismatched widths in DFG (#3872). [Geza Lore, Yike Zhou]
+
+
+Verilator 5.004 2022-12-14
+==========================
+
+**Major:**
+
+* Support named properties (#3667). [Ryszard Rozak, Antmicro Ltd]
+* Add ENUMVALUE warning when value misused for enum (#726) (#3777) (#3783).
+* Deprecate --no-threads; use --threads 1 for single threaded (#3703). [Kamil Rakoczy, Antmicro Ltd]
+
+**Minor:**
+
+* Support std::semaphore and typed std::mailbox (#3708). [Krzysztof Bieganski, Antmicro Ltd]
+* Support 'with' in unique, unique_index, min, max in queues (#3772). [Ryszard Rozak, Antmicro Ltd]
+* Support events in VCD/FST traces (#3759). [Yves Mathieu]
+* Support foreach loops on strings (#3760). [Ryszard Rozak, Antmicro Ltd]
+* Support member selects in with clauses (#3775). [Ryszard Rozak, Antmicro Ltd]
+* Support super.new calls (#3789). [Ryszard Rozak, Antmicro Ltd]
+* Support randcase.
+* Support pre_randomize and post_randomize.
+* Support $timeunit and $timeprecision.
+* Support assignment expressions.
+* Change ENDLABEL from warning into an error.
+* Internal AST improvements, also affect XML format (#3721). [Geza Lore]
+* Deprecate verilated_fst_sc.cpp and verilated_vcd_sc.cpp.
+* Disable stack size limit (#3706) (#3751). [Mariusz Glebocki]
+* Add error when use --exe with --lib-create (#3785). [Yinan Xu]
+* Fix jump handling in do while loops (#3731). [Ryszard Rozak, Antmicro Ltd]
+* Fix 'with' clause handling in functions (#3739). [Ryszard Rozak, Antmicro Ltd]
+* Fix CONTEXT compile error on MingW (#3741). [William D. Jones]
+* Fix MSVC compiler errors (#3742) (#3746). [Kritik Bhimani]
+* Fix CASEINCOMPLETE when covers all enum values (#3745) (#3782). [Guy-Armand Kamendje]
+* Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd]
+* Fix timing control in while-break loops (#3733) (#3769). [Ryszard Rozak, Antmicro Ltd]
+* Fix return in constructors (#3734). [Ryszard Rozak, Antmicro Ltd]
+* Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon]
+* Fix tracing parameters overridden with -G (#3723). [Iztok Jeras]
+* Fix folding of LogAnd with non-bool operands (#3726). [Geza Lore]
+* Fix DFG optimization issues (#3740) (#3771). [Geza Lore]
+* Fix pre/postincrement operations (#3744) (#3756). [Ryszard Rozak, Antmicro Ltd]
+* Fix cross-compile for MingW, Arm and RISC-V (#3752). [Miodrag Milanović]
+* Fix $unit as base package for other packages (#3755). [Ryszard Rozak, Antmicro Ltd]
+* Fix make jobserver with submakes (#3758). [Gus Smith]
+* Fix to escape VERILATOR_ROOT file paths (#3764) (#3765). [Jiacheng Qian]
+* Fix empty string literals converting to string types (#3774). [miree]
+* Fix to remove $date from .vcd files (#3779). [Larry Doolittle]
+* Fix missing user objects in --lib-create mode (#3780) (#3784). [Yinan Xu]
+* Fix non-blocking assignments in forks (#3781) (#3800). [Krzysztof Bieganski, Antmicro Ltd]
+* Fix forks without any delayed statements (#3792) (#3801). [Krzysztof Bieganski, Antmicro Ltd]
+* Fix internal error in bit op tree optimization (#3793). [Yutetsu TAKATSUKASA]
+* Fix lint_off EOFNEWLINE in .vlt files (#3796). [Andrew Nolte]
+* Fix wait 0.
+* Fix comparing ranged slices of unpacked arrays.
+
+
+Verilator 5.002 2022-10-29
+==========================
+
+**Major:**
+
+* This is a major new release.
+* Require C++20 for the new --timing features. Upgrading to a C++20 or
+  newer compiler is strongly recommended.
+* Support the Active and NBA scheduling regions as defined by the
+  SystemVerilog standard (IEEE 1800-2017 chapter 4). This means all generated
+  clocks are now simulated correctly (#3278, #3384). [Geza Lore, Shunyao CAD]
+* Support timing controls (delays, event controls in any location, wait
+  statements) and forks. [Krzysztof Bieganski, Antmicro Ltd]
+  This may require adding --timing or --no-timing. See docs for details.
+* Introduce a new combinational logic optimizer (DFG), that can yield
+  significant performance improvements on some designs. [Geza Lore, Shunyao CAD]
+* Add --binary option as alias of --main --exe --build --timing (#3625).
+  For designs where C++ was only used to make a simple no-I/O testbench, we
+  recommend abandoning that C++, and instead letting Verilator build it
+  with --binary (or --main).
+
+**Minor:**
+
+* Split UNUSED warning into genvar, param, and signal warnings (#3607). [Topa Topino]
+* Support standalone 'this' in classes (#2594) (#3248) (#3675). [Arkadiusz Kozdra, Antmicro Ltd]
+* Support tristate select/extend (#3604). [Ryszard Rozak, Antmicro Ltd>
+* Support linting for top module interfaces (#3635). [Kanad Kanhere]
+* Support virtual interfaces (#3654). [Arkadiusz Kozdra, Antmicro Ltd]
+* Support class type params without defaults (#3693). [Krzysztof Bieganski, Antmicro Ltd]
+* Support empty generate_regions (#3695). [mpb27]
+* Support access to constructs inside type parameters (#3702). [Arkadiusz Kozdra, Antmicro Ltd]
+* Add --dump-tree-dot to enable dumping Ast Tree .dot files (#3636). [Marcel Chang]
+* Add --get-supported to determine what features are in Verilator.
+* Add error on real edge event control.
+* Fix false LATCH warning on 'unique if' (#3088). [Rachit Nigam]
+* Fix cell assigning integer array parameters (#3299). [Michael Platzer]
+* Fix LSB error on --hierarchical submodules (#3539). [danbone]
+* Fix $display of fixed-width numbers (#3565). [Iztok Jeras]
+* Fix foreach and pre/post increment in functions (#3613). [Nandu Raj]
+* Fix linker errors in user-facing timing functions (#3657). [Krzysztof Bieganski, Antmicro Ltd]
+* Fix null access on optimized-out fork statements (#3658). [Krzysztof Bieganski, Antmicro Ltd]
+* Fix VPI inline module naming mismatch (#3690) (#3694). [Jiuyang Liu]
+* Fix deadlock in timeprecision when using SystemC (#3707). [Kamil Rakoczy, Antmicro Ltd]
+* Fix width mismatch on inside operator (#3714). [Alex Torregrosa]
+
+
+Verilator 4.228 2022-10-01
+==========================
+
+**Announcement:**
+
+* The next release is anticipated to premiere Verilator Version 5.  Please
+  consider beta-testing the github 'develop-v5' branch, which will soon
+  merge into the github 'master' branch (#3383).
+
+**Minor:**
+
+* Support some IEEE signal strengths (#3601) (#3629). [Ryszard Rozak, Antmicro Ltd]
+* Add --main to generate main() C++ (previously was experimental only).
+* Add --build-jobs, and rework arguments for -j (#3623). [Kamil Rakoczy]
+* Rename --bin to --build-dep-bin.
+* Rename debug flags --dumpi-tree, --dumpi-graph, etc. [Geza Lore]
+* Fix thread safety in SystemC VL_ASSIGN_SBW/WSB (#3494) (#3513). [Mladen Slijepcevic]
+* Fix crash in gate optimization of circular logic (#3543). [Bill Flynn]
+* Fix arguments in non-static method call (#3547) (#3582). [Gustav Svensk]
+* Fix default --mod-prefix when --prefix is repeated (#3603). [Geza Lore]
+* Fix calling trace() after open() segfault (#3610) (#3627). [Yu-Sheng Lin]
+* Fix typedef'ed class conversion to Boolean (#3616). [Aleksander Kiryk]
+* Fix Verilation speed when disabled warnings (#3632). [Kamil Rakoczy, Antmicro Ltd]
+
+
+Verilator 4.226 2022-08-31
+==========================
+
+**Minor:**
+
+* Add --future0 and --future1 options.
+* Support class parameters (#2231) (#3541). [Arkadiusz Kozdra, Antmicro Ltd]
+* Support wildcard index associative arrays (#3501). [Arkadiusz Kozdra, Antmicro Ltd]
+* Support negated properties (#3572). [Aleksander Kiryk]
+* Support $test$plusargs(expr) (#3489).
+* Rename trace rolloverSize() (#3570).
+* Improve Verilation speed with --threads on large designs. [Geza Lore]
+* Improve Verilation memory by reducing V3Number (#3521). [Mariusz Glebocki, Antmicro Ltd]
+* Fix struct pattern assignment (#2328) (#3517). [Mostafa Gamal]
+* Fix public combo propagation issues (#2905). [Todd Strader]
+* Fix incorrect tristate logic (#3399) [shareefj, Vighnesh Iyer]
+* Fix incorrect bit op tree optimization (#3470). [algrobman]
+* Fix bisonpre for MSYS2 (#3471).
+* Fix max memory usage (#3483). [Kamil Rakoczy, Antmicro Ltd]
+* Fix empty string arguments to display (#3484). [Grulfen]
+* Fix table optimizing away display (#3488). [Stefan Post]
+* Fix unique_ptr memory header for MinGW64 (#3493).
+* Fix $dump system task with --output-split-cfuncs (#3495) (#3497). [Varun Koyyalagunta]
+* Fix wrong bit op tree optimization (#3509). [Nathan Graybeal]
+* Fix nested default assignment for struct pattern (#3511) (#3524). [Mostafa Gamal]
+* Fix sformat string incorrectly cleared (#3515) (#3519). [Gustav Svensk]
+* Fix segfault exporting non-existent package (#3535).
+* Fix void-cast queue pop_front or pop_back (#3542) (#3364). [Drew Ranck]
+* Fix case statement comparing string literal (#3544). [Gustav Svensk]
+* Fix === with some tristate constants (#3551). [Ryszard Rozak, Antmicro Ltd]
+* Fix converting classes to string (#3552). [Arkadiusz Kozdra, Antmicro Ltd]
+* Fix --hierarchical with order-based pin connections (#3583) (#3585). [Kelin9298]
+
+
+Verilator 4.224 2022-06-19
+==========================
+
+**Major:**
+
+* VCD tracing is now parallelized with --threads (#3449). [Geza Lore, Shunyao CAD]
+
+**Minor:**
+
+* Add -f<optimization> options to replace -O<letter> options (#3436).
+* Changed --no-merge-const-pool to -fno-merge-const-pool (#3436).
+* Changed --no-decoration to remove output whitespace (#3460). [Kamil Rakoczy]
+* Support compile time trace signal selection with tracing_on/off (#3323). [Shunyao CAD]
+* Support non-ANSI interface port declarations (#3439). [Geza Lore, Shunyao CAD]
+* Support concat assignment to packed array (#3446).
+* Improve conditional merging optimization (#3125). [Geza Lore, Shunyao CAD]
+* Define VM_TRACE_VCD when tracing in VCD format. [Geza Lore, Shunyao CAD]
+* Add assert when VerilatedContext is mis-deleted (#3121). [Rupert Swarbrick]
+* Internal prep work towards timing control. [Krzysztof Bieganski, Antmicro Ltd]
+* Fix hang with large case statement optimization (#3405). [Mike Urbach]
+* Fix UNOPTFLAT warning from initial static var (#3406). [Kamil Rakoczy]
+* Fix compile error when enable VL_LEAK_CHECKS (#3411). [HungMingWu]
+* Fix cmake rules to support higher-level targets (#3377) (#3386). [Martin Stadler]
+* Fix BLKANDNBLK on $readmem/$writemem (#3379). [Alex Solomatnikov]
+* Fix 'with' operator with type casting (#3387). [xiak95]
+* Fix incorrect conditional merging (#3409). [Raynard Qiao]
+* Fix passing VL_TRACE_FST_WRITER_THREAD in CMake build. [Geza Lore, Shunyao CAD]
+* Fix compile error under strict C++11 mode (#3463). [Kevin Kiningham]
+* Fix public unpacked input ports (#3465). [Todd Strader]
+
+
+Verilator 4.222 2022-05-02
+==========================
+
+**Minor:**
+
+* Split --prof-threads into --prof-exec and --prof-pgo (#3365). [Geza Lore, Shunyao CAD]
+* Deprecate 'vluint64_t' and similar types (#3255).
+* Raise error on assignment to const in initial blocks. [Geza Lore, Shunyao CAD]
+* Issue INITIALDLY/COMBDLY/BLKSEQ warnings consistent with Verilator execution. [Geza Lore, Shunyao CAD]
+* Support LoongArch ISA multithreading (#3353) (#3354). [Xi Zhang]
+* Fix MSVC localtime_s (#3124).
+* Fix Bison 3.8.2 error (#3366). [elike-ypq]
+* Fix rare bug in -Oz (V3Localize) (#3286). [Geza Lore, Shunyao CAD]
+* Fix tracing interfaces inside interfaces (#3309). [Kevin Millis]
+* Fix filenames with dots overwriting debug .vpp files (#3373).
+* Fix including VK_USER_OBJS in make library (#3370) (#3382). [Julien Margetts]
+* Fix hang in generate symbol references (#3391) (#3398). [Yoda Lee]
+* Fix missing #include <memory> (#3392). [Aliaksei Chapyzhenka]
+* Fix crash in recursive module inlining (#3393). [david-sawatzke]
+* Fix --protect-ids mangling names of library methods. [Geza Lore, Shunyao CAD]
+* Fix foreach segmentation fault (#3400). [Kamil Rakoczy]
+
+
+Verilator 4.220 2022-03-12
+==========================
+
+**Minor:**
+
+* Removed the deprecated lint_off flag -msg; use -rule instead.
+* Removed the deprecated "fl" attribute in XML output; use "loc" attribute instead.
+* Suppress WIDTH warning on negate using carry bit (#3295). [Peter Monsson]
+* Add trace dumpvars() call for selective runtime tracing (#3322). [Shunyao CAD]
+* Add VERILATOR_VERSION_INTEGER for determining API (#3343). [Larry Doolittle]
+* Improve various V3Combine algorithm details (#3328). [Yutetsu TAKATSUKASA]
+* Improve various V3Order algorithm details. [Geza Lore]
+* Fix MacOS arm64 build (#3285) (#3291). [Guokai Chen]
+* Fix signed number operation (#3294) (#3308). [Raynard Qiao]
+* Fix FST traces to include vector range (#3296) (#3297). [Jamie Iles]
+* Fix skipping public enum values with four-state values (#3303).
+* Fix $readmem file not found to be warning not error (#3310). [Alexander Grobman]
+* Fix class stringification on wide arrays (#3312). [Iru Cai]
+* Fix $fscanf etc to return -1 on EOF (#3313). [Jose Tejada]
+* Fix public function arguments that are arrayed (#3316). [pawel256]
+* Fix unnamedblk error on foreach (#3321). [Aliaksei Chapyzhenka]
+* Fix crash in recursive module inlining (#3324). [Larry Doolittle]
+* Fix VL_RESTORER behavior on passing a lvalue reference (#3326). [HungMingWu]
+* Fix compile error with --trace-fst --sc (#3332). [leavinel]
+* Fix cast to array types (#3333). [Todd Strader]
+* Fix Vdeeptemp error with --threads and --compiler clang (#3338). [Per Karlsson]
+
+
+Verilator 4.218 2022-01-17
+==========================
+
+**Major:**
+
+* Primary inputs and outputs (VL_INW/VL_OUTW) now use VlWide type.
+  In general this should be backward compatible, but may lead to some
+  wrapper code needing changes.
+* Option --cdc is deprecated and is planned for removal,
+  file a bug if this is still being used.
+
+**Minor:**
+
+* Support class static members (#2233).
+* Support force/release (#2431) (#2593). [Shunyao CAD]
+* Add 'forceable' attribute to allow forcing from C++. (#3272). [Geza Lore, Shunyao CAD]
+* Support lower dimension looping in foreach loops (#3172). [Ehab Ibrahim]
+* Support up to 64 bit enums for .next/.prev/.name (#3244). [Alexander Grobman]
+* Reduce .rodata footprint of trace initialization (#3250). [Geza Lore, Shunyao CAD]
+* Support FST tracing in hierarchical Verilation (#3251). [Yutetsu TAKATSUKASA]
+* Use C++11 standard types for MacOS portability (#3254) (#3257). [Adrien Le Masle]
+* Fix make support for BSD ar (#2999) (#3256). [Julie Schwartz]
+* Fix bad ending address on $readmem (#3205). [Julie Schwartz]
+* Fix MSWIN compile error (#2681). [Unai Martinez-Corral]
+* Fix break under foreach loop (#3230).
+* Fix VL_STREAML_FAST_QQI with 64 bit left-hand-side (#3232) (#3235). [Adrien Le Masle]
+* Fix $sformat of inputs/outputs (#3236). [Adrien Le Masle]
+* Fix associative array first method as statement (#3228). [Adrien Le Masle]
+* Fix associative array foreach loop (#3229).
+* Fix $fclose not accepting expressions (#3237). [Julie Schwartz]
+* Fix $random not updating seed (#3238). [Julie Schwartz]
+* Fix top level param overwrite when package has same param (#3241) (#3247). [Adrien Le Masle]
+* Fix spurious UNUSED by ignoring inout pin connections (#3242). [Julie Schwartz]
+* Fix splitting of _eval and other top level functions. [Geza Lore, Shunyao CAD]
+* Fix internal error by inout port (#3258). [Yutetsu TAKATSUKASA]
+* Fix GCC 11 compile error (#3273). [HungMingWu]
+
+
+Verilator 4.216 2021-12-05
+==========================
+
+**Major:**
+
+* Add --lib-create, similar to --protect-lib but without protections.
+* Support tracing through --hierarchical/--lib-create libraries (#3200).
+
+**Minor:**
+
+* Internal code cleanups and improvements. [Geza Lore]
+* Improve --thread Verilation-time performance.
+* Support task name in $display %m (#3211). [Julie Schwartz]
+* Make 'bit', 'logic' and 'time' types unsigned by default. [Geza Lore]
+* Optimize $random concatenates/selects (#3114).
+* Fix array method names with parenthesis (#3181) (#3183). [Teng Huang]
+* Fix split_var assign merging (#3177) (#3179). [Yutetsu TAKATSUKASA]
+* Fix wrong bit op tree optimization (#3185). [Yutetsu TAKATSUKASA]
+* Fix some SliceSels not being constants (#3186) (#3218). [Michaël Lefebvre]
+* Fix nested generate if genblk naming (#3189). [yanx21]
+* Fix hang on recursive definition error (#3199). [Jonathan Kimmitt]
+* Fix display of signed without format (#3204). [Julie Schwartz]
+* Fix display of empty string constant (#3207) (#3215). [Julie Schwartz]
+* Fix incorrect width after and-or optimization (#3208). [Julie Schwartz]
+* Fix $fopen etc on integer arrays (#3214). [adrienlemasle]
+* Fix $size on dynamic strings (#3216).
+* Fix %0 format on $value$plusargs (#3217).
+* Fix timescale portability on Arm64 (#3222).
+
+
 Verilator 4.214 2021-10-17
 ==========================

-* Add profile-guided optmization of mtasks (#3150).
+**Major:**
+
+* Add profile-guided optimization of mtasks (#3150).
+
+**Minor:**
+
 * Verilator_gantt has removed the ASCII graphics, use the VCD output instead.
 * Verilator_gantt now shows the predicted mtask times, eval times, and additional statistics.
 * Verilator_gantt data files now include processor information, to allow later processing.
@@ -38,7 +390,7 @@ Verilator 4.212 2021-09-01
 * Fix re-evaluation of logic dependent on state set in DPI exports (#3091). [Geza Lore]
 * Support unpacked array localparams in tasks/functions (#3078). [Geza Lore]
 * Support timeunit/timeprecision in $unit.
-* Support assignment patterns as children of pins (#3041). [Krzysztof Bieganski]
+* Support assignment patterns as children of pins (#3041). [Krzysztof Bieganski, Antmicro Ltd]
 * Add --instr-count-dpi to tune assumed DPI import cost for multithreaded
  model scheduling. Default value changed to 200 (#3068). [Yinan Xu]
 * Output files are split based on the set of headers required
@@ -74,7 +426,7 @@ Verilator 4.210 2021-07-07

 * Add --prof-c to pass profiling to compiler (#3059). [Alexander Grobman]
 * Optimize a lot more model variables into function locals (#3027). [Geza Lore]
-* Support middle-of-design nested topmodules (#3026). [Dan Petrisko]
+* Support middle-of-design nested top modules (#3026). [Dan Petrisko]
 * Remove deprecated --no-relative-cfuncs option (#3024). [Geza Lore]
 * Remove deprecated --inhibit-sim option (#3035). [Geza Lore]
 * Merge const static data globally into a new constant pool (#3013). [Geza Lore]
@@ -103,7 +455,7 @@ Verilator 4.204 2021-06-12
 * Prep work towards better ccache hashing/performance. [Geza Lore]
 * Fix assertion failure in bitOpTree optimization (#2891) (#2899). [Raynard Qiao]
 * Fix DPI functions not seen as vpiModule (#2893). [Todd Strader]
-* Fix bounds check in VL_SEL_IWII (#2910). [Krzysztof Bieganski]
+* Fix bounds check in VL_SEL_IWII (#2910). [Krzysztof Bieganski, Antmicro Ltd]
 * Fix slowdown in elaboration (#2911). [Nathan Graybeal]
 * Fix initialization of assoc in assoc array (#2914). [myftptoyman]
 * Fix make support for gmake 3.x (#2920) (#2921). [Philipp Wagner]
@@ -113,10 +465,10 @@ Verilator 4.204 2021-06-12
 * Fix to emit 'else if' without nesting (#2944). [Geza Lore]
 * Fix part select issues in LATCH warning (#2948) (#2938). [Julien Margetts]
 * Fix to not emit empty files with low split limits (#2961). [Geza Lore]
-* Fix merging of assignments in C++ code (#2970). [Ruper Swarbrick]
+* Fix merging of assignments in C++ code (#2970). [Rupert Swarbrick]
 * Fix unused variable warnings (#2991). [Pieter Kapsenberg]
 * Fix --protect-ids when using SV classes (#2994). [Geza Lore]
-* Fix constant function calls with uninit value (#2995). [yanx21]
+* Fix constant function calls with uninitialized value (#2995). [yanx21]
 * Fix Makefiles to support Windows EXEEXT usage (#3008). [Miodrag Milanovic]


@@ -154,7 +506,7 @@ Verilator 4.202 2021-04-24
 * Fix Cygwin example compile issues (#2856). [Mark Shaw]
 * Fix select of with index variable (#2880). [Alexander Grobman]
 * Fix cmake version number to be numeric (#2881). [Yuri Victorovich]
-* Fix MinGW not supportting 'localtime_r' (#2882). [HyungKi Jeong]
+* Fix MinGW not supporting 'localtime_r' (#2882). [HyungKi Jeong]
 * Fix cast from packed, typedef'ed interface signal (#2884). [Todd Strader]
 * Fix VPI package reported as vpiModule (#2885). [Todd Strader]
 * Fix dumping waveforms to multiple FST files (#2889). [David Metz]
@@ -218,7 +570,7 @@ Verilator 4.108 2021-01-10
 **Major:**

 * Many VPI changes for IEEE compatibility, which may alter behavior from previous releases.
-* Support randomize() class method and rand (#2607). [Krzysztof Bieganski]
+* Support randomize() class method and rand (#2607). [Krzysztof Bieganski, Antmicro Ltd]

 **Minor:**

@@ -278,7 +630,7 @@ Verilator 4.104 2020-11-14
 * Support queue and associative array 'with' statements (#2616).
 * Support queue slicing (#2326).
 * Support associative array pattern assignments and defaults.
-* Support static methods and typedefs in classes (#2615). [Krzysztof Bieganski]
+* Support static methods and typedefs in classes (#2615). [Krzysztof Bieganski, Antmicro Ltd]
 * Add error on typedef referencing self (#2539). [Cody Piersall]
 * With --debug, turn off address space layout randomization.
 * Fix iteration over mutating list bug in VPI (#2588). [Kaleb Barrett]
@@ -301,7 +653,7 @@ Verilator 4.102 2020-10-15
 * Support # as a comment in -f files (#2497). [phantom-killua]
 * Support 'this' (#2585). [Rafal Kapuscik]
 * Support defines for FST tracing (#2592). [Markus Krause]
-* Support non-overapping implication inside properties (#1292). [Peter Monsson]
+* Support non-overlapping implication inside properties (#1292). [Peter Monsson]
 * Fix timescale with --hierarchical (#2554). [Yutetsu TAKATSUKASA]
 * Fix cmake build with --hierarchical (#2560). [Yutetsu TAKATSUKASA]
 * Fix -G dropping public indication (#2561). [Andrew Goessling]
@@ -327,7 +679,7 @@ Verilator 4.100 2020-09-07
 * Support (with limitations) class extern, class extends, virtual class.
 * Support $urandom, $urandom_range without stability.
 * Support assume property. [Peter Monsson]
-* Support non-overapping implication inside properties (#1292). [Peter Monsson]
+* Support non-overlapping implication inside properties (#1292). [Peter Monsson]
 * Fix false DECLFILENAME on black-boxed modules (#2430). [Philipp Wagner]
 * Fix naming of "id : begin" blocks.
 * Fix class constructor error on assignments to const.
@@ -2702,7 +3054,7 @@ Verilator 3.502 2005-11-30 Stable

 * Fix local non-IO variables in public functions and tasks.
 * Fix bad lifetime optimization when same signal is assigned multiple
-  times in both branch of a if. [Danny Ding]
+  times in both branch of an if. [Danny Ding]


 Verilator 3.501 2005-11-16 Stable
@@ -2842,8 +3194,8 @@ Verilator 3.450 2005-07-12
 * $finish will no longer exit, but set Verilated::gotFinish().
  This enables support for final statements, and for other cleanup code.
  If this is undesired, redefine the vl_user_finish routine. Top level
-  loops should use Verilated::gotFinish() as a exit condition for their
-  loop, and then call top->final(). To prevent a infinite loop, a double
+  loops should use Verilated::gotFinish() as an exit condition for their
+  loop, and then call top->final(). To prevent an infinite loop, a double
  $finish will still exit; this may be removed in future releases.
 * Support SystemVerilog keywords $bits, $countones, $isunknown,
  $onehot, $onehot0, always_comb, always_ff, always_latch, finish.
@@ -3244,7 +3596,7 @@ Verilator 3.201-beta 2003-12-10
 **Major:**

 * BETA VERSION, USE 3.124 for stable release!
-* Version 3.2XX includes a all new back-end.
+* Version 3.2XX includes an all new back-end.
  This includes automatic inlining, flattening of signals between
  hierarchy, and complete ordering of statements. This results in
  60-300% execution speedups, though less pretty C++ output. Even
@@ -3273,7 +3625,7 @@ Verilator 3.124 2003-12-05

 **Major:**

-* A optimized executable will be made by default, in addition to a debug
+* An optimized executable will be made by default, in addition to a debug
  executable. Invoking Verilator with --debug will pick the debug version.

 **Minor:**
@@ -3727,7 +4079,7 @@ Verilator 0.0 1994-07-08
 Copyright
 =========

-Copyright 2001-2021 by Wilson Snyder. This program is free software; you
+Copyright 2001-2023 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
@@ -7,7 +7,7 @@
 #
 #*****************************************************************************
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -53,7 +53,6 @@ INSTALL_DATA = @INSTALL_DATA@
 MAKEINFO = makeinfo
 POD2TEXT = pod2text
 MKINSTALLDIRS = $(SHELL) $(srcdir)/src/mkinstalldirs
-PERL = @PERL@

 # Version (for docs/guide/conf.py)
 PACKAGE_VERSION_NUMBER = @PACKAGE_VERSION_NUMBER@
@@ -107,6 +106,7 @@ SUBDIRS = docs src test_regress \
 	examples/cmake_tracing_c \
 	examples/cmake_tracing_sc \
 	examples/cmake_protect_lib \
+	examples/make_hello_binary \
 	examples/make_hello_c \
 	examples/make_hello_sc \
 	examples/make_tracing_c \
@@ -125,7 +125,12 @@ EXAMPLES_FIRST = \
 EXAMPLES = $(EXAMPLES_FIRST) $(filter-out $(EXAMPLES_FIRST), $(sort $(wildcard examples/*)))

 # See uninstall also - don't put wildcards in this variable, it might uninstall other stuff
-VL_INST_MAN_FILES = verilator.1 verilator_coverage.1
+# No verilator_ccache_report.1, verilator_difftree.1 as those are not bin/ installed
+VL_INST_MAN_FILES = \
+	verilator.1 \
+	verilator_coverage.1 \
+	verilator_gantt.1 \
+	verilator_profcfunc.1 \

 default: all
 all: all_nomsg msg_test
@@ -178,8 +183,12 @@ docs: info

 info: $(INFOS)

-%.1: ${srcdir}/bin/%
+verilator.1: ${srcdir}/bin/verilator
 	pod2man $< $@
+verilator_coverage.1: ${srcdir}/bin/verilator_coverage
+	pod2man $< $@
+%.1: ${srcdir}/bin/%
+	help2man --no-info --no-discard-stderr --version-string=- $< -o $@

 .PHONY: verilator.html
 verilator.html:
@@ -192,7 +201,7 @@ verilator.pdf: Makefile

 # See uninstall also - don't put wildcards in this variable, it might uninstall other stuff
 VL_INST_BIN_FILES = verilator verilator_bin$(EXEEXT) verilator_bin_dbg$(EXEEXT) verilator_coverage_bin_dbg$(EXEEXT) \
-	verilator_ccache_report verilator_coverage verilator_gantt verilator_includer verilator_profcfunc
+	verilator_ccache_report verilator_coverage verilator_difftree verilator_gantt verilator_includer verilator_profcfunc
 # Some scripts go into both the search path and pkgdatadir,
 # so they can be found by the user, and under $VERILATOR_ROOT.

@@ -203,6 +212,7 @@ VL_INST_INC_BLDDIR_FILES = \
 # Files under srcdir, instead of build time
 VL_INST_INC_SRCDIR_FILES = \
 	include/*.[chv]* \
+	include/*.sv \
 	include/gtkwave/*.[chv]* \
 	include/vltstd/*.[chv]* \

@@ -224,6 +234,7 @@ installbin:
 	$(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/bin
 	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_includer $(DESTDIR)$(pkgdatadir)/bin/verilator_includer )
 	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_ccache_report $(DESTDIR)$(pkgdatadir)/bin/verilator_ccache_report )
+	( cd ${srcdir}/bin ; $(INSTALL_PROGRAM) verilator_difftree $(DESTDIR)$(pkgdatadir)/bin/verilator_difftree )

 # Man files can either be part of the original kit, or built in current directory
 # So important we use $^ so VPATH is searched
@@ -243,6 +254,7 @@ installdata:
 	; for p in $(VL_INST_INC_SRCDIR_FILES) ; do \
 	  $(INSTALL_DATA) $$p $(DESTDIR)$(pkgdatadir)/$$p; \
 	done
+	$(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_hello_binary
 	$(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_hello_c
 	$(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_hello_sc
 	$(MKINSTALLDIRS) $(DESTDIR)$(pkgdatadir)/examples/make_tracing_c
@@ -278,6 +290,7 @@ uninstall:
 	-rmdir $(DESTDIR)$(pkgdatadir)/include/gtkwave
 	-rmdir $(DESTDIR)$(pkgdatadir)/include/vltstd
 	-rmdir $(DESTDIR)$(pkgdatadir)/include
+	-rmdir $(DESTDIR)$(pkgdatadir)/examples/make_hello_binary
 	-rmdir $(DESTDIR)$(pkgdatadir)/examples/make_hello_c
 	-rmdir $(DESTDIR)$(pkgdatadir)/examples/make_hello_sc
 	-rmdir $(DESTDIR)$(pkgdatadir)/examples/make_tracing_c
@@ -299,39 +312,63 @@ install-all: installbin installman installdata install-msg
 install-here: installman info

 # Use --xml flag to see the cppcheck code to use for suppression
-CPPCHECK_CPP = $(wildcard \
-	$(srcdir)/examples/*/*.cpp \
-	$(srcdir)/include/*.cpp \
-	$(srcdir)/src/*.cpp )
-CPPCHECK_H = $(wildcard \
+CPPCHECK1_CPP = $(wildcard $(srcdir)/include/*.cpp)
+CPPCHECK2_CPP = $(wildcard $(srcdir)/examples/*/*.cpp)
+CPPCHECK3_CPP = $(wildcard $(srcdir)/src/Vlc*.cpp)
+CPPCHECK4_CPP = $(wildcard $(srcdir)/src/V3[A-D]*.cpp $(srcdir)/src/Verilator*.cpp)
+CPPCHECK5_CPP = $(wildcard $(srcdir)/src/V3[E-I]*.cpp)
+CPPCHECK6_CPP = $(wildcard $(srcdir)/src/V3[P-Z]*.cpp)
+CPPCHECK7_CPP = $(wildcard $(srcdir)/src/V3[L-R]*.cpp)
+CPPCHECK8_CPP = $(wildcard $(srcdir)/src/V3[S-Z]*.cpp)
+CHECK_CPP = $(CPPCHECK1_CPP) $(CPPCHECK2_CPP) $(CPPCHECK3_CPP) $(CPPCHECK4_CPP) \
+	$(CPPCHECK5_CPP) $(CPPCHECK6_CPP) $(CPPCHECK7_CPP) $(CPPCHECK8_CPP)
+CHECK_H = $(wildcard \
 	$(srcdir)/include/*.h \
 	$(srcdir)/src/*.h )
-CPPCHECK_YL = $(wildcard \
+CHECK_YL = $(wildcard \
 	$(srcdir)/src/*.y \
 	$(srcdir)/src/*.l )
 CPPCHECK = src/cppcheck_filtered cppcheck
 CPPCHECK_FLAGS = --enable=all --inline-suppr \
-	--suppress=unusedScopedObject --suppress=cstyleCast --suppress=useInitializationList \
-	--suppress=nullPointerRedundantCheck
+	--suppress=cstyleCast --suppress=useInitializationList \
+	--suppress=nullPointer --suppress=nullPointerRedundantCheck --suppress=ctunullpointer \
+	--suppress=unusedFunction --suppress=unusedScopedObject \
+	--suppress=useStlAlgorithm
 CPPCHECK_FLAGS += --xml
-CPPCHECK_DEP = $(subst .cpp,.cppcheck,$(CPPCHECK_CPP))
+CPPCHECK_DEP = $(subst .cpp,.cppcheck,$(CHECK_CPP))
 CPPCHECK_INC = -I$(srcdir)/include -I$(srcdir)/src/obj_dbg -I$(srcdir)/src

-cppcheck: $(CPPCHECK_DEP)
-%.cppcheck: %.cpp
-	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 -DVL_THREADED=1 $(CPPCHECK_INC) $<
+cppcheck: cppcheck-1 cppcheck-2 cppcheck-3 cppcheck-4 cppcheck-5 cppcheck-6 cppcheck-7 cppcheck-8
+cppcheck-1:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK1_CPP)
+cppcheck-2:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK2_CPP)
+cppcheck-3:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK3_CPP)
+cppcheck-4:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK4_CPP)
+cppcheck-5:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK5_CPP)
+cppcheck-6:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK6_CPP)
+cppcheck-7:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK7_CPP)
+cppcheck-8:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK8_CPP)

 CLANGTIDY = clang-tidy
-CLANGTIDY_FLAGS = -config='' -checks='-fuchsia-*,-cppcoreguidelines-avoid-c-arrays,-cppcoreguidelines-init-variables'
-CLANGTIDY_DEP = $(subst .h,.h.tidy,$(CPPCHECK_H)) \
-	$(subst .cpp,.cpp.tidy,$(CPPCHECK_CPP))
-CLANGTIDY_DEFS = -DVL_DEBUG=1 -DVL_THREADED=1 -DVL_CPPCHECK=1
+CLANGTIDY_FLAGS = -config='' \
+	-header-filter='.*' \
+	-checks='-fuchsia-*,-cppcoreguidelines-avoid-c-arrays,-cppcoreguidelines-init-variables,-cppcoreguidelines-avoid-goto,-modernize-avoid-c-arrays,-readability-magic-numbers,-readability-simplify-boolean-expr,-cppcoreguidelines-macro-usage' \
+
+CLANGTIDY_DEP = $(subst .cpp,.cpp.tidy,$(CHECK_CPP))
+CLANGTIDY_DEFS = -DVL_DEBUG=1 -DVL_CPPCHECK=1

 clang-tidy: $(CLANGTIDY_DEP)
 %.cpp.tidy: %.cpp
 	$(CLANGTIDY) $(CLANGTIDY_FLAGS) $< -- $(CLANGTIDY_DEFS) $(CPPCHECK_INC) | 2>&1 tee $@
 %.h.tidy: %.h
-	$(CLANGTIDY) $(CLANGTIDY_FLAGS) $< -- $(CLANGTIDY_DEFS) $(CPPCHECK_INC) | 2>&1 tee $@
+	$(CLANGTIDY) $(CLANGTIDY_FLAGS) $< -- $(CLANGTIDY_DEFS) $(CPPCHECK_INC) -x c++-header | 2>&1 tee $@

 analyzer-src:
 	-rm -rf src/obj_dbg
@@ -343,19 +380,20 @@ analyzer-include:

 format: clang-format yapf format-pl-exec

-CLANGFORMAT = clang-format-11
+CLANGFORMAT = clang-format-14
 CLANGFORMAT_FLAGS = -i
-CLANGFORMAT_FILES = $(CPPCHECK_CPP) $(CPPCHECK_H) $(CPPCHECK_YL) test_regress/t/*.c* test_regress/t/*.h
+CLANGFORMAT_FILES = $(CHECK_CPP) $(CHECK_H) $(CHECK_YL) test_regress/t/*.c* test_regress/t/*.h

 clang-format:
-	@$(CLANGFORMAT) --version | egrep 11.0 > /dev/null \
-		|| echo "*** You are not using clang-format 11.0, indents may differ from master's ***"
+	@$(CLANGFORMAT) --version | egrep 14.0 > /dev/null \
+		|| echo "*** You are not using clang-format-14, indents may differ from master's ***"
 	$(CLANGFORMAT) $(CLANGFORMAT_FLAGS) $(CLANGFORMAT_FILES)

 PY_PROGRAMS = \
 	bin/verilator_ccache_report \
 	bin/verilator_difftree \
 	bin/verilator_gantt \
+	bin/verilator_includer \
 	bin/verilator_profcfunc \
 	examples/xml_py/vl_file_copy \
 	examples/xml_py/vl_hier_graph \
@@ -369,6 +407,7 @@ PY_PROGRAMS = \
 	src/flexfix \
 	src/vlcovgen \
 	test_regress/t/*.pf \
+	nodist/clang_check_attributes \
 	nodist/code_coverage \
 	nodist/dot_importer \
 	nodist/fuzzer/actual_fail \
@@ -388,10 +427,10 @@ yapf:
 FLAKE8 = flake8
 FLAKE8_FLAGS = \
 	--extend-exclude=fastcov.py \
-	--ignore=E123,E129,E251,E501,W503,W504,E701
+	--ignore=E123,E129,E251,E402,E501,W503,W504,E701

 PYLINT = pylint
-PYLINT_FLAGS = --disable=R0801
+PYLINT_FLAGS = --score=n --disable=R0801

 lint-py:
 	-$(FLAKE8) $(FLAKE8_FLAGS) $(PY_PROGRAMS)
@@ -21,18 +21,18 @@ Welcome to Verilator
 .. list-table::

   * - **Welcome to Verilator, the fastest Verilog/SystemVerilog simulator.**
-        * Accepts synthesizable Verilog or SystemVerilog
+        * Accepts Verilog or SystemVerilog
        * Performs lint code-quality checks
        * Compiles into multithreaded C++, or SystemC
        * Creates XML to front-end your own tools
     - |Logo|
   * - |verilator multithreaded performance|
     - **Fast**
-        * Outperforms many commercial simulators
-        * Single- and multi-threaded output models
+        * Outperforms many closed-source commercial simulators
+        * Single- and multithreaded output models
   * - **Widely Used**
        * Wide industry and academic deployment
-        * Out-of-the-box support from Arm, and RISC-V vendor IP
+        * Out-of-the-box support from Arm and RISC-V vendor IP
     - |verilator usage|
   * - |verilator community|
     - **Community Driven & Openly Licensed**
@@ -52,28 +52,28 @@ What Verilator Does
 Verilator is invoked with parameters similar to GCC or Synopsys's VCS.  It
 "Verilates" the specified Verilog or SystemVerilog code by reading it,
 performing lint checks, and optionally inserting assertion checks and
-coverage-analysis points. It outputs single- or multi-threaded .cpp and .h
+coverage-analysis points. It outputs single- or multithreaded .cpp and .h
 files, the "Verilated" code.

-The user writes a little C++/SystemC wrapper file, which instantiates the
-"Verilated" model of the user's top level module. These C++/SystemC files
-are then compiled by a C++ compiler (gcc/clang/MSVC++). The resulting
-executable performs the design simulation. Verilator also supports linking
-its generated libraries, optionally encrypted, into other simulators.
+These Verilated C++/SystemC files are then compiled by a C++ compiler
+(gcc/clang/MSVC++), optionally along with a user's own C++/SystemC wrapper
+file to instantiate the Verilated model. Executing the resulting executable
+performs the design simulation. Verilator also supports linking Verilated
+generated libraries, optionally encrypted, into other simulators.

-Verilator may not be the best choice if you are expecting a full featured
-replacement for NC-Verilog, VCS or another commercial Verilog simulator, or
-if you are looking for a behavioral Verilog simulator e.g. for a quick
-class project (we recommend `Icarus Verilog`_ for this.) However, if you
-are looking for a path to migrate SystemVerilog to C++ or SystemC, or your
-team is comfortable writing just a touch of C++ code, Verilator is the tool
-for you.
+Verilator may not be the best choice if you are expecting a full-featured
+replacement for a closed-source Verilog simulator, needs SDF annotation,
+mixed-signal simulation, or are doing a quick class project (we recommend
+`Icarus Verilog`_ for classwork.)  However, if you are looking for a path
+to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of
+synthesizable designs containing limited verification constructs, Verilator
+is the tool for you.


 Performance
 ===========

-Verilator does not simply convert Verilog HDL to C++ or SystemC. Rather,
+Verilator does not directly translate Verilog HDL to C++ or SystemC. Rather,
 Verilator compiles your code into a much faster optimized and optionally
 thread-partitioned model, which is in turn wrapped inside a C++/SystemC
 module. The results are a compiled Verilog model that executes even on a
@@ -84,9 +84,11 @@ multithreading (yielding 200-1000x total over interpreted simulators).

 Verilator has typically similar or better performance versus the
 closed-source Verilog simulators (Carbon Design Systems Carbonator,
-Modelsim, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic
-CVer/CVC). But, Verilator is open-sourced, so you can spend on computes
-rather than licenses. Thus Verilator gives you the best cycles/dollar.
+Modelsim/Questa, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and
+Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on
+computes rather than licenses. Thus, Verilator gives you the best
+cycles/dollar.
+

 Installation & Documentation
 ============================
@@ -99,7 +101,7 @@ For more information:
 - `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_,
  or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_

- `Subscribe to verilator announcements
+- `Subscribe to Verilator announcements
  <https://github.com/verilator/verilator-announce>`_

 - `Verilator forum <https://verilator.org/forum>`_
@@ -130,14 +132,14 @@ Related Projects
 - `GTKwave <http://gtkwave.sourceforge.net/>`_ - Waveform viewer for
  Verilator traces.

- `Icarus Verilog`_ - Icarus is a full featured interpreted Verilog
+- `Icarus Verilog`_ - Icarus is a full-featured interpreted Verilog
  simulator. If Verilator does not support your needs, perhaps Icarus may.


 Open License
 ============

-Verilator is Copyright 2003-2021 by Wilson Snyder. (Report bugs to
+Verilator is Copyright 2003-2023 by Wilson Snyder. (Report bugs to
 `Verilator Issues <https://verilator.org/issues>`_.)

 Verilator is free software; you can redistribute it and/or modify it under
@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -31,6 +31,7 @@ my $opt_gdb;
 my $opt_rr;
 my $opt_gdbbt;
 my $opt_quiet_exit;
+my $opt_unlimited_stack = 1;

 # No arguments can't do anything useful.  Give help
 if ($#ARGV < 0) {
@@ -49,16 +50,17 @@ foreach my $sw (@ARGV) {
 Getopt::Long::config("no_auto_abbrev", "pass_through");
 if (! GetOptions(
          # Major operating modes
-          "help"        => \&usage,
-          "debug"       => \&debug,
-          # "version!"  => \&version,   # Also passthru'ed
+          "help"             => \&usage,
+          "debug"            => \&debug,
+          # "version!"       => \&version,   # Also passthru'ed
          # Switches
-          "gdb!"        => \$opt_gdb,
-          "gdbbt!"      => \$opt_gdbbt,
-          "quiet-exit!" => \$opt_quiet_exit,
-          "rr!"         => \$opt_rr,
+          "gdb!"             => \$opt_gdb,
+          "gdbbt!"           => \$opt_gdbbt,
+          "quiet-exit!"      => \$opt_quiet_exit,
+          "rr!"              => \$opt_rr,
+          "unlimited-stack!" => \$opt_unlimited_stack,
          # Additional parameters
-          "<>"          => sub {},      # Ignored
+          "<>"               => sub {},      # Ignored
    )) {
    pod2usage(-exitstatus => 2, -verbose => 0);
 }
@@ -76,7 +78,8 @@ if ($opt_gdbbt && !gdb_works()) {
 my @quoted_sw = map { sh_escape($_) } @Opt_Verilator_Sw;
 if ($opt_gdb) {
    # Generic GDB interactive
-    run (aslr_off()
+    run (ulimit_stack_unlimited()
+         . aslr_off()
         . ($ENV{VERILATOR_GDB} || "gdb")
         . " " . verilator_bin()
         # Note, uncomment to set breakpoints before running:
@@ -92,12 +95,14 @@ if ($opt_gdb) {
         . " -ex 'bt'");
 } elsif ($opt_rr) {
    # Record with rr
-    run (aslr_off()
+    run (ulimit_stack_unlimited()
+         . aslr_off()
         . "rr record " . verilator_bin()
         . " " . join(' ', @quoted_sw));
 } elsif ($opt_gdbbt && $Debug) {
    # Run under GDB to get gdbbt
-    run (aslr_off()
+    run (ulimit_stack_unlimited()
+         . aslr_off()
         . "gdb"
         . " " . verilator_bin()
         . " --batch --quiet --return-child-result"
@@ -106,10 +111,13 @@ if ($opt_gdb) {
         . " -ex 'bt' -ex 'quit'");
 } elsif ($Debug) {
    # Debug
-    run(aslr_off() . verilator_bin() . " " . join(' ', @quoted_sw));
+    run(ulimit_stack_unlimited()
+        . aslr_off()
+        . verilator_bin()
+        . " " . join(' ', @quoted_sw));
 } else {
    # Normal, non gdb
-    run(verilator_bin() . " " . join(' ', @quoted_sw));
+    run(ulimit_stack_unlimited() . verilator_bin() . " " . join(' ', @quoted_sw));
 }

 #----------------------------------------------------------------------
@@ -180,6 +188,17 @@ sub aslr_off {
    }
 }

+sub ulimit_stack_unlimited {
+    return "" if !$opt_unlimited_stack;
+    system("ulimit -s unlimited 2>/dev/null");
+    my $status = $?;
+    if ($status == 0) {
+        return "ulimit -s unlimited 2>/dev/null; exec ";
+    } else {
+        return "";
+    }
+}
+
 sub run {
    # Run command, check errors
    my $command = shift;
@@ -244,6 +263,7 @@ Verilator - Translate and simulate SystemVerilog code using C++/SystemC

    verilator --help
    verilator --version
+    verilator --binary -j 0 [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
    verilator --cc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
    verilator --sc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so]
    verilator --lint-only -Wall [source_files.v]...
@@ -267,7 +287,7 @@ detailed descriptions of these arguments.

 =for VL_SPHINX_EXTRACT "_build/gen/args_verilator.rst"

-    <file.v>                    Verilog package, module and top module filenames
+    <file.v>                    Verilog package, module, and top module filenames
    <file.c/cc/cpp>             Optional C++ files to compile in
    <file.a/o/so>               Optional C++ files to link in

@@ -282,35 +302,43 @@ detailed descriptions of these arguments.
    --autoflush                 Flush streams after all $displays
    --bbox-sys                  Blackbox unknown $system calls
    --bbox-unsup                Blackbox unsupported language features
-    --bin <filename>            Override Verilator binary
+    --binary                    Build model binary
    --build                     Build model executable/library after Verilation
-     -CFLAGS <flags>            C++ compiler arguments for makefile
+    --build-dep-bin <filename>  Override build dependency Verilator binary
+    --build-jobs <jobs>         Parallelism for --build
    --cc                        Create C++ output
    --cdc                       Clock domain crossing analysis
+     -CFLAGS <flags>            C++ compiler arguments for makefile
    --clk <signal-name>         Mark specified signal as clock
-    --make <build-tool>         Generate scripts for specified build tool
+    --no-clk <signal-name>      Prevent marking specified signal as clock
    --compiler <compiler-name>  Tune for specified C++ compiler
    --converge-limit <loops>    Tune convergence settle time
    --coverage                  Enable all coverage
    --coverage-line             Enable line coverage
    --coverage-max-width <width>   Maximum array depth for coverage
    --coverage-toggle           Enable toggle coverage
-    --coverage-user             Enable SVL user coverage
    --coverage-underscore       Enable coverage of _signals
+    --coverage-user             Enable SVL user coverage
     -D<var>[=<value>]          Set preprocessor define
    --debug                     Enable debugging
    --debug-check               Enable debugging assertions
    --no-debug-leak             Disable leaking memory in --debug mode
    --debugi <level>            Enable debugging at a specified level
    --debugi-<srcfile> <level>  Enable debugging a source file at a level
+    --no-decoration             Disable comments and symbol decorations
    --default-language <lang>   Default language to parse
     +define+<var>=<value>      Set preprocessor define
    --dpi-hdr-only              Only produce the DPI header file
    --dump-defines              Show preprocessor defines with -E
-    --dump-tree                 Enable dumping .tree files
-    --dump-treei <level>        Enable dumping .tree files at a level
-    --dump-treei-<srcfile> <level>  Enable dumping .tree file at a source file at a level
+    --dump-dfg                  Enable dumping DfgGraphs to .dot files
+    --dump-graph                Enable dumping V3Graphs to .dot files
+    --dump-tree                 Enable dumping Ast .tree files
    --dump-tree-addrids         Use short identifiers instead of addresses
+    --dump-<srcfile>            Enable dumping everything in source file
+    --dumpi-dfg <level>         Enable dumping DfgGraphs to .dot files at level
+    --dumpi-graph <level>       Enable dumping V3Graphs to .dot files at level
+    --dumpi-tree <level>        Enable dumping Ast .tree files at level
+    --dumpi-<srcfile> <level>   Enable dumping everything in source file at level
     -E                         Preprocess, but do not compile
    --error-limit <value>       Abort after this number of errors
    --exe                       Link to create executable
@@ -319,61 +347,62 @@ detailed descriptions of these arguments.
     -f <file>                  Parse arguments from a file
     -FI <file>                 Force include of a file
    --flatten                   Force inlining of all modules, tasks and functions
+     -fno-<optimization>        Disable internal optimization stage
     -G<name>=<value>           Overwrite top-level parameter
+    --gate-stmts <value>        Tune gate optimizer depth
    --gdb                       Run Verilator under GDB interactively
    --gdbbt                     Run Verilator under GDB for backtrace
    --generate-key              Create random key for --protect-key
    --getenv <var>              Get environment variable with defaults
+    --get-supported <feature>   Get if feature is supported
    --help                      Display this help
    --hierarchical              Enable hierarchical Verilation
     -I<dir>                    Directory to search for includes
-     -j <jobs>                  Parallelism for --build
-    --gate-stmts <value>        Tune gate optimizer depth
    --if-depth <value>          Tune IFDEPTH warning
     +incdir+<dir>              Directory to search for includes
    --inline-mult <value>       Tune module inlining
    --instr-count-dpi <value>   Assumed dynamic instruction count of DPI imports
-     -LDFLAGS <flags>           Linker pre-object arguments for makefile
+     -j <jobs>                  Parallelism for --build (alias to --build-jobs)
    --l2-name <value>           Verilog scope name of the top module
    --language <lang>           Default language standard to parse
+     -LDFLAGS <flags>           Linker pre-object arguments for makefile
+    --lib-create <name>         Create a DPI library
     +libext+<ext>+[ext]...     Extensions for finding modules
    --lint-only                 Lint, but do not make output
+    --make <build-tool>         Generate scripts for specified build tool
     -MAKEFLAGS <flags>         Arguments to pass to make during --build
+    --main                      Generate C++ main() file
    --max-num-width <value>     Maximum number width (default: 64K)
-    --MMD                       Create .d dependency files
-    --MP                        Create phony dependency targets
    --Mdir <directory>          Name of output object directory
-    --no-merge-const-pool       Disable merging of different types in const pool
+    --MMD                       Create .d dependency files
    --mod-prefix <topname>      Name to prepend to lower classes
-    --no-clk <signal-name>      Prevent marking specified signal as clock
-    --no-decoration             Disable comments and symbol decorations
-    --no-pins64                 Don't use vluint64_t's for 33-64 bit sigs
-    --no-skip-identical         Disable skipping identical output
+    --MP                        Create phony dependency targets
     +notimingchecks            Ignored
     -O0                        Disable optimizations
-     -O3                        High performance optimizations
+     -O3                        High-performance optimizations
     -O<optimization-letter>    Selectable optimizations
     -o <executable>            Name of final executable
    --no-order-clock-delay      Disable ordering clock enable assignments
-    --no-verilate               Skip verilation and just compile previously Verilated code.
    --output-split <statements>          Split .cpp files into pieces
    --output-split-cfuncs <statements>   Split model functions
    --output-split-ctrace <statements>   Split tracing functions
     -P                         Disable line numbers and blanks with -E
-    --pins-bv <bits>            Specify types for top level ports
-    --pins-sc-uint              Specify types for top level ports
-    --pins-sc-biguint           Specify types for top level ports
-    --pins-uint8                Specify types for top level ports
+    --pins-bv <bits>            Specify types for top-level ports
+    --pins-sc-biguint           Specify types for top-level ports
+    --pins-sc-uint              Specify types for top-level ports
+    --pins-uint8                Specify types for top-level ports
+    --no-pins64                 Don't use uint64_t's for 33-64 bit sigs
    --pipe-filter <command>     Filter all input through a script
    --pp-comments               Show preprocessor comments with -E
-    --prefix <topname>          Name of top level class
+    --prefix <topname>          Name of top-level class
+    --private                   Debugging; see docs
    --prof-c                    Compile C++ code with profiling
    --prof-cfuncs               Name functions for profiling
-    --prof-threads              Enable generating gantt chart data for threads
-    --protect-key <key>         Key for symbol protection
+    --prof-exec                 Enable generating execution profile for gantt chart
+    --prof-pgo                  Enable generating profiling data for PGO
    --protect-ids               Hash identifier names for obscurity
+    --protect-key <key>         Key for symbol protection
    --protect-lib <name>        Create a DPI protected library
-    --private                   Debugging; see docs
    --public                    Debugging; see docs
    --public-flat-rw            Mark all variables, etc as public_flat_rw
     -pvalue+<name>=<value>     Overwrite toplevel parameter
@@ -384,17 +413,21 @@ detailed descriptions of these arguments.
    --rr                        Run Verilator and record with rr
    --savable                   Enable model save-restore
    --sc                        Create SystemC output
+    --no-skip-identical         Disable skipping identical output
    --stats                     Create statistics file
    --stats-vars                Provide statistics on variables
+    --structs-packed            Convert all unpacked structures to packed structures
     -sv                        Enable SystemVerilog parsing
     +systemverilogext+<ext>    Synonym for +1800-2017ext+<ext>
    --threads <threads>         Enable multithreading
    --threads-dpi <mode>        Enable multithreaded DPI
    --threads-max-mtasks <mtasks>  Tune maximum mtask partitioning
+    --timing                    Enable timing support
+    --no-timing                 Disable timing support
    --timescale <timescale>     Sets default timescale
    --timescale-override <timescale>  Overrides all timescales
    --top <topname>             Alias of --top-module
-    --top-module <topname>      Name of top level input module
+    --top-module <topname>      Name of top-level input module
    --trace                     Enable waveform creation
    --trace-coverage            Enable tracing of coverage
    --trace-depth <levels>      Depth of tracing
@@ -403,14 +436,16 @@ detailed descriptions of these arguments.
    --trace-max-width <width>   Maximum array depth for tracing
    --trace-params              Enable tracing of parameters
    --trace-structs             Enable tracing structure names
-    --trace-threads <threads>   Enable waveform creation on separate threads
+    --trace-threads <threads>   Enable FST waveform creation on separate threads
    --trace-underscore          Enable tracing of _signals
     -U<var>                    Undefine preprocessor define
+    --no-unlimited-stack        Don't disable stack size limit
    --unroll-count <loops>      Tune maximum loop iterations
    --unroll-stmts <stmts>      Tune maximum loop body size
    --unused-regexp <regexp>    Tune UNUSED lint signals
     -V                         Verbose version and config
     -v <filename>              Verilog library
+    --no-verilate               Skip Verilation and just compile previously Verilated code
     +verilog1995ext+<ext>      Synonym for +1364-1995ext+<ext>
     +verilog2001ext+<ext>      Synonym for +1364-2001ext+<ext>
    --version                   Displays program version and exits
@@ -425,6 +460,9 @@ detailed descriptions of these arguments.
     -Wno-lint                  Disable all lint warnings
     -Wno-style                 Disable all style warnings
     -Wpedantic                 Warn on compliance-test issues
+     -Wwarn-<message>           Enable specified warning message
+     -Wwarn-lint                Enable lint warning message
+     -Wwarn-style               Enable style warning message
    --x-assign <mode>           Assign non-initial Xs to this value
    --x-initial <mode>          Assign initial Xs to this value
    --x-initial-edge            Enable initial X->0 and X->1 edge triggers
@@ -444,10 +482,10 @@ description of these arguments.
     +verilator+error+limit+<value>    Set error limit
     +verilator+help                   Display help
     +verilator+noassert               Disable assert checking
-     +verilator+prof+threads+file+<filename>  Set profile filename
-     +verilator+prof+threads+start+<value>    Set profile starting point
-     +verilator+prof+threads+window+<value>   Set profile duration
-     +verilator+prof+vlt+file+<filename>      Set profile guided filename
+     +verilator+prof+exec+file+<filename>  Set execution profile filename
+     +verilator+prof+exec+start+<value>    Set execution profile starting point
+     +verilator+prof+exec+window+<value>   Set execution profile duration
+     +verilator+prof+vlt+file+<filename>   Set PGO profile filename
     +verilator+rand+reset+<value>     Set random reset technique
     +verilator+seed+<value>           Set random seed
     +verilator+V                      Verbose version and config
@@ -458,7 +496,7 @@ description of these arguments.

 The latest version is available from L<https://verilator.org>.

-Copyright 2003-2021 by Wilson Snyder. This program is free software; you can
+Copyright 2003-2023 by Wilson Snyder. This program is free software; you can
 redistribute it and/or modify the Verilator internals under the terms of
 either the GNU Lesser General Public License Version 3 or the Perl Artistic
 License Version 2.0.
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0115,C0116,C0123,C0301,R0902,R0913,R0914,R0912,R0915,W0621
+# pylint: disable=C0103,C0114,C0115,C0116,C0123,C0209,C0301,R0902,R0913,R0914,R0912,R0915,W0621
 ######################################################################

 import argparse
@@ -12,9 +12,12 @@ from datetime import datetime
 parser = argparse.ArgumentParser(
    allow_abbrev=False,
    formatter_class=argparse.RawDescriptionHelpFormatter,
-    description="""Report ccache behavior of a Verilated model build.""",
+    description="""Report ccache behavior of a Verilated model build.
+
+    For documentation see
+    https://verilator.org/guide/latest/exe_verilator_ccache_report.html""",
    epilog=
-    """Copyright 2002-2021 by Wilson Snyder. This program is free software; you
+    """Copyright 2002-2023 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
@@ -1,7 +1,7 @@
 #!/usr/bin/env perl
 ######################################################################
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -187,7 +187,7 @@ L<https://verilator.org/guide/latest/exe_verilator_coverage.html>.

 The latest version is available from L<https://verilator.org>.

-Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+Copyright 2003-2023 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify the Verilator internals under the terms
 of either the GNU Lesser General Public License Version 3 or the Perl
 Artistic License Version 2.0.
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0116
+# pylint: disable=C0103,C0114,C0116,C0209
 ######################################################################

 import argparse
@@ -38,10 +38,10 @@ def diff_dir(a, b):

    anyfile = False
    for base in sorted(files.keys()):
+        if ('a' not in files[base]) or ('b' not in files[base]):
+            continue
        a = files[base]['a']
        b = files[base]['b']
-        if not a or not b:
-            continue
        print("=" * 70)
        print("= %s <-> %s" % (a, b))
        diff_file(a, b)
@@ -73,7 +73,7 @@ def diff_file(a, b):

 def version_from(filename):
    # Return dump format
-    with open(filename) as fh:
+    with open(filename, "r", encoding="utf8") as fh:
        lineno = 0
        for line in fh:
            if lineno > 10:
@@ -86,8 +86,8 @@ def version_from(filename):

 def filterf(fn1, fn2):
    # Remove hex numbers before diffing
-    with open(fn1) as fh1:
-        with open(fn2, "w") as fh2:
+    with open(fn1, "r", encoding="utf8") as fh1:
+        with open(fn2, "w", encoding="utf8") as fh2:
            for line in fh1:
                if re.search(r' This=', line):
                    continue
@@ -104,16 +104,13 @@ def filterf(fn1, fn2):
 parser = argparse.ArgumentParser(
    allow_abbrev=False,
    formatter_class=argparse.RawDescriptionHelpFormatter,
-    description="""Compare two Verilator debugging trees""",
-    epilog=
-    """Verilator_difftree is used for debugging Verilator tree output files.
+    description="""Compare two Verilator debugging trees.
+
+Verilator_difftree is used for debugging Verilator tree output files.
 It performs a diff between two files, or all files common between two
-directories, ignoring irrelevant pointer differences.
-
-For documentation see
-https://verilator.org/guide/latest/exe_verilator_difftree.html
-
-Copyright 2005-2021 by Wilson Snyder. This program is free software; you
+directories, ignoring irrelevant pointer differences.""",
+    epilog=
+    """Copyright 2005-2023 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0116,C0301,R0914,R0912,R0915,W0511,eval-used
+# pylint: disable=C0103,C0114,C0116,C0209,C0301,R0914,R0912,R0915,W0511,eval-used
 ######################################################################

 import argparse
@@ -9,7 +9,7 @@ import re
 import statistics
 # from pprint import pprint

-Threads = collections.defaultdict(lambda: {})
+Threads = collections.defaultdict(lambda: collections.defaultdict(lambda: {}))
 Mtasks = collections.defaultdict(lambda: {})
 Evals = collections.defaultdict(lambda: {})
 EvalLoops = collections.defaultdict(lambda: {})
@@ -29,13 +29,13 @@ def process(filename):


 def read_data(filename):
-    with open(filename) as fh:
-        re_prof = re.compile(
-            r'^VLPROF mtask\s(\d+)\sstart\s(\d+)\selapsed\s(\d+)\spredict_start\s(\d+)\spredict_cost\s(\d+)\scpu\s(\d+)\son thread (\d+)'
-        )
-        re_eval = re.compile(r'^VLPROF eval\sstart\s(\d+)\selapsed\s(\d+)')
-        re_loop = re.compile(
-            r'^VLPROF eval_loop\sstart\s(\d+)\selapsed\s(\d+)')
+    with open(filename, "r", encoding="utf8") as fh:
+        re_thread = re.compile(r'^VLPROFTHREAD (\d+)$')
+        re_record = re.compile(r'^VLPROFEXEC (\S+) (\d+)(.*)$')
+        re_payload_mtaskBegin = re.compile(
+            r'id (\d+) predictStart (\d+) cpu (\d+)')
+        re_payload_mtaskEnd = re.compile(r'id (\d+) predictCost (\d+)')
+
        re_arg1 = re.compile(r'VLPROF arg\s+(\S+)\+([0-9.]*)\s*')
        re_arg2 = re.compile(r'VLPROF arg\s+(\S+)\s+([0-9.]*)\s*$')
        re_stat = re.compile(r'VLPROF stat\s+(\S+)\s+([0-9.]+)')
@@ -43,47 +43,60 @@ def read_data(filename):
        re_proc_cpu = re.compile(r'VLPROFPROC processor\s*:\s*(\d+)\s*$')
        re_proc_dat = re.compile(r'VLPROFPROC ([a-z_ ]+)\s*:\s*(.*)$')
        cpu = None
+        thread = None
+
+        lastEvalBeginTick = None
+        lastEvalLoopBeginTick = None

        for line in fh:
-            if re_prof.match(line):
-                match = re_prof.match(line)
-                mtask = int(match.group(1))
-                start = int(match.group(2))
-                elapsed_time = int(match.group(3))
-                end = start + elapsed_time
-                predict_start = int(match.group(4))
-                predict_cost = int(match.group(5))
-                cpu = int(match.group(6))
-                thread = int(match.group(7))
-                if start not in Threads[thread]:
-                    Threads[thread][start] = {}
-                Threads[thread][start]['mtask'] = mtask
-                Threads[thread][start]['end'] = end
-                Threads[thread][start]['cpu'] = cpu
-                Threads[thread][start]['predict_start'] = predict_start
-                Threads[thread][start]['predict_cost'] = predict_cost
-
-                if 'elapsed' not in Mtasks[mtask]:
-                    Mtasks[mtask] = {'end': 0, 'elapsed': 0}
-                Mtasks[mtask]['thread'] = thread
-                Mtasks[mtask]['elapsed'] += elapsed_time
-                Mtasks[mtask]['predict_start'] = predict_start
-                Mtasks[mtask]['predict_cost'] = predict_cost
-                Mtasks[mtask]['end'] = max(Mtasks[mtask]['end'], end)
-            elif re_eval.match(line):
-                match = re_eval.match(line)
-                start = int(match.group(1))
-                elapsed_time = int(match.group(2))
-                Evals[start]['start'] = start
-                Evals[start]['end'] = start + elapsed_time
-            elif re_loop.match(line):
-                match = re_loop.match(line)
-                start = int(match.group(1))
-                elapsed_time = int(match.group(2))
-                EvalLoops[start]['start'] = start
-                EvalLoops[start]['end'] = start + elapsed_time
-            elif re.match(r'^VLPROFTHREAD', line):
-                None  # pylint: disable=pointless-statement
+            recordMatch = re_record.match(line)
+            if recordMatch:
+                kind, tick, payload = recordMatch.groups()
+                tick = int(tick)
+                payload = payload.strip()
+                if kind == "EVAL_BEGIN":
+                    Evals[tick]['start'] = tick
+                    lastEvalBeginTick = tick
+                elif kind == "EVAL_END":
+                    Evals[lastEvalBeginTick]['end'] = tick
+                    lastEvalBeginTick = None
+                elif kind == "EVAL_LOOP_BEGIN":
+                    EvalLoops[tick]['start'] = tick
+                    lastEvalLoopBeginTick = tick
+                elif kind == "EVAL_LOOP_END":
+                    EvalLoops[lastEvalLoopBeginTick]['end'] = tick
+                    lastEvalLoopBeginTick = None
+                elif kind == "MTASK_BEGIN":
+                    mtask, predict_start, ecpu = re_payload_mtaskBegin.match(
+                        payload).groups()
+                    mtask = int(mtask)
+                    predict_start = int(predict_start)
+                    ecpu = int(ecpu)
+                    Threads[thread][tick]['mtask'] = mtask
+                    Threads[thread][tick]['predict_start'] = predict_start
+                    Threads[thread][tick]['cpu'] = ecpu
+                    if 'elapsed' not in Mtasks[mtask]:
+                        Mtasks[mtask] = {'end': 0, 'elapsed': 0}
+                    Mtasks[mtask]['begin'] = tick
+                    Mtasks[mtask]['thread'] = thread
+                    Mtasks[mtask]['predict_start'] = predict_start
+                elif kind == "MTASK_END":
+                    mtask, predict_cost = re_payload_mtaskEnd.match(
+                        payload).groups()
+                    mtask = int(mtask)
+                    predict_cost = int(predict_cost)
+                    begin = Mtasks[mtask]['begin']
+                    Threads[thread][begin]['end'] = tick
+                    Threads[thread][begin]['predict_cost'] = predict_cost
+                    Mtasks[mtask]['elapsed'] += tick - begin
+                    Mtasks[mtask]['predict_cost'] = predict_cost
+                    Mtasks[mtask]['end'] = max(Mtasks[mtask]['end'], tick)
+                elif Args.debug:
+                    print("-Unknown execution trace record: %s" % line)
+            elif re_thread.match(line):
+                thread = int(re_thread.match(line).group(1))
+            elif re.match(r'^VLPROF(THREAD|VERSION)', line):
+                pass
            elif re_arg1.match(line):
                match = re_arg1.match(line)
                Global['args'][match.group(1)] = match.group(2)
@@ -105,7 +118,7 @@ def read_data(filename):
                value = re.sub(r'\s+$', '', value)
                Global['cpuinfo'][cpu][term] = value
            elif re.match(r'^#', line):
-                None  # pylint: disable=pointless-statement
+                pass
            elif Args.debug:
                print("-Unk: %s" % line)
            # TODO -- this is parsing text printed by a client.
@@ -131,11 +144,13 @@ def report():
        plus = "+" if re.match(r'^\+', arg) else " "
        print("  %s%s%s" % (arg, plus, Global['args'][arg]))

-    nthreads = len(Threads)
+    nthreads = int(Global['stats']['threads'])
    Global['cpus'] = {}
    for thread in Threads:
        # Make potentially multiple characters per column
        for start in Threads[thread]:
+            if not Threads[thread][start]:
+                continue
            cpu = Threads[thread][start]['cpu']
            elapsed = Threads[thread][start]['end'] - start
            if cpu not in Global['cpus']:
@@ -169,74 +184,79 @@ def report():
    print("\nAnalysis:")
    print("  Total threads             = %d" % nthreads)
    print("  Total mtasks              = %d" % len(Mtasks))
-    ncpus = len(Global['cpus'])
+    ncpus = max(len(Global['cpus']), 1)
    print("  Total cpus used           = %d" % ncpus)
-    print("  Total yields              = %d" % int(Global['stats']['yields']))
+    print("  Total yields              = %d" %
+          int(Global['stats'].get('yields', 0)))
    print("  Total evals               = %d" % len(Evals))
    print("  Total eval loops          = %d" % len(EvalLoops))
-    print("  Total eval time           = %d rdtsc ticks" %
-          Global['measured_last_end'])
-    print("  Longest mtask time        = %d rdtsc ticks" % long_mtask_time)
-    print("  All-thread mtask time     = %d rdtsc ticks" %
-          measured_mt_mtask_time)
-    long_efficiency = long_mtask_time / (Global.get('measured_last_end', 1)
-                                         or 1)
-    print("  Longest-thread efficiency = %0.1f%%" % (long_efficiency * 100.0))
-    mt_efficiency = measured_mt_mtask_time / (
-        Global.get('measured_last_end', 1) * nthreads or 1)
-    print("  All-thread efficiency     = %0.1f%%" % (mt_efficiency * 100.0))
-    print("  All-thread speedup        = %0.1f" % (mt_efficiency * nthreads))
-    if Global['rdtsc_cycle_time'] > 0:
-        ut = measured_mt_mtask_time / Global['rdtsc_cycle_time']
-        print("tot_mtask_cpu=" + measured_mt_mtask_time + " cyc=" +
-              Global['rdtsc_cycle_time'] + " ut=" + ut)
+    if Mtasks:
+        print("  Total eval time           = %d rdtsc ticks" %
+              Global['measured_last_end'])
+        print("  Longest mtask time        = %d rdtsc ticks" % long_mtask_time)
+        print("  All-thread mtask time     = %d rdtsc ticks" %
+              measured_mt_mtask_time)
+        long_efficiency = long_mtask_time / (Global.get(
+            'measured_last_end', 1) or 1)
+        print("  Longest-thread efficiency = %0.1f%%" %
+              (long_efficiency * 100.0))
+        mt_efficiency = measured_mt_mtask_time / (
+            Global.get('measured_last_end', 1) * nthreads or 1)
+        print("  All-thread efficiency     = %0.1f%%" %
+              (mt_efficiency * 100.0))
+        print("  All-thread speedup        = %0.1f" %
+              (mt_efficiency * nthreads))
+        if Global['rdtsc_cycle_time'] > 0:
+            ut = measured_mt_mtask_time / Global['rdtsc_cycle_time']
+            print("tot_mtask_cpu=" + measured_mt_mtask_time + " cyc=" +
+                  Global['rdtsc_cycle_time'] + " ut=" + ut)

-    predict_mt_efficiency = predict_mt_mtask_time / (
-        Global.get('predict_last_end', 1) * nthreads or 1)
-    print("\nPrediction (what Verilator used for scheduling):")
-    print("  All-thread efficiency     = %0.1f%%" %
-          (predict_mt_efficiency * 100.0))
-    print("  All-thread speedup        = %0.1f" %
-          (predict_mt_efficiency * nthreads))
+        predict_mt_efficiency = predict_mt_mtask_time / (
+            Global.get('predict_last_end', 1) * nthreads or 1)
+        print("\nPrediction (what Verilator used for scheduling):")
+        print("  All-thread efficiency     = %0.1f%%" %
+              (predict_mt_efficiency * 100.0))
+        print("  All-thread speedup        = %0.1f" %
+              (predict_mt_efficiency * nthreads))

-    p2e_ratios = []
-    min_p2e = 1000000
-    min_mtask = None
-    max_p2e = -1000000
-    max_mtask = None
+        p2e_ratios = []
+        min_p2e = 1000000
+        min_mtask = None
+        max_p2e = -1000000
+        max_mtask = None

-    for mtask in sorted(Mtasks.keys()):
-        if Mtasks[mtask]['elapsed'] > 0:
-            if Mtasks[mtask]['predict_cost'] == 0:
-                Mtasks[mtask]['predict_cost'] = 1  # don't log(0) below
-            p2e_ratio = math.log(Mtasks[mtask]['predict_cost'] /
-                                 Mtasks[mtask]['elapsed'])
-            p2e_ratios.append(p2e_ratio)
+        for mtask in sorted(Mtasks.keys()):
+            if Mtasks[mtask]['elapsed'] > 0:
+                if Mtasks[mtask]['predict_cost'] == 0:
+                    Mtasks[mtask]['predict_cost'] = 1  # don't log(0) below
+                p2e_ratio = math.log(Mtasks[mtask]['predict_cost'] /
+                                     Mtasks[mtask]['elapsed'])
+                p2e_ratios.append(p2e_ratio)

-            if p2e_ratio > max_p2e:
-                max_p2e = p2e_ratio
-                max_mtask = mtask
-            if p2e_ratio < min_p2e:
-                min_p2e = p2e_ratio
-                min_mtask = mtask
+                if p2e_ratio > max_p2e:
+                    max_p2e = p2e_ratio
+                    max_mtask = mtask
+                if p2e_ratio < min_p2e:
+                    min_p2e = p2e_ratio
+                    min_mtask = mtask

-    print("\nStatistics:")
-    print("  min log(p2e) = %0.3f" % min_p2e, end="")
-    print("  from mtask %d (predict %d," %
-          (min_mtask, Mtasks[min_mtask]['predict_cost']),
-          end="")
-    print(" elapsed %d)" % Mtasks[min_mtask]['elapsed'])
-    print("  max log(p2e) = %0.3f" % max_p2e, end="")
-    print("  from mtask %d (predict %d," %
-          (max_mtask, Mtasks[max_mtask]['predict_cost']),
-          end="")
-    print(" elapsed %d)" % Mtasks[max_mtask]['elapsed'])
+        print("\nMTask statistics:")
+        print("  min log(p2e) = %0.3f" % min_p2e, end="")
+        print("  from mtask %d (predict %d," %
+              (min_mtask, Mtasks[min_mtask]['predict_cost']),
+              end="")
+        print(" elapsed %d)" % Mtasks[min_mtask]['elapsed'])
+        print("  max log(p2e) = %0.3f" % max_p2e, end="")
+        print("  from mtask %d (predict %d," %
+              (max_mtask, Mtasks[max_mtask]['predict_cost']),
+              end="")
+        print(" elapsed %d)" % Mtasks[max_mtask]['elapsed'])

-    stddev = statistics.pstdev(p2e_ratios)
-    mean = statistics.mean(p2e_ratios)
-    print("  mean = %0.3f" % mean)
-    print("  stddev = %0.3f" % stddev)
-    print("  e ^ stddev = %0.3f" % math.exp(stddev))
+        stddev = statistics.pstdev(p2e_ratios)
+        mean = statistics.mean(p2e_ratios)
+        print("  mean = %0.3f" % mean)
+        print("  stddev = %0.3f" % stddev)
+        print("  e ^ stddev = %0.3f" % math.exp(stddev))

    report_cpus()

@@ -298,7 +318,7 @@ def report_cpus():

 def write_vcd(filename):
    print("Writing %s" % filename)
-    with open(filename, "w") as fh:
+    with open(filename, "w", encoding="utf8") as fh:
        vcd = {
            'values':
            collections.defaultdict(lambda: {}),  # {<time>}{<code>} = value
@@ -375,44 +395,45 @@ def write_vcd(filename):
            vcd['values'][eval_start][elcode] = n
            vcd['values'][eval_end][elcode] = None

-        # Predicted graph
-        for eval_start in EvalLoops:
-            eval_end = EvalLoops[eval_start]['end']
-            # Compute scale so predicted graph is of same width as eval
-            measured_scaling = (eval_end -
-                                eval_start) / Global['predict_last_end']
-            # Predict mtasks that fill the time the eval occupied
-            for mtask in Mtasks:
-                thread = Mtasks[mtask]['thread']
-                pred_scaled_start = eval_start + int(
-                    Mtasks[mtask]['predict_start'] * measured_scaling)
-                pred_scaled_end = eval_start + int(
-                    (Mtasks[mtask]['predict_start'] +
-                     Mtasks[mtask]['predict_cost']) * measured_scaling)
-                if pred_scaled_start == pred_scaled_end:
-                    continue
+        if Mtasks:
+            # Predicted graph
+            for eval_start in EvalLoops:
+                eval_end = EvalLoops[eval_start]['end']
+                # Compute scale so predicted graph is of same width as eval
+                measured_scaling = (eval_end -
+                                    eval_start) / Global['predict_last_end']
+                # Predict mtasks that fill the time the eval occupied
+                for mtask in Mtasks:
+                    thread = Mtasks[mtask]['thread']
+                    pred_scaled_start = eval_start + int(
+                        Mtasks[mtask]['predict_start'] * measured_scaling)
+                    pred_scaled_end = eval_start + int(
+                        (Mtasks[mtask]['predict_start'] +
+                         Mtasks[mtask]['predict_cost']) * measured_scaling)
+                    if pred_scaled_start == pred_scaled_end:
+                        continue

-                sig = "predicted_thread%d_mtask" % thread
-                if sig not in vcd['sigs']['predicted_threads']:
-                    vcd['sigs']['predicted_threads'][sig] = code
-                    code += 1
-                mcode = vcd['sigs']['predicted_threads'][sig]
+                    sig = "predicted_thread%d_mtask" % thread
+                    if sig not in vcd['sigs']['predicted_threads']:
+                        vcd['sigs']['predicted_threads'][sig] = code
+                        code += 1
+                    mcode = vcd['sigs']['predicted_threads'][sig]

-                vcd['values'][pred_scaled_start][mcode] = mtask
-                vcd['values'][pred_scaled_end][mcode] = None
+                    vcd['values'][pred_scaled_start][mcode] = mtask
+                    vcd['values'][pred_scaled_end][mcode] = None

-                parallelism['predicted'][pred_scaled_start] += 1
-                parallelism['predicted'][pred_scaled_end] -= 1
+                    parallelism['predicted'][pred_scaled_start] += 1
+                    parallelism['predicted'][pred_scaled_end] -= 1

-        # Parallelism graph
-        for measpred in ('measured', 'predicted'):
-            vcd['sigs']['Stats']["%s_parallelism" % measpred] = code
-            pcode = code
-            code += 1
-            value = 0
-            for time in sorted(parallelism[measpred].keys()):
-                value += parallelism[measpred][time]
-                vcd['values'][time][pcode] = value
+            # Parallelism graph
+            for measpred in ('measured', 'predicted'):
+                vcd['sigs']['Stats']["%s_parallelism" % measpred] = code
+                pcode = code
+                code += 1
+                value = 0
+                for time in sorted(parallelism[measpred].keys()):
+                    value += parallelism[measpred][time]
+                    vcd['values'][time][pcode] = value

        # Create output file
        fh.write("$version Generated by verilator_gantt $end\n")
@@ -454,16 +475,16 @@ def write_vcd(filename):
 parser = argparse.ArgumentParser(
    allow_abbrev=False,
    formatter_class=argparse.RawDescriptionHelpFormatter,
-    description="""Create Gantt chart of multi-threaded execution""",
-    epilog=
-    """Verilator_gantt creates a visual representation to help analyze Verilator
+    description="""Create Gantt chart of multi-threaded execution.
+
+Verilator_gantt creates a visual representation to help analyze Verilator
 #xmultithreaded simulation performance, by showing when each macro-task
 #xstarts and ends, and showing when each thread is busy or idle.

 For documentation see
-https://verilator.org/guide/latest/exe_verilator_gantt.html
-
-Copyright 2018-2021 by Wilson Snyder. This program is free software; you
+https://verilator.org/guide/latest/exe_verilator_gantt.html""",
+    epilog=
+    """Copyright 2018-2023 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
@@ -476,10 +497,10 @@ parser.add_argument('--no-vcd',
                    action='store_true')
 parser.add_argument('--vcd',
                    help='filename for vcd outpue',
-                    default='profile_threads.vcd')
+                    default='profile_exec.vcd')
 parser.add_argument('filename',
-                    help='input profile_threads.dat filename to process',
-                    default='profile_threads.dat')
+                    help='input profile_exec.dat filename to process',
+                    default='profile_exec.dat')

 Args = parser.parse_args()

@@ -1,20 +1,29 @@
-#!/usr/bin/env perl
-# DESCRIPTION: Print include statements for each ARGV
+#!/usr/bin/env python3
+# pylint: disable=C0114,C0209
+#
+# Copyright 2003-2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify the Verilator internals under the terms
+# of either the GNU Lesser General Public License Version 3 or the Perl
+# Artistic License Version 2.0.
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 ######################################################################

-require 5.005;
-use warnings;
-print "// DESCR" . "IPTION: Generated by verilator_includer via makefile\n";
-foreach my $param (@ARGV) {
-    if ($param =~ /^-D([^=]+)=(.*)/) {
-        print "#define $1 $2\n";
-    } else {
-        print "#include \"$param\"\n";
-    }
-}
+import re
+import sys
+
+print("// DESCR" + "IPTION: Generated by verilator_includer via makefile")
+
+re_arg_d = re.compile(r'^-D([^=]+)=(.*)')
+
+for arg in sys.argv[1:]:
+    match_d = re_arg_d.match(arg)
+    if match_d:
+        print("#define %s %s" % (match_d.group(1), match_d.group(2)))
+    else:
+        print("#include \"%s\"" % (arg))
+
+######################################################################
+# Local Variables:
+# compile-command: "./verilator_includer -Ddef=value -Ddef2=value2 file1.h file2.h"
+# End:
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0116,R0914,R0912,R0915,eval-used
+# pylint: disable=C0103,C0114,C0116,C0209,R0914,R0912,R0915,eval-used
 ######################################################################

 import argparse
@@ -13,7 +13,7 @@ import re
 def profcfunc(filename):
    funcs = {}

-    with open(filename) as fh:
+    with open(filename, "r", encoding="utf8") as fh:

        for line in fh:
            #                  %time      cumesec   selfsec     calls     {stuff}   name
@@ -67,16 +67,15 @@ def profcfunc(filename):
    groups['design'] = collections.defaultdict(lambda: 0)
    groups['module'] = collections.defaultdict(lambda: 0)

-    for func in funcs:
-        pct = funcs[func]['pct']
+    for func, func_item in funcs.items():
+        pct = func_item['pct']
        vfunc = func

        funcarg = re.sub(r'^.*\(', '', func)

        design = None
-        for vde in verilated_mods:
-            if verilated_mods[vde].match(func) or verilated_mods[vde].match(
-                    funcarg):
+        for vde, vde_item in verilated_mods.items():
+            if vde_item.match(func) or vde_item.match(funcarg):
                design = vde
                break

@@ -114,12 +113,12 @@ def profcfunc(filename):
            groups['module']['C++'] += pct

        if vfunc not in vfuncs:
-            vfuncs[vfunc] = funcs[func]
+            vfuncs[vfunc] = func_item
            vfuncs[vfunc]['design'] = vdesign
        else:
-            vfuncs[vfunc]['pct'] += funcs[func]['pct']
-            vfuncs[vfunc]['calls'] += funcs[func]['calls']
-            vfuncs[vfunc]['sec'] += funcs[func]['sec']
+            vfuncs[vfunc]['pct'] += func_item['pct']
+            vfuncs[vfunc]['calls'] += func_item['calls']
+            vfuncs[vfunc]['sec'] += func_item['sec']

    for ftype in ['type', 'design', 'module']:
        missing = 100
@@ -136,9 +135,9 @@ def profcfunc(filename):
        print()

    design_width = 1
-    for func in vfuncs:
-        if design_width < len(vfuncs[func]['design']):
-            design_width = len(vfuncs[func]['design'])
+    for func, func_item in vfuncs.items():
+        if design_width < len(func_item['design']):
+            design_width = len(func_item['design'])

    print("Verilog code profile:")
    print("   These are split into three categories:")
@@ -172,17 +171,17 @@ def profcfunc(filename):
 parser = argparse.ArgumentParser(
    allow_abbrev=False,
    formatter_class=argparse.RawDescriptionHelpFormatter,
-    description="""Read gprof report created with --prof-cfuncs""",
-    epilog=
-    """Verilator_profcfunc reads a profile report created by gprof.  The names of
+    description="""Read gprof report created with --prof-cfuncs.
+
+Verilator_profcfunc reads a profile report created by gprof.  The names of
 the functions are then transformed, assuming the user used Verilator's
 --prof-cfuncs, and a report printed showing the percentage of time, etc,
 in each Verilog block.

 For documentation see
-https://verilator.org/guide/latest/exe_verilator_profcfunc.html
-
-Copyright 2002-2021 by Wilson Snyder. This program is free software; you
+https://verilator.org/guide/latest/exe_verilator_profcfunc.html""",
+    epilog=
+    """Copyright 2002-2023 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
@@ -19,6 +19,10 @@ set -x

 cd $(dirname "$0")/..

+# Avoid occasional cpan failures "Issued certificate has expired."
+export PERL_LWP_SSL_VERIFY_HOSTNAME=0
+echo "check_certificate = off" >> ~/.wgetrc
+
 fatal() {
  echo "ERROR: $(basename "$0"): $1" >&2; exit 1;
 }
@@ -53,15 +57,24 @@ if [ "$CI_BUILD_STAGE_NAME" = "build" ]; then
  # build Verilator

  if [ "$CI_OS_NAME" = "linux" ]; then
+    sudo apt-get update ||
    sudo apt-get update
-    sudo apt-get install libfl-dev libgoogle-perftools-dev ccache
-    if [ "$CI_RUNS_ON" = "ubuntu-20.04" ]; then
+    sudo apt-get install ccache help2man libfl-dev ||
+    sudo apt-get install ccache help2man libfl-dev
+    if [ "$CI_RUNS_ON" != "ubuntu-22.04" ]; then
+      # Some conflict of libunwind verison on 22.04, can live without it for now
+      sudo apt-get install libgoogle-perftools-dev ||
+      sudo apt-get install libgoogle-perftools-dev
+    fi
+    if [ "$CI_RUNS_ON" = "ubuntu-20.04" ] || [ "$CI_RUNS_ON" = "ubuntu-22.04" ]; then
+      sudo apt-get install libsystemc libsystemc-dev ||
      sudo apt-get install libsystemc libsystemc-dev
    fi
    if [ "$COVERAGE" = 1 ]; then
      yes yes | sudo cpan -fi Parallel::Forker
    fi
    if [ "$CI_M32" = 1 ]; then
+      sudo apt-get install gcc-multilib g++-multilib ||
      sudo apt-get install gcc-multilib g++-multilib
    fi
  elif [ "$CI_OS_NAME" = "osx" ]; then
@@ -82,13 +95,23 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
  # run the tests

  if [ "$CI_OS_NAME" = "linux" ]; then
+    sudo apt-get update ||
    sudo apt-get update
    # libfl-dev needed for internal coverage's test runs
+    sudo apt-get install gdb gtkwave lcov libfl-dev ccache ||
    sudo apt-get install gdb gtkwave lcov libfl-dev ccache
-    if [ "$CI_RUNS_ON" = "ubuntu-20.04" ]; then
+    # Required for test_regress/t/t_dist_attributes.pl
+    if [ "$CI_RUNS_ON" = "ubuntu-22.04" ]; then
+      sudo apt-get install libclang-dev ||
+      sudo apt-get install libclang-dev
+      pip3 install clang==14.0
+    fi
+    if [ "$CI_RUNS_ON" = "ubuntu-20.04" ] || [ "$CI_RUNS_ON" = "ubuntu-22.04" ]; then
+      sudo apt-get install libsystemc-dev ||
      sudo apt-get install libsystemc-dev
    fi
    if [ "$CI_M32" = 1 ]; then
+      sudo apt-get install lib32z1-dev gcc-multilib g++-multilib ||
      sudo apt-get install lib32z1-dev gcc-multilib g++-multilib
    fi
  elif [ "$CI_OS_NAME" = "osx" ]; then
@@ -69,7 +69,7 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then

  if [ "$CI_OS_NAME" = "osx" ]; then
    export VERILATOR_TEST_NO_GDB=1  # Pain to get GDB to work on OS X
-    # TODO below may no longer be requried as configure checks for -pg
+    # TODO below may no longer be required as configure checks for -pg
    export VERILATOR_TEST_NO_GPROF=1  # Apple Clang has no -pg
    # export PATH="/Applications/gtkwave.app/Contents/Resources/bin:$PATH" # fst2vcd
    file bin/verilator_bin
@@ -85,7 +85,7 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then
    "$MAKE" -j "$NPROC" -k
  elif [ "$CI_OS_NAME" = "freebsd" ]; then
    export VERILATOR_TEST_NO_GDB=1 # Disable for now, ideally should run
-    # TODO below may no longer be requried as configure checks for -pg
+    # TODO below may no longer be required as configure checks for -pg
    export VERILATOR_TEST_NO_GPROF=1 # gprof is a bit different on FreeBSD, disable
  fi

@@ -0,0 +1,15 @@
+if (-Not (Test-Path $PWD/../.ccache/win_bison.exe)) {
+	git clone --depth 1 https://github.com/lexxmark/winflexbison
+	cd winflexbison
+	mkdir build
+	cd build
+	cmake .. --install-prefix $PWD/../../../.ccache
+	cmake --build . --config Release
+	cmake --install . --prefix $PWD/../../../.ccache
+	cd ../..
+}
+mkdir build
+cd build
+cmake .. --install-prefix $PWD/../install
+cmake --build . --config Release
+cmake --install . --prefix $PWD/../install
@@ -0,0 +1,10 @@
+cd install
+$Env:VERILATOR_ROOT=$PWD
+cd examples/cmake_tracing_c
+mkdir build
+cd build
+cmake ..
+cmake --build . --config Release
+Release/example.exe
+cd ..
+Remove-Item -path build -recurse
@@ -6,7 +6,7 @@
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

-FROM ubuntu:20.04
+FROM ubuntu:22.04

 RUN apt-get update \
    && DEBIAN_FRONTEND=noninteractive \
@@ -23,6 +23,7 @@ RUN apt-get update \
                        gdb \
                        git \
                        gtkwave \
+                        help2man \
                        libfl2 \
                        libfl-dev \
                        libgoogle-perftools-dev \
@@ -1,3 +1,6 @@
+.. Copyright 2003-2023 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
 Verilator Build Docker Container
 ================================

@@ -8,7 +11,7 @@ Verilator build. It uses the following parameters:

 -  Source revision (default: master)

-  Compiler (GCC 9.3.0, clang 10.0.0, default: 9.3.0)
+-  Compiler (GCC 10.3.0, clang 10.0.0, default: 10.3.0)

 The container is published as ``verilator/verilator-buildenv`` on `docker
 hub
@@ -6,7 +6,7 @@
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

-FROM ubuntu:20.04
+FROM ubuntu:22.04

 RUN apt-get update \
    && DEBIAN_FRONTEND=noninteractive \
@@ -1,3 +1,6 @@
+.. Copyright 2003-2023 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
 Verilator Executable Docker Container
 =====================================

@@ -62,12 +65,11 @@ Internals
 ---------

 The Dockerfile builds Verilator and removes the tree when completed to
-reduce the image size. The entrypoint is set as a wrapper script
+reduce the image size. The entrypoint is a wrapper script
 (``verilator-wrap.sh``). That script 1. calls Verilator, and 2. copies the
 Verilated runtime files to the ``obj_dir`` or the ``-Mdir``
 respectively. This allows the user to have the files to they may later
 build the C++ output with the matching runtime files. The wrapper also
 patches the Verilated Makefile accordingly.

-There is also a hook defined that is run by docker hub via automated
-builds.
+A hook is also defined and run by Docker Hub via automated builds.
@@ -1,6 +1,6 @@
 # DESCRIPTION: codecov.io config
 #
-# Copyright 2020-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2020-2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -1,20 +1,20 @@
 # DESCRIPTION: Process this file with autoconf to produce a configure script.
 #
-# Copyright 2003-2021 by Wilson Snyder. Verilator is free software; you
+# Copyright 2003-2023 by Wilson Snyder. Verilator is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU Lesser
 # General Public License Version 3 or the Perl Artistic License Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

-#AC_INIT([Verilator],[#.### YYYY-MM-DD])
-#AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[4.214 2021-10-17],
-        [https://verilator.org],
-        [verilator],[https://verilator.org])
 # When releasing, also update header of Changes file
 # and commit using "devel release" or "Version bump" message
 # Then 'make maintainer-dist'
+#AC_INIT([Verilator],[#.### YYYY-MM-DD])
+#AC_INIT([Verilator],[#.### devel])
+AC_INIT([Verilator],[5.006 2023-01-22],
+        [https://verilator.org],
+        [verilator],[https://verilator.org])

-AC_CONFIG_HEADER(src/config_build.h)
+AC_CONFIG_HEADERS(src/config_build.h)
 AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc verilator-config.cmake verilator-config-version.cmake)

 # Version
@@ -22,6 +22,8 @@ AC_MSG_RESULT([configuring for $PACKAGE_STRING])
 PACKAGE_VERSION_NUMBER=`AS_ECHO("$PACKAGE_VERSION") | sed 's/ .*//g'`
 AC_SUBST(PACKAGE_VERSION_NUMBER)
 AC_DEFINE_UNQUOTED([PACKAGE_VERSION_NUMBER_STRING],["$PACKAGE_VERSION_NUMBER"],[Package version as a number])
+VERILATOR_VERSION_INTEGER=`AS_ECHO("$PACKAGE_VERSION") | [sed 's/\([0-9]\)\.\([0-9][0-9][0-9]\) .*/\1\2000/g']`
+AC_SUBST(VERILATOR_VERSION_INTEGER)

 # Ignore automake flags passed by Ubuntu builds
 AC_ARG_ENABLE([dependency-tracking],
@@ -110,7 +112,7 @@ AC_MSG_CHECKING(whether to show and stop on compilation warnings)
 AC_ARG_ENABLE([ccwarn],
              [AS_HELP_STRING([--enable-ccwarn],
                              [enable showing and stopping on compilation warnings
-                               in Verilator binrary and Verilated makefiles])],
+                               in Verilator binary and Verilated makefiles])],
              [case "${enableval}" in
                yes) CFG_WITH_CCWARN=yes ;;
                no)  CFG_WITH_CCWARN=no ;;
@@ -143,10 +145,10 @@ AC_SUBST(CFG_WITH_LONGTESTS)
 AC_MSG_RESULT($CFG_WITH_LONGTESTS)

 # Compiler flags (ensure they are not empty to avoid configure defaults)
-CFLAGS+=" "
-CPPFLAGS+=" "
-CXXFLAGS+=" "
-LDFLAGS+=" "
+CFLAGS="$CFLAGS "
+CPPFLAGS="$CPPFLAGS "
+CXXFLAGS="$CXXFLAGS "
+LDFLAGS="$LDFLAGS "

 # Checks for programs.
 AC_PROG_CC
@@ -346,14 +348,14 @@ AC_SUBST(CFG_CXXFLAGS_PROFILE)

 # Flag to select newest language standard supported
 # Macros work such that first option that passes is the one we take
-# Currently enabled c++14 due to packaged SystemC dependency
-# c++14 is the newest that Verilator is regressed to support
+# Currently enable c++17/c++14 due to packaged SystemC dependency
+# c++17 is the newest that Verilator is regularly tested to support
 # c++11 is the oldest that Verilator supports
-# gnu is requried for Cygwin to compile verilated.h successfully
+# gnu is required for Cygwin to compile verilated.h successfully
 #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++20)
 #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++20)
-#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++17)
-#_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++17)
+_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++17)
+_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++17)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++14)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++14)
 _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++11)
@@ -368,6 +370,36 @@ _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_WEXTRA,-Wlogical-op)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_WEXTRA,-Wthread-safety)
 AC_SUBST(CFG_CXXFLAGS_WEXTRA)

+# Flags for coroutine support for dynamic scheduling
+_MY_CXX_CHECK_IFELSE(
+  -fcoroutines-ts,
+  [CFG_CXXFLAGS_COROUTINES="-fcoroutines-ts"],
+  [CFG_CXXFLAGS_COROUTINES="-fcoroutines"])
+AC_SUBST(CFG_CXXFLAGS_COROUTINES)
+
+# HAVE_COROUTINES
+# Check if coroutines are supported at all
+AC_MSG_CHECKING([whether coroutines are supported by $CXX])
+ACO_SAVE_CXXFLAGS="$CXXFLAGS"
+CXXFLAGS="$CXXFLAGS $CFG_CXXFLAGS_COROUTINES"
+AC_LINK_IFELSE(
+    [AC_LANG_PROGRAM([
+#ifdef __clang__
+#define __cpp_impl_coroutine 1
+#endif
+#include <coroutine>
+    ],[[]])],
+    [_my_result=yes
+     AC_DEFINE([HAVE_COROUTINES],[1],[Defined if coroutines are supported by $CXX])],
+    [AC_LINK_IFELSE(
+        [AC_LANG_PROGRAM([#include <experimental/coroutine>],[[]])],
+        [_my_result=yes
+         AC_DEFINE([HAVE_COROUTINES],[1],[Defined if coroutines are supported by $CXX])],
+        [_my_result=no])])
+AC_MSG_RESULT($_my_result)
+CXXFLAGS="$ACO_SAVE_CXXFLAGS"
+AC_SUBST(HAVE_COROUTINES)
+
 # Flags for compiling Verilator internals including parser always
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Qunused-arguments)
 _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-faligned-new)
@@ -496,15 +528,22 @@ AC_DEFUN([_MY_CXX_CHECK_CXX_VER],
     [_my_result=no])
   ])

+# Add $CFG_CXXFLAGS_STD only if can't compile correctly otherwise,
+# as adding std= when not needed can cause errors with the C++ std library.
+CFG_CXXFLAGS_STD=$CFG_CXXFLAGS_STD_NEWEST
 AC_MSG_CHECKING(whether $CXX supports C++11)
 _MY_CXX_CHECK_CXX_VER()
 AC_MSG_RESULT($_my_result)
 if test "$_my_result" = "no" ; then
-   CXXFLAGS="$CXXFLAGS $CFG_CXXFLAGS_STD_NEWEST"
-   CFG_CXX_FLAGS_CMAKE="$CFG_CXX_FLAGS_CMAKE $CFG_CXXFLAGS_STD_NEWEST"
-   AC_MSG_CHECKING(whether $CXX supports C++11 with $CFG_CXXFLAGS_STD_NEWEST)
+   CXXFLAGS="$CXXFLAGS $CFG_CXXFLAGS_STD"
+   CFG_CXX_FLAGS_CMAKE="$CFG_CXX_FLAGS_CMAKE $CFG_CXXFLAGS_STD"
+   AC_MSG_CHECKING(whether $CXX supports C++11 with $CFG_CXXFLAGS_STD)
   _MY_CXX_CHECK_CXX_VER()
   AC_MSG_RESULT($_my_result)
+else
+   # CFG_CXXFLAGS_STD is also propagated to include/verilated.mk.in
+   # make sure we use the same std flag while compiling verilator and verilated design
+   CFG_CXXFLAGS_STD=""
 fi
 if test "$_my_result" = "no" ; then
   AC_MSG_NOTICE([[]])
@@ -513,6 +552,7 @@ if test "$_my_result" = "no" ; then
 Verilator requires a C++11 or newer compiler.]])

 fi
+AC_SUBST(CFG_CXXFLAGS_STD)

 # Checks for library functions.
 AC_CHECK_MEMBER([struct stat.st_mtim.tv_nsec],
@@ -2,3 +2,4 @@
 *.html
 *.pdf
 _build
+guide/spelling.txt
@@ -44,15 +44,10 @@ Did you write a patch that fixes a bug?
  - Have your patch include the addition of your name to `docs/CONTRIBUTORS
    <CONTRIBUTORS>`__ (preferred).

-  - Use "git -s" as part of your commit. This adds a "signed-of-by"
-    attribute which will certify your contribution as described in the
-    `Signed-of-By convention
-    <https://github.com/wking/signed-off-by/blob/master/Documentation/SubmittingPatches>`__.
-
  - Email, or post in an issue a statement that you certify your
    contributions.

-  - In any of these cases your name will be added to `docs/CONTRIBUTORS
+  - In any of these cases, your name will be added to `docs/CONTRIBUTORS
    <CONTRIBUTORS>`__ and you are agreeing all future contributions are
    also certified.

@@ -64,7 +59,7 @@ Did you write a patch that fixes a bug?
  Creative Commons Public Domain (CC0), unless you request otherwise or
  put a GNU/Artistic license on your file.

- Most important is we get your patch. If you’d like to clean up
+- Most important is we get your patch. If you'd like to clean up
  indentation and related issues ahead of our feedback, that is
  appreciated; please see the coding conventions in `docs/internals
  <internals.rst>`__.
@@ -3,12 +3,18 @@ under the Developer Certificate of Origin (https://developercertificate.org/).

 Please see the Verilator manual for 200+ additional contributors. Thanks to all.

+Adrien Le Masle
 Ahmed El-Mahmoudy
+Aleksander Kiryk
 Alex Chadwick
 Àlex Torregrosa
+Aliaksei Chapyzhenka
 Ameya Vikram Singh
 Andreas Kuster
+Andrew Nolte
+Arkadiusz Kozdra
 Chris Randall
+Chuxuan Wang
 Conor McCullough
 Dan Petrisko
 Daniel Bates
@@ -16,6 +22,7 @@ David Horton
 David Metz
 David Stanford
 David Turner
+Drew Ranck
 Drew Taussig
 Driss Hafdi
 Edgar E. Iglesias
@@ -26,51 +33,76 @@ Garrett Smith
 Geza Lore
 Gianfranco Costamagna
 Glen Gibb
+Gökçe Aydos
 Graham Rushton
+Guokai Chen
+Gustav Svensk
+G-A. Kamendje
 Harald Heckmann
 Howard Su
 Huang Rui
+Huanghuang Zhou
+HungMingWu
 HyungKi Jeong
 Iru Cai
 Ivan Vnučec
+Ilya Barkov
 Iztok Jeras
+Jake Merdich
 James Hanlon
 James Hutchinson
 James Pallister
+James Shi
 Jamey Hicks
+Jamie Iles
 Jan Van Winkel
 Jean Berniolles
 Jeremy Bennett
+Jevin Sweval
+Jiacheng Qian
+Jiuyang Liu
+Joey Liu
 John Coiner
 John Demme
 Jonathan Drolet
 Josh Redford
+Julie Schwartz
 Julien Margetts
 Kaleb Barrett
+Kamil Rakoczy
 Kanad Kanhere
 Keith Colbert
 Kevin Kiningham
+Kritik Bhimani
 Krzysztof Bieganski
 Kuba Ober
+Larry Doolittle
 Ludwig Rogiers
 Lukasz Dalek
 Maarten De Braekeleer
 Maciej Sobkowski
+Marcel Chang
 Marco Widmer
+Mariusz Glebocki
 Markus Krause
 Marlon James
 Marshal Qiao
 Martin Schmidt
+Martin Stadler
 Matthew Ballance
 Michael Killough
+Michaël Lefebvre
 Mike Popoloski
 Miodrag Milanović
+Mladen Slijepcevic
 Morten Borup Petersen
+Mostafa Gamal
 Nandu Raj
 Nathan Kohagen
 Nathan Myers
 Patrick Stewart
 Paul Wright
+Pawel Sagan
 Peter Horvath
 Peter Monsson
 Philipp Wagner
@@ -79,8 +111,10 @@ Pieter Kapsenberg
 Piotr Binkowski
 Qingyao Sun
 Rafal Kapuscik
+Raynard Qiao
 Richard Myers
 Rupert Swarbrick
+Ryszard Rozak
 Samuel Riedel
 Sean Cross
 Sebastien Van Cauwenberghe
@@ -88,20 +122,29 @@ Sergi Granell
 Stefan Wallentowitz
 Stephen Henry
 Steven Hugg
+Sören Tempel
+Teng Huang
 Tim Snyder
 Tobias Rosenkranz
 Tobias Wölfel
 Todd Strader
 Tomasz Gorochowik
+Topa Topino
 Tymoteusz Blazejczyk
 Udi Finkelstein
 Unai Martinez-Corral
+Varun Koyyalagunta
 Vassilis Papaefstathiou
 Veripool API Bot
 Victor Besyakov
+William D. Jones
 Wilson Snyder
+Xi Zhang
+Yinan Xu
+Yoda Lee
 Yossi Nivin
 Yuri Victorovich
 Yutetsu TAKATSUKASA
+Yu-Sheng Lin
 Yves Mathieu
 Zhanglei Wang
@@ -5,7 +5,7 @@
 #
 # Code available from: https://verilator.org
 #
-# Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+# Copyright 2003-2023 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -35,6 +35,7 @@ default:
 # Intermediate rules

 vl-extract: ../bin/verilator ../Changes
+	ln -sf ../spelling.txt guide/spelling.txt
 	mkdir -p _build/gen
 	$(PYTHON3) bin/vl_sphinx_extract ../bin/verilator
 	sed 's/`/\&96;/g' < ../Changes > _build/gen/Changes
@@ -77,6 +78,7 @@ clean mostlyclean distclean maintainer-clean::
 	rm -f *.pg *.pgs *.toc *.tp *.tps *.vr *.vrs *.idx
 	rm -f *.ev *.evs *.ov *.ovs *.cv *.cvs *.ma *.mas
 	rm -f *.tex
+	rm -f guide/spelling.txt

 distclean maintainer-clean::
 	rm -f *.info* *.1 *.html *.pdf $(INFOS)
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0112,C0114,C0115,C0116,C0301,R0201,R0903
+# pylint: disable=C0112,C0114,C0115,C0116,C0209,C0301,R0201,R0903
 # -*- Python -*- See copyright, etc below
 ######################################################################

@@ -14,7 +14,7 @@ class VlSphinxExtract:
    SkipBasenames = {}

    def process(self, filename):
-        with open(filename) as fhr:
+        with open(filename, "r", encoding="utf8") as fhr:
            fhw = None
            for line in fhr:
                # =for VL_SPHINX_EXTRACT "file_to_write_to"
@@ -22,7 +22,7 @@ class VlSphinxExtract:
                if match:
                    outname = match.group(1)
                    print("Writing %s" % outname)
-                    fhw = open(outname, "w")
+                    fhw = open(outname, "w", encoding="utf8")  # pylint: disable=consider-using-with
                    fhw.write(
                        ".. comment: generated by vl_sphinx_extract from " +
                        filename + "\n")
@@ -40,7 +40,7 @@ parser = argparse.ArgumentParser(
    formatter_class=argparse.RawDescriptionHelpFormatter,
    description="""Read a file and extract documentation data.""",
    epilog=
-    """ Copyright 2021-2021 by Wilson Snyder.  This package is free software;
+    """ Copyright 2021-2023 by Wilson Snyder.  This package is free software;
 you can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0112,C0114,C0115,C0116,C0301,R0903
+# pylint: disable=C0112,C0114,C0115,C0116,C0209,C0301,R0903
 # -*- Python -*- See copyright, etc below
 ######################################################################

@@ -27,7 +27,7 @@ class VlSphinxFix:

    def _edit(self, filename):
        is_html = re.search(r'\.(html)$', filename)
-        with open(filename) as fhr:
+        with open(filename, "r", encoding="utf8") as fhr:
            origfile = fhr.read()
            wholefile = origfile
            # Option doesn't like spaces, so we use
@@ -43,7 +43,7 @@ class VlSphinxFix:
                if self.debug:
                    print("Edit %s" % filename)
                tempname = filename + ".tmp"
-                with open(tempname, "w") as fhw:
+                with open(tempname, "w", encoding="utf8") as fhw:
                    fhw.write(wholefile)
                os.rename(tempname, filename)

@@ -55,7 +55,7 @@ parser = argparse.ArgumentParser(
    formatter_class=argparse.RawDescriptionHelpFormatter,
    description="""Post-process Sphinx HTML.""",
    epilog=
-    """ Copyright 2021-2021 by Wilson Snyder.  This package is free software;
+    """ Copyright 2021-2023 by Wilson Snyder.  This package is free software;
 you can redistribute it and/or modify it under the terms of either the GNU
 Lesser General Public License Version 3 or the Perl Artistic License
 Version 2.0.
@@ -1,7 +1,5 @@
 .. comment: generated by t_lint_didnotconverge_bad
 .. code-block::

-   -V{t#,#}+    Vt_lint_didnotconverge_bad___024root___change_request
-   -V{t#,#}+    Vt_lint_didnotconverge_bad___024root___change_request_1
-   -V{t#,#}        CHANGE: t/t_lint_didnotconverge_bad.v:14: a
-   %Error: t/t_lint_didnotconverge_bad.v:7: Verilated model didn't converge
+   -V{t#,#}         'stl' region trigger index 1 is active: @([hybrid] a)
+   %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge.
@@ -1,4 +1,4 @@
 .. comment: generated by t_lint_didnotconverge_nodbg_bad
 .. code-block::

-   %Error: t/t_lint_didnotconverge_bad.v:7: Verilated model didn't converge
+   %Error: t/t_lint_didnotconverge_bad.v:7: Settle region did not converge.
@@ -1,4 +1,4 @@
 .. comment: generated by t_lint_stmtdly_bad
 .. code-block::

-   %Warning-STMTDLY: example.v:1:8 Unsupported: Ignoring delay on this delayed statement.
+   %Warning-STMTDLY: example.v:1:7 Ignoring delay on this statement due to --no-timing
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 ****************
@@ -10,7 +10,7 @@ Revision History
   "Revision History" in the sidebar.

 Changes are contained in the :file:`Changes` file of the distribution, and
-also summarized below.  To subscribe to new versions see `Verilator
+also summarized below.  To subscribe to new versions, see `Verilator
 Announcements <https://github.com/verilator/verilator-announce>`_.

 .. include:: ../_build/gen/Changes
@@ -1,6 +1,7 @@
 # pylint: disable=C0103,C0114,C0116,C0301,E0402,W0622
 #
 # Configuration file for Verilator's Sphinx documentation builder.
+# Copyright 2003-2023 by Wilson Snyder.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 #
 # This file only contains overridden options. For a full list:
@@ -13,6 +14,7 @@ from datetime import datetime
 import os
 import re
 import sys
+
 sys.path.insert(0, os.path.abspath('./_ext'))

 import sphinx_rtd_theme  # pylint: disable=wrong-import-position,
@@ -20,7 +22,7 @@ import sphinx_rtd_theme  # pylint: disable=wrong-import-position,

 def get_vlt_version():
    filename = "../../Makefile"
-    with open(filename) as fh:
+    with open(filename, "r", encoding="utf8") as fh:
        for line in fh:
            match = re.search(r"PACKAGE_VERSION_NUMBER *= *([a-z0-9.]+)", line)
            if match:
@@ -36,7 +38,7 @@ def setup(app):
 # -- Project information

 project = 'Verilator'
-copyright = '2021 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0'
+copyright = '2022 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0'
 author = 'Wilson Snyder'

 # The master toctree document.
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 .. _Connecting:
@@ -51,8 +51,8 @@ also the instance of the top level instance in the design hierarchy (what
 you would refer to with :code:`$root` in SystemVerilog).  This meant that
 all internal variables that were implemented by Verilator in the root scope
 were accessible as members of the model class itself.  Note there were often
-many such variable due to module inlining, including :code:`/* verilator
-public_flat */` items.
+many such variable due to module inlining, including
+:code:`/* verilator public_flat */` items.

 This means that user code that accesses internal signals in the model
 (likely including :code:`/* verilator public_flat */` signals, as they are
@@ -86,58 +86,20 @@ Connecting to C++
 In C++ output mode (:vlopt:`--cc`), the Verilator generated model class is a
 simple C++ class.  The user must write a C++ wrapper and main loop for the
 simulation, which instantiates the model class, and link with the Verilated
-model.  Here is a simple example:
+model.

-.. code-block:: C++
+Refer to ``examples/make_tracing_c`` in the distribution for a detailed
+commented example.

-         #include <verilated.h>          // Defines common routines
-         #include <iostream>             // Need std::cout
-         #include "Vtop.h"               // From Verilating "top.v"
+Top level IO signals are read and written as members of the model.  You
+call the model's :code:`eval()` method to evaluate the model.  When the
+simulation is complete call the model's :code:`final()` method to execute
+any SystemVerilog final blocks, and complete any assertions. If using
+:vlopt:`--timing`, there are two additional functions for checking if
+there are any events pending in the simulation due to delays, and for
+retrieving the simulation time of the next delayed event. See
+:ref:`Evaluation Loop`.

-         Vtop *top;                      // Instantiation of model
-
-         vluint64_t main_time = 0;       // Current simulation time
-         // This is a 64-bit integer to reduce wrap over issues and
-         // allow modulus.  This is in units of the timeprecision
-         // used in Verilog (or from --timescale-override)
-
-         double sc_time_stamp() {        // Called by $time in Verilog
-             return main_time;           // converts to double, to match
-                                         // what SystemC does
-         }
-
-         int main(int argc, char** argv) {
-             Verilated::commandArgs(argc, argv);   // Remember args
-
-             top = new Vtop;             // Create model
-
-             top->reset_l = 0;           // Set some inputs
-
-             while (!Verilated::gotFinish()) {
-                 if (main_time > 10) {
-                     top->reset_l = 1;   // Deassert reset
-                 }
-                 if ((main_time % 10) == 1) {
-                     top->clk = 1;       // Toggle clock
-                 }
-                 if ((main_time % 10) == 6) {
-                     top->clk = 0;
-                 }
-                 top->eval();            // Evaluate model
-                 cout << top->out << endl;       // Read a output
-                 main_time++;            // Time passes...
-             }
-
-             top->final();               // Done simulating
-             //    // (Though this example doesn't get here)
-             delete top;
-         }
-
-
-Note top level IO signals are read and written as members of the model.  You
-call the :code:`eval()` method to evaluate the model.  When the simulation is
-complete call the :code:`final()` method to execute any SystemVerilog final
-blocks, and complete any assertions. See :ref:`Evaluation Loop`.


 Connecting to SystemC
@@ -150,7 +112,7 @@ netlist as an instantiation.
 The SC_MODULE gets the same pinout as the Verilog module, with the
 following type conversions: Pins of a single bit become bool.  Pins 2-32
 bits wide become uint32_t's.  Pins 33-64 bits wide become sc_bv's or
-vluint64_t's depending on the :vlopt:`--no-pins64` option.  Wider pins
+uint64_t's depending on the :vlopt:`--no-pins64` option.  Wider pins
 become sc_bv's.  (Uints simulate the fastest so are used where possible.)

 Model internals, including lower level sub-modules are not pure SystemC
@@ -200,7 +162,7 @@ DPI System Task/Functions
 -------------------------

 Verilator extends the DPI format to allow using the same scheme to
-efficiently add system functions.  Simply use a dollar-sign prefixed system
+efficiently add system functions.  Use a dollar-sign prefixed system
 function name for the import, but note it must be escaped.

 .. code-block:: sv
@@ -257,7 +219,9 @@ with respect to that top level module, then the scope could be set with

     #include "svdpi.h"
     ...
-     svSetScope(svGetScopeFromName("TOP.dut"));
+     const svScope scope = svGetScopeFromName("TOP.dut");
+     assert(scope);  // Check for nullptr if scope not found
+     svSetScope(scope);

 (Remember that Verilator adds a "TOP" to the top of the module hierarchy.)

@@ -422,12 +386,12 @@ accesses the above signal "readme" would be:

 .. code-block:: bash

-     cat >sim_main.cpp <<'<<EOF'
+     cat >sim_main.cpp <<'EOF'
       #include "Vour.h"
       #include "verilated.h"
       #include "verilated_vpi.h"  // Required to get definitions

-       vluint64_t main_time = 0;   // See comments in first example
+       uint64_t main_time = 0;   // See comments in first example
       double sc_time_stamp() { return main_time; }

       void read_and_check() {
@@ -442,16 +406,17 @@ accesses the above signal "readme" would be:
           printf("Value of v: %d\n", v.value.integer);  // Prints "readme"
       }

-       int main(int argc, char** argv, char** env) {
+       int main(int argc, char** argv) {
           Verilated::commandArgs(argc, argv);
-           Vour* top = new Vour;
-           Verilated::internalsDump();  // See scopes to help debug
-           while (!Verilated::gotFinish()) {
+           const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+           const std::unique_ptr<Vour> top{new Vour{contextp.get()}};
+
+           contextp->internalsDump();  // See scopes to help debug
+           while (!contextp->gotFinish()) {
               top->eval();
               VerilatedVpi::callValueCbs();  // For signal callbacks
               read_and_check();
           }
-           delete top;
           return 0;
       }
     EOF
@@ -478,10 +443,25 @@ there is only a single design, you would call :code:`eval_step()` then
 :code:`eval_end_step()`; in fact :code:`eval()` described above is just a
 wrapper which calls these two functions.

+3. If using delays and :vlopt:`--timing`, there are two additional methods
+the user should call:
+
+   * :code:`designp->eventsPending()`, which returns :code:`true` if there are
+     any delayed events pending,
+   * :code:`designp->nextTimeSlot()`, which returns the simulation time of the
+     next delayed event. This method can only be called if
+     :code:`designp->nextTimeSlot()` returned :code:`true`.
+
+Call :code:`eventsPending()` to check if you should continue with the
+simulation, and then :code:`nextTimeSlot()` to move simulation time forward.
+:vlopt:`--main` can be used with :vlopt:`--timing` to generate a basic example
+of a timing-enabled eval loop.
+
 When :code:`eval()` (or :code:`eval_step()`) is called Verilator looks for
 changes in clock signals and evaluates related sequential always blocks,
-such as computing always_ff @ (posedge...) outputs.  Then Verilator
-evaluates combinatorial logic.
+such as computing always_ff @ (posedge...) outputs. With :vlopt:`--timing`, it
+resumes any delayed processes awaiting the current simulation time. Then
+Verilator evaluates combinational logic.

 Note combinatorial logic is not computed before sequential always blocks
 are computed (for speed reasons). Therefore it is best to set any non-clock
@@ -506,7 +486,7 @@ structure.  If a ``VerilatedContext`` is not created prior to creating a
 model, a default global one is created automatically.

 The ``Verilated::`` methods, including the ``Verilated::commandArgs`` call
-shown above, simply call VerilatedContext methods using the default global
+shown above, call VerilatedContext methods using the default global
 VerilatedContext.  (Technically they operate on the last one used by a
 given thread.)  If you are using multiple simulation contexts you should
 not use the Verilated:: methods, and instead always use VerilatedContext
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 *******************************
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 ************************
@@ -11,7 +11,7 @@ Authors
 When possible, please instead report bugs at `Verilator Issues
 <https://verilator.org/issues>`_.

-Primary author is Wilson Snyder <[email protected]>.
+The primary author is Wilson Snyder <[email protected]>.

 Major concepts by Paul Wasson, Duane Galbi, John Coiner, Geza Lore, Yutetsu
 Takatsukasa, and Jie Xu.
@@ -22,122 +22,135 @@ Contributors

 Many people have provided ideas and other assistance with Verilator.

-Verilator is receiving major development support from the `CHIPS Alliance
-<https://chipsalliance.org>`_.
+Verilator is receiving significant development support from the `CHIPS
+Alliance <https://chipsalliance.org>`_, `Antmicro Ltd
+<https://antmicro.com>`_ and `Shunyao CAD <https://shunyaocad.com>`_.

 Previous major corporate sponsors of Verilator, by providing significant
-contributions of time or funds included include: Atmel Corporation, Cavium
+contributions of time or funds include: Atmel Corporation, Cavium
 Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd.,
 Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune
 Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc.,
-and SiCortex Inc.
+SiCortex Inc, and Shunyao CAD.

-The people who have contributed major functionality are: Byron Bradley,
-Jeremy Bennett, Lane Brooks, John Coiner, Duane Galbi, Geza Lore, Todd
-Strader, Stefan Wallentowitz, Paul Wasson, Jie Xu, and Wilson Snyder.
-Major testers included Jeff Dutton, Jonathon Donaldson, Ralf Karge, David
-Hewson, Iztok Jeras, Wim Michiels, Alex Solomatnikov, Sebastien Van
-Cauwenberghe, Gene Weber, and Clifford Wolf.
+The contributors of major functionality are: Krzysztof
+Bieganski, Byron Bradley, Jeremy Bennett, Lane Brooks, John Coiner, Duane
+Galbi, Geza Lore, Todd Strader, Stefan Wallentowitz, Paul Wasson, Jie Xu,
+and Wilson Snyder.  Major testers included Jeff Dutton, Jonathon Donaldson,
+Ralf Karge, David Hewson, Iztok Jeras, Wim Michiels, Alex Solomatnikov,
+Sebastien Van Cauwenberghe, Gene Weber, and Clifford Wolf.

 Some of the people who have provided ideas, and feedback for Verilator
-include: David Addison, Nikana Anastasiadis, Vasu Arasanipalai, Jens Arm,
-Tariq B. Ahmad, Sharad Bagri, Matthew Ballance, Andrew Bardsley, Matthew
-Barr, Geoff Barrett, Kaleb Barrett, Julius Baxter, Jeremy Bennett, Michael
-Berman, Jean Berniolles, Victor Besyakov, Moinak Bhattacharyya, Krzysztof
-Bieganski, David Binderman, Piotr Binkowski, Johan Bjork, David Black,
-Tymoteusz Blazejczyk, Daniel Bone, Morten Borup Petersen, Gregg Bouchard,
-Christopher Boumenot, Nick Bowler, Byron Bradley, Bryan Brady, Charlie
-Brej, J Briquet, Lane Brooks, John Brownlee, Jeff Bush, Lawrence Butcher,
-Tony Bybell, Iru Cai, Ted Campbell, Chris Candler, Lauren Carlson, Donal
-Casey, Alex Chadwick, Terry Chen, Yi-Chung Chen, Enzo Chi, Robert A. Clark,
-Ryan Clarke, Allan Cochrane, John Coiner, Gianfranco Costamagna, Sean
-Cross, George Cuan, Joe DErrico, Lukasz Dalek, Gunter Dannoritzer, Ashutosh
-Das, Maarten De Braekeleer, Bernard Deadman, Alberto Del Rio, John Demme,
-Mike Denio, John Deroo, Philip Derrick, John Dickol, Ruben Diez, Danny
-Ding, Jacko Dirks, Ivan Djordjevic, Jonathon Donaldson, Sebastian Dressler,
-Alex Duller, Jeff Dutton, Tomas Dzetkulic, Richard E George, Edgar
-E. Iglesias, Usuario Eda, Charles Eddleston, Chandan Egbert, Jan Egil Ruud,
-Joe Eiler, Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Charles Eric
-LaForest, Robert Farrell, Eugen Fekete, Fabrizio Ferrandi, Udi Finkelstein,
-Brian Flachs, Andrea Foletto, Bob Fredieu, Duane Galbi, Benjamin Gartner,
-Christian Gelinek, Peter Gerst, Glen Gibb, Michael Gielda, Barbara Gigerl,
-Shankar Giri, Dan Gisselquist, Petr Gladkikh, Sam Gladstone, Andrew
-Goessling, Amir Gonnen, Chitlesh Goorah, Tomasz Gorochowik, Kai Gossner,
-Sergi Granell, Al Grant, Alexander Grobman, Xuan Guo, Driss Hafdi, Neil
+include:
+
+David Addison, Tariq B. Ahmad, Nikana Anastasiadis, Vasu Arasanipalai, Jens
+Arm, Sharad Bagri, Matthew Ballance, Andrew Bardsley, Matthew Barr, Geoff
+Barrett, Kaleb Barrett, Julius Baxter, Jeremy Bennett, Michael Berman, Jean
+Berniolles, Victor Besyakov, Moinak Bhattacharyya, Krzysztof Bieganski,
+David Binderman, Piotr Binkowski, Johan Bjork, David Black, Tymoteusz
+Blazejczyk, Daniel Bone, Gregg Bouchard, Christopher Boumenot, Nick Bowler,
+Byron Bradley, Bryan Brady, Maarten De Braekeleer, Charlie Brej, J Briquet,
+Lane Brooks, John Brownlee, Jeff Bush, Lawrence Butcher, Tony Bybell, Iru
+Cai, Ted Campbell, Chris Candler, Lauren Carlson, Donal Casey, Alex
+Chadwick, Marcel Chang, Aliaksei Chapyzhenka, Guokai Chen, Terry Chen,
+Yi-Chung Chen, Enzo Chi, Robert A. Clark, Ryan Clarke, Allan Cochrane, John
+Coiner, Keith Colbert, Gianfranco Costamagna, Sean Cross, George Cuan, Joe
+DErrico, Lukasz Dalek, Gunter Dannoritzer, Ashutosh Das, Bernard Deadman,
+John Demme, Mike Denio, John Deroo, Philip Derrick, John Dickol, Ruben
+Diez, Danny Ding, Jacko Dirks, Ivan Djordjevic, Jonathon Donaldson, Larry
+Doolittle, Sebastian Dressler, Jonathan Drolet, Alex Duller, Jeff Dutton,
+Tomas Dzetkulic, Usuario Eda, Charles Eddleston, Chandan Egbert, Joe Eiler,
+Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Robert Farrell, Eugen
+Fekete, Fabrizio Ferrandi, Udi Finkelstein, Brian Flachs, Bill Flynn,
+Andrea Foletto, Bob Fredieu, Duane Galbi, Mostafa Gamal, Benjamin Gartner,
+Christian Gelinek, Richard E George, Peter Gerst, Glen Gibb, Michael
+Gielda, Barbara Gigerl, Shankar Giri, Dan Gisselquist, Petr Gladkikh, Sam
+Gladstone, Mariusz Glebocki, Andrew Goessling, Amir Gonnen, Chitlesh
+Goorah, Tomasz Gorochowik, Kai Gossner, Sergi Granell, Al Grant, Nathan
+Graybeal, Alexander Grobman, Graham Rushton, Xuan Guo, Driss Hafdi, Neil
 Hamilton, James Hanlon, Oyvind Harboe, Jannis Harder, Junji Hashimoto,
 Thomas Hawkins, Mitch Hayenga, Harald Heckmann, Robert Henry, Stephen
 Henry, David Hewson, Jamey Hicks, Joel Holdsworth, Andrew Holme, Hiroki
 Honda, Alex Hornung, Pierre-Henri Horrein, David Horton, Peter Horvath, Jae
-Hossell, Kuoping Hsu, Alan Hunter, James Hutchinson, Anderson Ignacio da
-Silva, Jamie Iles, Thomas J Whatson, Ben Jackson, Mark Jackson Pulver,
-Shareef Jalloq, Marlon James, Krzysztof Jankowski, HyungKi Jeong, Iztok
-Jeras, James Johnson, Christophe Joly, Franck Jullien, James Jung, Mike
-Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje, Vasu Kandadi,
-Kanad Kanhere, Patricio Kaplan, Pieter Kapsenberg, Rafal Kapuscik, Ralf
-Karge, Dan Katz, Sol Katzman, Ian Kennedy, Michael Killough, Jonathan
-Kimmitt, Olof Kindgren, Kevin Kiningham, Dan Kirkham, Sobhan Klnv, Gernot
-Koch, Jack Koenig, Soon Koh, Nathan Kohagen, Steve Kolecki, Brett Koonce,
-Will Korteland, Wojciech Koszek, Varun Koyyalagunta, Markus Krause, David
-Kravitz, Roland Kruse, Andreas Kuster, Sergey Kvachonok, Ed Lander, Steve
-Lang, Stephane Laurent, Walter Lavino, Christian Leber, Larry Lee, Igor
-Lesik, John Li, Eivind Liland, Charlie Lind, Andrew Ling, Jiuyang Liu, Paul
-Liu, Derek Lockhart, Jake Longo, Geza Lore, Arthur Low, Stefan Ludwig, Dan
-Lussier, Fred Ma, Duraid Madina, Odd Magne Reitan, Affe Mao, Julien
-Margetts, Mark Marshall, Alfonso Martinez, Unai Martinez-Corral, Yves
-Mathieu, Patrick Maupin, Conor McCullough, Jason McMullan, Elliot Mednick,
-Wim Michiels, Miodrag Milanovic, Peter Monsson, Sean Moore, Dennis
-Muhlestein, John Murphy, Matt Myers, Nathan Myers, Richard Myers, Dimitris
-Nalbantis, Peter Nelson, Bob Newgard, Paul Nitza, Yossi Nivin, Pete Nixon,
-Lisa Noack, Mark Nodine, Kuba Ober, Andreas Olofsson, Baltazar Ortiz,
-Aleksander Osman, Don Owen, James Pallister, Vassilis Papaefstathiou, Brad
-Parker, Dan Petrisko, Maciej Piechotka, David Pierce, Cody Piersall,
-Dominic Plunkett, David Poole, Mike Popoloski, Roman Popov, Rich Porter,
-Niranjan Prabhu, Usha Priyadharshini, Prateek Puri, Marshal Qiao, Nandu
-Raj, Danilo Ramos, Chris Randall, Anton Rapp, Josh Redford, Frederic
-Requin, Dustin Richmond, Samuel Riedel, Eric Rippey, Oleg Rodionov, Ludwig
-Rogiers, Paul Rolfe, Arjen Roodselaar, Tobias Rosenkranz, Huang Rui, Denis
-Rystsov, John Sanguinetti, Galen Seitz, Joseph Shaker, Salman Sheikh, Yu
-Sheng Lin, Hao Shi, Mike Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Fan
-Shupei, Rodney Sinclair, Steven Slatter, Brian Small, Garrett Smith, Tim
-Snyder, Wilson Snyder, Maciej Sobkowski, Stan Sokorac, Alex Solomatnikov,
-Wei Song, Art Stamness, David Stanford, John Stevenson, Pete Stevenson,
-Patrick Stewart, Rob Stoddard, Todd Strader, John Stroebel, Sven Stucki,
-Howard Su, Emerson Suguimoto, Gene Sullivan, Wai Sum Mong, Qingyao Sun,
-Renga Sundararajan, Rupert Swarbrick, Yutetsu Takatsukasa, Thierry Tambe,
-Drew Taussig, Peter Tengstrand, Wesley Terpstra, Rui Terra, Stefan Thiede,
-Gary Thomas, Ian Thompson, Kevin Thompson, Mike Thyer, Hans Tichelaar,
-Viktor Tomov, Steve Tong, Alex Torregrosa, Michael Tresidder, David Turner,
-Neil Turton, Cong Van Nguyen, Hans Van Antwerpen, Jan Van Winkel, Sebastien
-Van Cauwenberghe, Laurens van Dam, Leendert van Doorn, Srini Vemuri, Yuri
+Hossell, Kuoping Hsu, Teng Huang, Steven Hugg, Alan Hunter, James
+Hutchinson, Ehab Ibrahim, Edgar E. Iglesias, Jamie Iles, Vighnesh Iyer, Ben
+Jackson, Shareef Jalloq, Marlon James, Krzysztof Jankowski, HyungKi Jeong,
+Iztok Jeras, Alexandre Joannou, James Johnson, Christophe Joly, Franck
+Jullien, James Jung, Mike Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand
+Kamendje, Vasu Kandadi, Kanad Kanhere, Patricio Kaplan, Pieter Kapsenberg,
+Rafal Kapuscik, Ralf Karge, Per Karlsson, Dan Katz, Sol Katzman, Ian
+Kennedy, Michael Killough, Sun Kim, Jonathan Kimmitt, Olof Kindgren, Kevin
+Kiningham, Dan Kirkham, Aleksander Kiryk, Sobhan Klnv, Gernot Koch, Jack
+Koenig, Soon Koh, Nathan Kohagen, Steve Kolecki, Brett Koonce, Will
+Korteland, Wojciech Koszek, Varun Koyyalagunta, Arkadiusz Kozdra, Markus
+Krause, David Kravitz, Roland Kruse, Andreas Kuster, Sergey Kvachonok,
+Charles Eric LaForest, Ed Lander, Steve Lang, Stephane Laurent, Walter
+Lavino, Christian Leber, Larry Lee, Yoda Lee, Michaël Lefebvre, Igor Lesik,
+John Li, Eivind Liland, Yu Sheng Lin, Charlie Lind, Andrew Ling, Jiuyang
+Liu, Paul Liu, Derek Lockhart, Jake Longo, Geza Lore, Arthur Low, Stefan
+Ludwig, Dan Lussier, Fred Ma, Duraid Madina, Affe Mao, Julien Margetts,
+Mark Marshall, Alfonso Martinez, Unai Martinez-Corral, Adrien Le Masle,
+Yves Mathieu, Patrick Maupin, Conor McCullough, Jason McMullan, Elliot
+Mednick, David Metz, Wim Michiels, Miodrag Milanovic, Kevin Millis, Wai Sum
+Mong, Peter Monsson, Sean Moore, Dennis Muhlestein, John Murphy, Matt
+Myers, Nathan Myers, Richard Myers, Dimitris Nalbantis, Peter Nelson, Bob
+Newgard, Rachit Nigam, Paul Nitza, Yossi Nivin, Pete Nixon, Lisa Noack,
+Mark Nodine, Kuba Ober, Andreas Olofsson, Baltazar Ortiz, Aleksander Osman,
+Don Owen, James Pallister, Vassilis Papaefstathiou, Brad Parker, Morten
+Borup Petersen, Dan Petrisko, Maciej Piechotka, David Pierce, Cody
+Piersall, Michael Platzer, Dominic Plunkett, David Poole, Mike Popoloski,
+Roman Popov, Rich Porter, Stefan Post, Niranjan Prabhu, Damien Pretet, Usha
+Priyadharshini, Mark Jackson Pulver, Prateek Puri, Marshal Qiao, Nandu Raj,
+Kamil Rakoczy, Danilo Ramos, Drew Ranck, Chris Randall, Anton Rapp, Josh
+Redford, Odd Magne Reitan, Frederic Requin, Dustin Richmond, Samuel Riedel,
+Alberto Del Rio, Eric Rippey, Oleg Rodionov, Ludwig Rogiers, Paul Rolfe,
+Arjen Roodselaar, Tobias Rosenkranz, Ryszard Rozak, Huang Rui, Graham
+Rushton, Jan Egil Ruud, Denis Rystsov, John Sanguinetti, Martin Schmidt,
+Julie Schwartz, Galen Seitz, Joseph Shaker, Salman Sheikh, Hao Shi, Mike
+Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Fan Shupei, Anderson Ignacio
+da Silva, Rodney Sinclair, Ameya Vikram Singh, Steven Slatter, Mladen
+Slijepcevic, Brian Small, Garrett Smith, Tim Snyder, Wilson Snyder, Maciej
+Sobkowski, Stan Sokorac, Alex Solomatnikov, Flavien Solt, Wei Song, Trefor
+Southwell, Martin Stadler, Art Stamness, David Stanford, John Stevenson,
+Pete Stevenson, Patrick Stewart, Rob Stoddard, Todd Strader, John Stroebel,
+Sven Stucki, Howard Su, Emerson Suguimoto, Gene Sullivan, Qingyao Sun,
+Renga Sundararajan, Gustav Svensk, Rupert Swarbrick, Yutetsu Takatsukasa,
+Thierry Tambe, Drew Taussig, Jose Tejada, Peter Tengstrand, Wesley
+Terpstra, Rui Terra, Stefan Thiede, Gary Thomas, Ian Thompson, Kevin
+Thompson, Mike Thyer, Hans Tichelaar, Viktor Tomov, Steve Tong, Topa
+Topino, Alex Torregrosa, Michael Tresidder, David Turner, Neil Turton, Mike
+Urbach, Hans Van Antwerpen, Sebastien Van Cauwenberghe, Laurens van Dam,
+Leendert van Doorn, Cong Van Nguyen, Jan Van Winkel, Srini Vemuri, Yuri
 Victorovich, Bogdan Vukobratovic, Holger Waechtler, Philipp Wagner, Stefan
-Wallentowitz, Shawn Wang, Paul Wasson, Greg Waters, Thomas Watts, Eugene
-Weber, David Welch, Martin Whitaker, Marco Widmer, Leon Wildman, Daniel
-Wilkerson, Gerald Williams, Trevor Williams, Jeff Winston, Joshua Wise,
-Clifford Wolf, Tobias Wolfel, Johan Wouters, Paul Wright, Junyi Xi, Ding
-Xiaoliang, Jie Xu, Mandy Xu, Yinan Xu, Luke Yang, Amir Yazdanbakhsh, and
-Keyi Zhang.
+Wallentowitz, Shawn Wang, Zhanglei Wang, Paul Wasson, Greg Waters, Thomas
+Watts, Eugene Weber, David Welch, Thomas J Whatson, Martin Whitaker, Marco
+Widmer, Leon Wildman, Daniel Wilkerson, Gerald Williams, Trevor Williams,
+Jeff Winston, Joshua Wise, Clifford Wolf, Tobias Wolfel, Johan Wouters,
+Paul Wright, Junyi Xi, Ding Xiaoliang, Jie Xu, Mandy Xu, Yinan Xu, Luke
+Yang, Amir Yazdanbakhsh, Keyi Zhang, and Xi Zhang.
+
+Thanks to them, and all those we've missed mentioning above, and to those
+whom have wished to remain anonymous.

-Thanks to them, and all those we've missed including above, or wished to
-remain anonymous.

 Historical Origins
 ==================

 Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group at
 Digital Equipment Corporation.  The Verilog code that was converted to C
-was then merged with a C based CPU model of the Alpha processor and
-simulated in a C based environment called CCLI.
+was then merged with a C-based CPU model of the Alpha processor and
+simulated in a C-based environment called CCLI.

-In 1995 Verilator started being used also for Multimedia and Network
-Processor development inside Digital.  Duane Galbi took over active
-development of Verilator, and added several performance enhancements.  CCLI
-was still being used as the shell.
+In 1995 Verilator started being used for Multimedia and Network Processor
+development inside Digital.  Duane Galbi took over the active development
+of Verilator, and added several performance enhancements, and CCLI was
+still being used as the shell.

 In 1998, through the efforts of existing DECies, mainly Duane Galbi,
 Digital graciously agreed to release the source code.  (Subject to the code
 not being resold, which is compatible with the GNU Public License.)

-In 2001, Wilson Snyder took the kit, and added a SystemC mode, and called
+In 2001, Wilson Snyder took the kit, added a SystemC mode, and called
 it Verilator2.  This was the first packaged public release.

 In 2002, Wilson Snyder created Verilator 3.000 by rewriting Verilator from
@@ -151,6 +164,10 @@ In 2018, Verilator 4.000 was released with multithreaded support.
 In 2019, Verilator joined the `CHIPS Alliance
 <https://chipsalliance.org>`_.

+In 2022, Verilator 5.000 was released with IEEE scheduling semantics,
+fork/join, delay handling, DFG performance optimizations, and other
+improvements.
+
 Currently, various language features and performance enhancements are added
-as the need arises.  Verilator is now about 3x faster than in 2002, and is
-faster than most (if not every) other simulator.
+as the need arises, focusing on completing Universal Verification
+Methodology (UVM, IEEE 1800.2-2017) support.
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 *********
@@ -8,12 +8,12 @@ Copyright
 The latest version of Verilator is available from `https://verilator.org
 <https://verilator.org>`_.

-Copyright 2003-2021 by Wilson Snyder. This program is free software; you
+Copyright 2003-2023 by Wilson Snyder. This program is free software; you
 can redistribute it and/or modify the Verilator internals under the terms
 of either the GNU Lesser General Public License Version 3 or the Perl
 Artistic License Version 2.0.

-All Verilog and C++/SystemC code quoted within this documentation file are
-released as Creative Commons Public Domain (CC0).  Many example files and
+All Verilog and C++/SystemC code quoted within this documentation file is
+released as Creative Commons Public Domain (CC0). Many example files and
 test files are likewise released under CC0 into effectively the Public
 Domain as described in the files themselves.
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 Deprecations
@@ -7,19 +7,37 @@ Deprecations
 The following deprecated items are scheduled for future removal:

 C++11 compiler support
-  Verilator currently requires C++11 or newer compilers.  Verilator will
-  require C++14 or newer compilers for both compiling Verilator and
-  compiling Verilated models no sooner than January 2022.
+  Verilator currently requires a C++20 or newer compiler for timing, and a
+  C++11 or newer compiler for no-timing.
+
+  Verilator will require C++14 or newer compilers for both compiling
+  Verilator and compiling Verilated models with --no-timing no sooner than
+  January 2023.
+
+  Verilator will require C++20 or newer compilers for both compiling
+  Verilator and compiling all Verilated models no sooner than January 2025.

 Verilated_heavy.h
  The legacy "verilated_heavy.h" include was replaced with just including
  "verilated.h". Verilated_heavy.h is planned for removal no sooner than
  July 2022.

-Configuration File -msg
-  The :vlopt:`lint_off` "-msg" option has been replaced with the "-rule"
-  option.  "-msg" is planned for removal no sooner than January 2021.
+Option `--cdc`
+  The experimental `--cdc` option is believed to be generally unused and is
+  planned for removal no sooner than January 2023.

-XML locations
-  The XML "fl" attribute has been replaced with the "loc" attribute.  "fl"
-  is planned for removal no sooner than January 2021.
+Option `-O<letter>`
+  The debug `-O<letter>` options have been replaced with
+  `-fno-<optimization>` debug options to match GCC. The old options are
+  planned for removal no sooner than June 2023.
+
+Option `--prof-threads`
+  The `--prof-threads` option has been superseded by the `--prof-exec` and
+  `--prof-pgo` options and is planned for removal no sooner than April 2023.
+
+Verilated model options `+verilator+prof+threads+*`
+  The `+verilator+prof+threads+start`, `+verilator+prof+threads+window` and
+  `+verilator+prof+threads+file` options have been superseded by the
+  `+verilator+prof+exec+start`, `+verilator+prof+exec+window` and
+  `+verilator+prof+exec+file` options respectively and are planned for removal
+  no sooner than April 2023.
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 Environment
@@ -10,7 +10,7 @@ associated programs.
 .. option:: LD_LIBRARY_PATH

   A generic Linux/OS variable specifying what directories have shared
-   object (.so) files.  This path should include SystemC and any other
+   object (.so) files.  This path should include SystemC and other
   shared objects needed at simulation runtime.

 .. option:: MAKE
@@ -20,6 +20,12 @@ associated programs.
   this variable to launch GNU make.  If this variable is not specified,
   "make" is used.

+.. option:: MAKEFLAGS
+
+   Flags created by :command:`make` to pass to submakes. Verilator searches
+   this variable to determine if a jobserver is used; see
+   :vlopt:`--build-jobs`.
+
 .. option:: OBJCACHE

   Optionally specifies a caching or distribution program to place in front
@@ -54,14 +60,14 @@ associated programs.

 .. option:: SYSTEMC_INCLUDE

-   If set, specifies the directory containing the systemc.h header file. If
-   not specified, it will come from a default optionally specified at
+   If set, specifies the directory containing the systemc.h header file.
+   If not specified, it will come from a default optionally specified at
   configure time (before Verilator was compiled), or computed from
   SYSTEMC/include.

 .. option:: SYSTEMC_LIBDIR

-   If set, specifies the directory containing the libsystemc.a library. If
+   If set, specifies the directory containing the libsystemc.a library.  If
   not specified, it will come from a default optionally specified at
   configure time (before Verilator was compiled), or computed from
   SYSTEMC/lib-SYSTEMC_ARCH.
@@ -0,0 +1,63 @@
+.. Copyright 2003-2023 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+.. _Example Create-Binary Execution:
+
+Example Create-Binary Execution
+===============================
+
+We'll compile this SystemVerilog example into a Verilated simulation binary.  For
+an example that discusses the next level of detail see :ref:`Example C++
+Execution`.
+
+.. include:: example_common_install.rst
+
+Now, let's create an example Verilog file:
+
+.. code-block:: bash
+
+     mkdir test_our
+     cd test_our
+
+     cat >our.v <<'EOF'
+       module our;
+          initial begin $display("Hello World"); $finish; end
+       endmodule
+     EOF
+
+Now we run Verilator on our little example.
+
+.. code-block:: bash
+
+     verilator --binary -j 0 -Wall our.v
+
+Breaking this command down:
+
+#. :vlopt:`--binary` telling Verilator to do everything needed to create a
+   simulation executable.
+
+#. :vlopt:`-j` `0` to Verilate using use as many CPU threads as the machine
+   has.
+
+#. :vlopt:`-Wall` so Verilator has stronger lint warnings
+   enabled.
+
+#. An finally, :command:`our.v`, which is our SystemVerilog design file.
+
+And now we run it:
+
+.. code-block:: bash
+
+     obj_dir/Vour
+
+And we get as output:
+
+.. code-block:: bash
+
+     Hello World
+     - our.v:2: Verilog $finish
+
+You're better off using a Makefile to run the steps for you, so when your
+source changes, it will automatically run all of the appropriate steps.  To
+aid this, Verilator can create a makefile dependency file.  For examples
+that do this, see the :file:`examples` directory in the distribution.
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 .. _Example C++ Execution:
@@ -12,7 +12,7 @@ of what this C++ code is doing, see

 .. include:: example_common_install.rst

-Now, let's create an example Verilog, and C++ wrapper file:
+Now, let's create an example Verilog and C++ wrapper file:

 .. code-block:: bash

@@ -28,7 +28,7 @@ Now, let's create an example Verilog, and C++ wrapper file:
     cat >sim_main.cpp <<'EOF'
       #include "Vour.h"
       #include "verilated.h"
-       int main(int argc, char** argv, char** env) {
+       int main(int argc, char** argv) {
           VerilatedContext* contextp = new VerilatedContext;
           contextp->commandArgs(argc, argv);
           Vour* top = new Vour{contextp};
@@ -39,19 +39,15 @@ Now, let's create an example Verilog, and C++ wrapper file:
       }
     EOF

-Now we run Verilator on our little example.
+Now we run Verilator on our little example;

 .. code-block:: bash

-     verilator -Wall --cc --exe --build sim_main.cpp our.v
+     verilator --cc --exe --build -j 0 -Wall sim_main.cpp our.v

 Breaking this command down:

-#. :vlopt:`-Wall` so Verilator has stronger lint warnings
-   enabled.
-
-#. :vlopt:`--cc` to get C++ output (versus e.g. SystemC
-   or only linting).
+#. :vlopt:`--cc` to get C++ output (versus e.g., SystemC, or only linting).

 #. :vlopt:`--exe`, along with our :command:`sim_main.cpp` wrapper file, so
   the build will create an executable instead of only a library.
@@ -61,7 +57,13 @@ Breaking this command down:
   own compile rules, and run make yourself as we show in :ref:`Example
   SystemC Execution`.)

-#. An finally, :command:`our.v` which is our SystemVerilog design file.
+#. :vlopt:`-j 0 <-j>` to Verilate using use as many CPU threads as the
+   machine has.
+
+#. :vlopt:`-Wall` so Verilator has stronger lint warnings
+   enabled.
+
+#. And finally, :command:`our.v` which is our SystemVerilog design file.

 Once Verilator completes we can see the generated C++ code under the
 :file:`obj_dir` directory.
@@ -86,7 +88,7 @@ And we get as output:
     Hello World
     - our.v:2: Verilog $finish

-Really, you're better off using a Makefile to run the steps for you so when
-your source changes it will automatically run all of the appropriate steps.
-To aid this Verilator can create a makefile dependency file.  For examples
-that do this see the :file:`examples` directory in the distribution.
+You're better off using a Makefile to run the steps for you, so when your
+source changes, it will automatically run all of the appropriate steps.  To
+aid this, Verilator can create a makefile dependency file.  For examples
+that do this, see the :file:`examples` directory in the distribution.
@@ -1,7 +1,7 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

-First you need Verilator installed, see :ref:`Installation`. In brief, if
+First you need Verilator installed, see :ref:`Installation`.  In brief, if
 you installed Verilator using the package manager of your operating system,
 or did a :command:`make install` to place Verilator into your default path,
 you do not need anything special in your environment, and should not have
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 .. _Examples in the Distribution:
@@ -7,9 +7,11 @@ Examples in the Distribution
 ============================

 See the ``examples/`` directory that is part of the distribution, and
-is installed (in a OS-specific place, often in e.g.
+is installed (in an OS-specific place, often in e.g.
 ``/usr/local/share/verilator/examples``).  These examples include:

+examples/make_hello_binary
+   Example GNU-make simple Verilog->binary conversion
 examples/make_hello_c
   Example GNU-make simple Verilog->C++ conversion
 examples/make_hello_sc
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 .. _Example SystemC Execution:
@@ -43,7 +43,7 @@ Now we run Verilator on our little example:

 .. code-block:: bash

-     verilator -Wall --sc --exe sc_main.cpp our.v
+     verilator --sc --exe -Wall sc_main.cpp our.v

 This example does not use --build, therefore we need to explicitly compile
 it:
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 .. _Examples:
@@ -17,6 +17,7 @@ This section covers the following examples:
   :maxdepth: 1
   :hidden:

+   example_binary.rst
   example_cc.rst
   example_sc.rst
   example_dist.rst
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 .. _Simulation Runtime Arguments:
@@ -8,7 +8,7 @@ Simulation Runtime Arguments

 The following are the arguments that may be passed to a Verilated
 executable, provided that executable calls
-:code:`Verilated::commandArgs()`.
+:code:`VerilatedContext*->commandArgs(argc, argv)`.

 All simulation runtime arguments begin with "+verilator", so that the
 user's executable may skip over all "+verilator" arguments when parsing its
@@ -38,42 +38,54 @@ Summary:

   Display help and exit.

-.. option:: +verilator+prof+threads+file+<filename>
+.. option:: +verilator+prof+exec+file+<filename>

-   When a model was Verilated using :vlopt:`--prof-threads`, sets the
+   When a model was Verilated using :vlopt:`--prof-exec`, sets the
   simulation runtime filename to dump to.  Defaults to
-   :file:`profile_threads.dat`.
+   :file:`profile_exec.dat`.

-.. option:: +verilator+prof+threads+start+<value>
+.. option:: +verilator+prof+exec+start+<value>

-   When a model was Verilated using :vlopt:`--prof-threads`, the simulation
+   When a model was Verilated using :vlopt:`--prof-exec`, the simulation
   runtime will wait until $time is at this value (expressed in units of
   the time precision), then start the profiling warmup, then
   capturing. Generally this should be set to some time that is well within
   the normal operation of the simulation, i.e. outside of reset. If 0, the
   dump is disabled. Defaults to 1.

-.. option:: +verilator+prof+threads+window+<value>
+.. option:: +verilator+prof+exec+window+<value>

-   When a model was Verilated using :vlopt:`--prof-threads`, after $time
-   reaches :vlopt:`+verilator+prof+threads+start+\<value\>`, Verilator will
+   When a model was Verilated using :vlopt:`--prof-exec`, after $time
+   reaches :vlopt:`+verilator+prof+exec+start+\<value\>`, Verilator will
   warm up the profiling for this number of eval() calls, then will capture
   the profiling of this number of eval() calls.  Defaults to 2, which
   makes sense for a single-clock-domain module where it's typical to want
   to capture one posedge eval() and one negedge eval().

+.. option:: +verilator+prof+threads+file+<filename>
+
+   Deprecated. Alias for :vlopt:`+verilator+prof+exec+file+\<filename\>`
+
+.. option:: +verilator+prof+threads+start+<value>
+
+   Deprecated. Alias for :vlopt:`+verilator+prof+exec+start+\<value\>`
+
+.. option:: +verilator+prof+threads+window+<value>
+
+   Deprecated. Alias for :vlopt:`+verilator+prof+exec+window+\<value\>`
+
 .. option:: +verilator+prof+vlt+file+<filename>

-   When a model was Verilated using :vlopt:`--prof-threads`, sets the
+   When a model was Verilated using :vlopt:`--prof-pgo`, sets the
   profile-guided optimization data runtime filename to dump to.  Defaults
   to :file:`profile.vlt`.

 .. option:: +verilator+rand+reset+<value>

-   When a model was Verilated using :vlopt:`--x-initial unique
-   <--x-initial>`, sets the simulation runtime initialization technique.  0
-   = Reset to zeros. 1 = Reset to all-ones.  2 = Randomize.  See
-   :ref:`Unknown States`.
+   When a model was Verilated using
+   :vlopt:`--x-initial unique <--x-initial>`, sets the simulation runtime
+   initialization technique.  0 = Reset to zeros. 1 = Reset to all-ones.  2
+   = Randomize.  See :ref:`Unknown States`.

 .. option:: +verilator+seed+<value>

@@ -84,7 +96,7 @@ Summary:
 .. option:: +verilator+noassert

   Disable assert checking per runtime argument. This is the same as
-   calling :code:`Verilated::assertOn(false)` in the model.
+   calling :code:`VerilatedContext*->assertOn(false)` in the model.

 .. option:: +verilator+V

@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 verilator_coverage
@@ -12,8 +12,8 @@ coverage points exist on the same source code line, additional lines will
 be inserted to report the additional points.

 Additional Verilog-XL-style standard arguments specify the search paths
-necessary to find the source code that the coverage analysis was performed
-on.
+necessary to find the source code on which the coverage analysis was
+performed.

 To filter those items to be included in coverage, you may read
 logs/coverage.dat into an editor and do a M-x keep-lines to include only
@@ -24,7 +24,7 @@ statement to the appropriate statement block, or see
 :option:`/*verilator&32;coverage_off*/`.  This will remove the coverage
 points after the model is re-Verilated.

-For an overview of use of verilator_coverage, see :ref:`Coverage Analysis`.
+For an overview of the use of verilator_coverage, see :ref:`Coverage Analysis`.


 verilator_coverage Example Usage
@@ -50,25 +50,25 @@ verilator_coverage Arguments
 .. option:: <filename>

 Specifies the input coverage data file.  Multiple filenames may be provided
-to read multiple inputs.  If no data file is specified, by default
+to read multiple inputs.  If no data file is specified, by default,
 "coverage.dat" will be read.

 .. option:: --annotate <output_directory>

-Specifies the directory name that source files with annotated coverage data
-should be written to.
+Specifies the directory name to which source files with annotated coverage
+data should be written.

 .. option:: --annotate-all

 Specifies all files should be shown.  By default, only those source files
-which have low coverage are written to the output directory.
+with low coverage are written to the output directory.

 .. option:: --annotate-min <count>

 Specifies if the coverage point does not include the count number of
 coverage hits, then the coverage point will be considered above the
-threashold, and the coverage report will put a "%" to indicate the coverage
-is not sufficient.  Defaults to 10.
+threshold, and the coverage report will put a "%" to indicate the coverage
+is insufficient.  Defaults to 10.

 .. option:: --help

@@ -78,12 +78,12 @@ Displays a help summary, the program version, and exits.

 Prints an experimental report listing the relative importance of each test
 in covering all of the coverage points.  The report shows "Covered" which
-indicates the number of points that test covers; a test is considered to
+indicates the number of points the test covers; a test is considered to
 cover a point if it has a bucket count of at least 1. The "rank" column has
-a higher number t indicate the test is more important, and rank 0 means the
+a higher number t indicate the test is more critical, and rank 0 means the
 test does not need to be run to cover the points.  "RankPts" indicates the
 number of coverage points this test will contribute to overall coverage if
-all tests are run in the order of highest to lowest rank.
+all tests are run in the order of highest to the lowest rank.

 .. option:: --unlink

@@ -98,8 +98,8 @@ Displays program version and exits.

 Specifies the aggregate coverage results, summed across all the files,
 should be written to the given filename in verilator_coverage data format.
-This is useful for use in scripts to combine many coverage data files
-(likely generated from random test runs) into one master coverage file.
+This is useful in scripts to combine many coverage data files (likely
+generated from random test runs) into one master coverage file.

 .. option:: --write-info <filename.info>

@@ -108,7 +108,8 @@ should be written to the given filename in :command:`lcov` .info format.
 This may be used to feed into :command:`lcov` to aggregate or generate
 reports.

-The info format loses data compared to the Verilator coverage data format;
-the info will all forms of coverage converted to line style coverage, and
-if there are multiple coverage points on a single line, the minimum
-coverage across those points will be used to report coverage of the line.
+Converting from the Verilator coverage data format to the info format is
+lossy; the info will have all forms of coverage merged line coverage, and
+if there are multiple coverage points on a single line they will merge.
+The minimum coverage across all merged points will be used to report
+coverage of the line.
@@ -1,20 +1,20 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 verilator_gantt
 ===============

 Verilator_gantt creates a visual representation to help analyze Verilator
-multithreaded simulation performance, by showing when each macro-task
-starts and ends, and showing when each thread is busy or idle.
+multithreaded simulation performance by showing when each macro-task
+starts, ends, and when each thread is busy or idle.

-For an overview of use of verilator_gantt, see :ref:`Profiling`.
+For an overview of the use of verilator_gantt, see :ref:`Profiling`.

 Gantt Chart VCD
 ---------------

-Verilated_gnatt creates a value change dump (VCD) format dump file which
-may be viewed in a waveform viewer (e.g. C<GTKWave>):
+Verilated_gantt creates a value change dump (VCD) format dump file which
+may be viewed in a waveform viewer (e.g., C<GTKWave>):

 .. figure:: figures/fig_gantt_min.png

@@ -27,9 +27,8 @@ time tick of the system's high-performance counter.
 Gantt Chart VCD Signals
 -----------------------

-In waveforms there are the following signals. In GTKWave, using a data
-format of "decimal" will remove the leading zeros and make the traces
-easier to read.
+In waveforms, there are the following signals. In GTKWave, use "decimal"
+data format to remove the leading zeros and make the traces easier to read.

 evals
  Increments each time when eval_step was measured to be active.  This
@@ -37,12 +36,12 @@ evals

 eval_loop
  Increments each time when the evaluation loop within eval_step was
-  measured to be active.  For best performance there is only a single
-  evaluation loop within each eval_step call, that is the eval_loop
+  measured to be active.  For best performance, there is only a single
+  evaluation loop within each eval_step call; that is, the eval_loop
  waveform looks identical to the evals waveform.

 measured_parallelism
-  The number of mtasks active at this time, for best performance this will
+  The number of mtasks active at this time, for best performance, this will
  match the thread count. In GTKWave, use a data format of "analog step" to
  view this signal.

@@ -72,7 +71,7 @@ verilator_gantt Arguments

 .. option:: <filename>

-The filename to read data from, defaults to "profile_threads.dat".
+The filename to read data from; the default is "profile_exec.dat".

 .. option:: --help

@@ -84,4 +83,4 @@ Disables creating a .vcd file.

 .. option:: --vcd <filename>

-Sets the output filename for vcd dump. Default is "verilator_gantt.vcd".
+Sets the output filename for vcd dump; the default is "verilator_gantt.vcd".
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 verilator_profcfunc
@@ -6,14 +6,14 @@ verilator_profcfunc

 Verilator_profcfunc reads a profile report created by gprof.  The names of
 the functions are then transformed, assuming the user used Verilator's
--prof-cfuncs, and a report printed showing the percentage of time, etc, in
-each Verilog block.
+--prof-cfuncs, and a report printed showing the percentage of the time,
+etc., in each Verilog block.

 Due to rounding errors in gprof reports, the input report's percentages may
-not total to 100%.  In the verilator_profcfunc report this will get
+not total 100%.  In the verilator_profcfunc report this will get
 reported as a rounding error.

-For an overview of use of verilator_profcfunc, see :ref:`Profiling`.
+For an overview of the use of verilator_profcfunc, see :ref:`Profiling`.

 verilator_profcfunc Arguments
 -----------------------------
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 *********************************
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 *******************
@@ -12,19 +12,25 @@ or "`ifdef`"'s may break other tools.
 .. option:: `__FILE__

   The :option:`\`__FILE__` define expands to the current filename as a
-   string, like C++'s __FILE__.  This Verilator feature added in 2006 was
-   incorporated into the IEEE 1800-2009 standard.
+   string, like C++'s __FILE__.  This Verilator feature, added in 2006, was
+   incorporated into IEEE 1800-2009.

 .. option:: `__LINE__

   The :option:`\`__LINE__` define expands to the current filename as a
   string, like C++'s __LINE__.  This Verilator feature added in 2006 was
-   incorporated into the IEEE 1800-2009 standard.
+   incorporated into IEEE 1800-2009.

 .. option:: `error [string]

   This will report an error when encountered, like C++'s #error.

+.. option:: """ [string] """
+
+   A triple-quoted block specifies a string that may include newlines and
+   single quotes.  This extension is experimental and may be removed
+   without deprecation.
+
 .. option:: $c([string], ...);

   The string will be embedded directly in the output C++ code at the point
@@ -45,16 +51,24 @@ or "`ifdef`"'s may break other tools.
   rather than hard-coding variable names in the string
   :code:`$c("func(a)")`, instead pass the variable as an expression
   ::code:`$c("func(",a,")")`.  This will allow the call to work inside
-   Verilog functions where the variable is flattened out, and also enable
-   other optimizations.
+   Verilog functions where the variable is flattened out and enable other
+   optimizations.
+
+   Verilator does not use any text inside the quotes for
+   ordering/scheduling.  If you need the $c to be called at a specific
+   time, e.g., when a variable changes, then the $c must be under an
+   appropriate sensitivity statement, e.g.,
+   :code:`always @(posedge clk) $c("func()")` to call it on every edge, or,
+   e.g., :code:`always @* c("func(",a,")")` to call it when :code:`a`
+   changes (the latter working because :code:`a` is outside the quotes).

   If you will be reading or writing any Verilog variables inside the C++
   functions, the Verilog signals must be declared with
   :option:`/*verilator&32;public*/` metacomments.

-   You may also append an arbitrary number to $c, generally the width of
-   the output; :code:`signal_32_bits = $c32("...");`.  This allows for
-   compatibility with other simulators which require a differently named
+   You may also append a number to $c, which specifies the bit width of
+   the output, e.g., :code:`signal_32_bits = $c32("...");`.  This allows for
+   compatibility with other simulators, which require a differently named
   PLI function name for each different output width.

 .. option:: $display, $write, $fdisplay, $fwrite, $sformat, $swrite
@@ -62,61 +76,71 @@ or "`ifdef`"'s may break other tools.
   Format arguments may use C fprintf sizes after the % escape.  Per the
   Verilog standard, %x prints a number with the natural width, and %0x
   prints a number with minimum width.  Verilator extends this so %5x
-   prints 5 digits per the C standard (this is unspecified in Verilog, but
-   was incorporated into the 1800-2009).
+   prints 5 digits per the C standard. This extension was standardized into
+   1800-2009.
+
+.. option:: $timeprecision
+
+   Returns the timeprecision of the model as an integer.  This extension is
+   experimental and may be removed without deprecation.
+
+.. option:: $timeunit
+
+   Returns the timeunit of the current module as an integer.  This
+   extension is experimental and may be removed without deprecation.

 .. option:: `coverage_block_off

   Specifies the entire begin/end block should be ignored for coverage
-   analysis.  Must be inside a code block, e.g. within a begin/end pair.
+   analysis.  Must be inside a code block, e.g., within a begin/end pair.
   Same as :option:`coverage_block_off` in :ref:`Configuration Files`.

 .. option:: `systemc_header

-   Take remaining text up to the next :option:`\`verilog` or
+   Take the remaining text up to the next :option:`\`verilog` or
   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
   verbatim into the output .h file's header.  Must be placed as a module
-   item, e.g. directly inside a module/endmodule pair. Despite the name of
+   item, e.g., directly inside a module/endmodule pair. Despite the name of
   this macro, this also works in pure C++ code.

 .. option:: `systemc_ctor

-   Take remaining text up to the next :option:`\`verilog` or
+   Take the remaining text up to the next :option:`\`verilog` or
   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
   verbatim into the C++ class constructor.  Must be placed as a module
-   item, e.g. directly inside a module/endmodule pair. Despite the name of
+   item, e.g., directly inside a module/endmodule pair. Despite the name of
   this macro, this also works in pure C++ code.

 .. option:: `systemc_dtor

-   Take remaining text up to the next :option:`\`verilog` or
+   Take the remaining text up to the next :option:`\`verilog` or
   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
   verbatim into the C++ class destructor.  Must be placed as a module
-   item, e.g. directly inside a module/endmodule pair. Despite the name of
+   item, e.g., directly inside a module/endmodule pair. Despite the name of
   this macro, this also works in pure C++ code.

 .. option:: `systemc_interface

-   Take remaining text up to the next :option:`\`verilog` or
+   Take the remaining text up to the next :option:`\`verilog` or
   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
   verbatim into the C++ class interface.  Must be placed as a module item,
-   e.g. directly inside a module/endmodule pair. Despite the name of this
+   e.g., directly inside a module/endmodule pair. Despite the name of this
   macro, this also works in pure C++ code.

 .. option:: `systemc_imp_header

-   Take remaining text up to the next :option:`\`verilog` or
+   Take the remaining text up to the next :option:`\`verilog` or
   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
   verbatim into the header of all files for this C++ class implementation.
-   Must be placed as a module item, e.g. directly inside a module/endmodule
+   Must be placed as a module item, e.g., directly inside a module/endmodule
   pair. Despite the name of this macro, this also works in pure C++ code.

 .. option:: `systemc_implementation

-   Take remaining text up to the next :option:`\`verilog` or
+   Take the remaining text up to the next :option:`\`verilog` or
   :option:`\`systemc_... <\`systemc_header>` mode switch and place it
   verbatim into a single file of the C++ class implementation.  Must be
-   placed as a module item, e.g. directly inside a module/endmodule
+   placed as a module item, e.g., directly inside a module/endmodule
   pair. Despite the name of this macro, this also works in pure C++ code.

   If you will be reading or writing any Verilog variables in the C++
@@ -126,7 +150,7 @@ or "`ifdef`"'s may break other tools.

 .. option:: `SYSTEMVERILOG

-   The SYSTEMVERILOG, SV_COV_START and related standard defines are set by
+   The SYSTEMVERILOG, SV_COV_START, and related standard defines are set by
   default when :vlopt:`--language <--language>` is "1800-\*".

 .. option:: `VERILATOR
@@ -140,9 +164,16 @@ or "`ifdef`"'s may break other tools.

 .. option:: `verilator_config

-   Take remaining text up to the next :option:`\`verilog` mode switch and
+   Take the remaining text up to the next :option:`\`verilog` mode switch and
   treat it as Verilator configuration commands.  See :ref:`Configuration Files`.

+.. option:: `VERILATOR_TIMING
+
+   The VERILATOR_TIMING define is set when :vlopt:`--timing` is used to
+   allow an "\`ifdef" of code dependent on this feature.  Note that this define
+   is not affected by the :option:`timing_off` configuration file option
+   nor timing metacomments.
+
 .. option:: `verilog

   Switch back to processing Verilog code after a
@@ -152,8 +183,12 @@ or "`ifdef`"'s may break other tools.

 .. option:: /*verilator&32;clock_enable*/

+   Deprecated and has no effect (ignored).
+
+   In versions before 5.000:
+
   Used after a signal declaration to indicate the signal is used to gate a
-   clock, and the user takes responsibility for insuring there are no races
+   clock, and the user is responsible for ensuring there are no races
   related to it. (Typically by adding a latch, and running static timing
   analysis.) For example:

@@ -166,9 +201,7 @@ or "`ifdef`"'s may break other tools.

   The clock_enable attribute will cause the clock gate to be ignored in
   the scheduling algorithm, sometimes required for correct clock behavior,
-   and always improving performance.  It's also a good idea to enable the
-   :option:`IMPERFECTSCH` warning, to ensure all clock enables are properly
-   recognized.
+   and always improving performance.

   Same as :option:`clock_enable` configuration file option.

@@ -176,10 +209,7 @@ or "`ifdef`"'s may break other tools.

 .. option:: /*verilator&32;no_clocker*/

-   Used after a signal declaration to indicate the signal is used as clock
-   or not. This information is used by Verilator to mark the signal as
-   clocker and propagate the clocker attribute automatically to derived
-   signals. See :vlopt:`--clk`.
+   Specifies whether the signal is used as clock or not. See :vlopt:`--clk`.

   Same as :option:`clocker` and :option:`no_clocker` in configuration
   files.
@@ -193,15 +223,29 @@ or "`ifdef`"'s may break other tools.

 .. option:: /*verilator&32;coverage_off*/

-   Specifies that following lines of code should have coverage disabled.
+   Specifies that that following lines of code should have coverage disabled.
   Often used to ignore an entire module for coverage analysis purposes.

 .. option:: /*verilator&32;coverage_on*/

-   Specifies that following lines of code should have coverage re-enabled
+   Specifies that that following lines of code should have coverage re-enabled
   (if appropriate :vlopt:`--coverage` flags are passed) after being
   disabled earlier with :option:`/*verilator&32;coverage_off*/`.

+.. option:: /*verilator&32;forceable*/
+
+   Specifies that the signal (net or variable) should be made forceable from
+   C++ code by generating public `<signame>__VforceEn` and
+   `<signame>__VforceVal` signals. The force control signals are created as
+   :option:`public_flat` signals.
+
+   To force a marked signal from C++, set the corresponding `__VforceVal`
+   variable to the desired value, and the `__VforceEn` signal to the bit-mask
+   indicating which bits of the signal to force. To force all bits of the
+   target signal, set `__VforceEn` to all ones. To release the signal (or part
+   thereof), set appropriate bits of the `__VforceEn` signal to zero.
+
+   Same as :option:`forceable` in configuration  files.

 .. _verilator_hier_block:

@@ -228,10 +272,10 @@ or "`ifdef`"'s may break other tools.
 .. option:: /*verilator&32;isolate_assignments*/

   Used after a signal declaration to indicate the assignments to this
-   signal in any blocks should be isolated into new blocks.  When there is
-   a large combinatorial block that is resulting in an ``UNOPTFLAT``
-   warning, attaching this to the signal causing a false loop may clear up
-   the problem.
+   signal in any blocks should be isolated into new blocks.  When large
+   combinatorial block results in a :option:`UNOPTFLAT` warning, attaching
+   this to the signal that was causing a false loop may work around the
+   warning.

   IE, with the following:

@@ -285,7 +329,7 @@ or "`ifdef`"'s may break other tools.

 .. option:: /*verilator&32;lint_save*/

-   Push the current state of what lint messages are turned on or turned off
+   Push the current state of what lint messages are turned on or off
   to a stack.  Later meta-comments may then lint_on or lint_off specific
   messages, then return to the earlier message state by using
   :code:`/*verilator&32;lint_restore*/`.  For example:
@@ -297,8 +341,8 @@ or "`ifdef`"'s may break other tools.
         ...  // code needing WIDTH turned off
         // verilator lint_restore

-   If WIDTH was on before the lint_off, it will now be restored to on, and
-   if it was off before the lint_off it will remain off.
+   If WIDTH was on before the lint_off, it would now be restored to on, and
+   if it was off before the lint_off it would remain off.

 .. option:: /*verilator&32;no_inline_module*/

@@ -342,13 +386,12 @@ or "`ifdef`"'s may break other tools.

   Used after an input, output, register, or wire declaration to indicate
   the signal should be declared so that C code may read or write the value
-   of the signal.  This will also declare this module public, otherwise use
+   of the signal.  This will also declare this module public; otherwise, use
   :code:`/*verilator&32;public_flat*/`.

-   Instead of using public variables, consider instead making a DPI or
-   public function that accesses the variable.  This is nicer as it
-   provides an obvious entry point that is also compatible across
-   simulators.
+   Instead of using public variables, consider making a DPI or public
+   function that accesses the variable.  This is nicer as it provides an
+   obvious entry point compatible across simulators.

   Same as :option:`public` configuration file option.

@@ -358,7 +401,7 @@ or "`ifdef`"'s may break other tools.
   indicate the function or task should be made into a C++ function, public
   to outside callers.  Public tasks will be declared as a void C++
   function, public functions will get the appropriate non-void (bool,
-   uint32_t, etc) return type.  Any input arguments will become C++
+   uint32_t, etc.) return type.  Any input arguments will become C++
   arguments to the function.  Any output arguments will become C++
   reference arguments.  Any local registers/integers will become function
   automatic variables on the stack.
@@ -396,10 +439,10 @@ or "`ifdef`"'s may break other tools.
 .. option:: /*verilator&32;public_flat_rw @(<edge_list>)*/ (on variable)

   Used after an input, output, register, or wire declaration to indicate
-   the signal should be declared public_flat_rd (see above), and also
-   writable, where writes should be considered to have the timing specified
-   by the given sensitivity edge list.  Set for all variables, ports and
-   wires using the :vlopt:`--public-flat-rw` option.
+   the signal should be declared public_flat_rd (see above), and writable,
+   where writes should be considered to have the timing specified by the
+   given sensitivity edge list. Use of this is implied when using the
+   :vlopt:`--public-flat-rw` option.

   Same as :option:`public_flat_rw` configuration file option.

@@ -408,8 +451,8 @@ or "`ifdef`"'s may break other tools.
   Used after a module statement to indicate the module should not be
   inlined (unless specifically requested) so that C code may access the
   module.  Verilator automatically sets this attribute when the module
-   contains any public signals or \`systemc_ directives.  Also set for all
-   modules when using the :vlopt:`--public` option.
+   contains public signals or \`systemc_ directives.  Use of this is
+   implied when using the :vlopt:`--public` option.

   Same as :option:`public` configuration file option.

@@ -418,27 +461,26 @@ or "`ifdef`"'s may break other tools.
   Deprecated and ignored.  Previously used after an input declaration to
   indicate the signal should be declared in SystemC as a sc_clock instead
   of a bool.  This was needed in SystemC 1.1 and 1.2 only; versions 2.0
-   and later do not require clock pins to be sc_clocks and this is no
+   and later do not require clock pins to be sc_clocks, and this is no
   longer needed and is ignored.

 .. option:: /*verilator&32;sc_bv*/

   Used after a port declaration.  It sets the port to be of
-   :code:`sc_bv<{width}>` type, instead of bool, vluint32_t or vluint64_t.
+   :code:`sc_bv<{width}>` type, instead of bool, uint32_t, or uint64_t.
   This may be useful if the port width is parameterized and the
-   instantiating C++ code wants to always have a sc_bv so it can accept any
-   width.  In general you should avoid using this attribute when not
-   necessary as with increasing usage of sc_bv the performance decreases
-   significantly.
+   instantiating C++ code always wants to have a sc_bv accept any width.
+   In general, you should avoid using this attribute when unnecessary, as
+   the performance decreases significantly with increasing usage of sc_bv.

   Same as :option:`sc_bv` configuration file option.

 .. option:: /*verilator&32;sformat*/

   Attached to the final argument of type "input string" of a function or
-   task to indicate the function or task should pass all remaining
+   task to indicate that the function or task should pass all remaining
   arguments through $sformatf.  This allows creation of DPI functions with
-   $display like behavior.  See the :file:`test_regress/t/t_dpi_display.v`
+   $display-like behavior.  See the :file:`test_regress/t/t_dpi_display.v`
   file for an example.

   Same as :option:`sformat` configuration file option.
@@ -448,7 +490,7 @@ or "`ifdef`"'s may break other tools.
   Attached to a variable or a net declaration to break the variable into
   multiple pieces typically to resolve ``UNOPTFLAT`` performance issues.
   Typically the variables to attach this to are recommended by Verilator
-   itself, see :option:`UNOPTFLAT`.
+   itself; see :option:`UNOPTFLAT`.

   For example, Verilator will internally convert a variable with the
   metacomment such as:
@@ -465,12 +507,12 @@ or "`ifdef`"'s may break other tools.
         logic [7:0] x__BRA__1__KET__ /*verilator split_var*/;

   Note that the generated packed variables retain the split_var
-   metacomment because they may be split into further smaller pieces
-   according to the access patterns.
+   metacomment because they may be split into smaller pieces according to
+   the access patterns.

   This only supports unpacked arrays, packed arrays, and packed structs of
-   integer types (reg, logic, bit, byte, int...); otherwise if a split was
-   requested but cannot occur a SPLITVAR warning is issued.  Splitting
+   integer types (reg, logic, bit, byte, int...); otherwise, if a split was
+   requested but cannot occur, a SPLITVAR warning is issued.  Splitting
   large arrays may slow down the Verilation speed, so use this only on
   variables that require it.

@@ -482,14 +524,47 @@ or "`ifdef`"'s may break other tools.
   Verilator) text that should be passed through to the XML output as a tag,
   for use by downstream applications.

+.. option:: /*verilator&32;timing_off*/
+
+   Ignore all timing constructs after this metacomment. All timing controls
+   behave as if they were not there (the same way as with
+   :option:`--no-timing`), and :code:`fork`/:code:`join*` blocks are
+   converted into :code:`begin`/:code:`end` blocks.
+
+   Same as :option:`timing_off` configuration file option.
+
+.. option:: /*verilator&32;timing_on*/
+
+   Re-enable all timing constructs after this metacomment (only applicable
+   after :option:`timing_off`).
+
+   Same as :option:`timing_on` configuration file option.
+
+.. option:: /*verilator&32;trace_init_task*/
+
+   Attached to a DPI import to indicate that function should be called when
+   initializing tracing. This attribute is indented only to be used
+   internally in code that Verilator generates when :vlopt:`--lib-create`
+   or :vlopt:`--hierarchical` is used along with :vlopt:`--trace`.
+
 .. option:: /*verilator&32;tracing_off*/

-   Disable waveform tracing for all future signals that are declared in
-   this module, or instances below this module.  Often this is placed just
-   after a primitive's module statement, so that the entire module and
-   instances below it are not traced.
+   Disable waveform tracing for all future signals declared in this module,
+   or instances below this module.  Often this is placed just after a
+   primitive's module statement, so that the entire module and instances
+   below it are not traced.

 .. option:: /*verilator&32;tracing_on*/

   Re-enable waveform tracing for all future signals or instances that are
   declared.
+
+.. option:: $stacktrace
+
+   Called as a task, print a stack trace.  Called as a function, return a
+   string with a stack trace.  This relies on the C++ system trace, which
+   may give less meaningful results if the model is not compiled with debug
+   symbols.  Also, the data represents the C++ stack; the SystemVerilog
+   functions/tasks involved may be renamed and/or inlined before becoming
+   the C++ functions that may be visible in the stack trace.  This
+   extension is experimental and may be removed without deprecation.
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 ******************************
@@ -14,8 +14,8 @@ Can I contribute?
 """""""""""""""""

 Please contribute!  Just submit a pull request, or raise an issue to
-discuss if looking for something to help on.  For more information see our
-contributor agreement.
+discuss if you are looking for something to help on.  For more information
+see our contributor agreement.


 How widely is Verilator used?
@@ -24,7 +24,7 @@ How widely is Verilator used?
 Verilator is used by many of the largest silicon design companies, large
 organizations such as CERN, and even by college student projects.

-Verilator is one of the "big 4" simulators, meaning one of the 4 main
+Verilator is one of the "big 4" simulators, meaning one of the four leading
 SystemVerilog simulators available, namely the closed-source products Synopsys
 VCS (tm), Mentor Questa/ModelSim (tm), Cadence
 Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator.
@@ -35,15 +35,17 @@ simulators.
 Does Verilator run under Windows?
 """""""""""""""""""""""""""""""""

-Yes, using Cygwin.  Verilated output also compiles under Microsoft Visual
-C++, but this is not tested every release.
+Yes, ideally, run Ubuntu under Windows Subsystem for Linux (WSL2).
+Alternatively, use Cygwin, though this tends to be slower and is not
+regularly tested.  Verilated output also compiles under Microsoft Visual
+C++, but this is also not regularly tested.


 Can you provide binaries?
 """""""""""""""""""""""""

 You can install Verilator via the system package manager (apt, yum, etc.)
-on many Linux distributions, including Debian, Ubuntu, SuSE, RedHat, and
+on many Linux distributions, including Debian, Ubuntu, SuSE, Red Hat, and
 others.  These packages are provided by the Linux distributions and
 generally will lag the version of the mainline Verilator repository.  If no
 binary package is available for your distribution, how about you set one
@@ -56,37 +58,52 @@ How can it be faster than (name-a-big-3-closed-source-simulator)?
 Generally, the implied part of the question is "... with all of the
 manpower they can put into developing it."

-Most simulators have to be compliant with the complete IEEE 1364 (Verilog)
-and IEEE 1800 (SystemVerilog) standards, meaning they have to be event
-driven.  This prevents them from being able to reorder blocks and make
-netlist-style optimizations, which are where most of the gains come from.
+Most simulators must comply with the complete IEEE 1364 (Verilog) and IEEE
+1800 (SystemVerilog) standards, meaning they have to be event-driven.  This
+prevents them from being able to reorder blocks and make netlist-style
+optimizations, which are where most of the gains come from.

 You should not be scared by non-compliance.  Your synthesis tool isn't
 compliant with the whole standard to start with, so your simulator need not
-be either.  Verilator is closer to the synthesis interpretation, so this is
+be either.  Verilator is closer to the synthesis interpretation, which is
 a good thing for getting working silicon.


 Will Verilator output remain under my own license/copyright?
 """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""

-Yes, it's just like using GCC on your programs; this is why Verilator uses
-the "GNU **Lesser** Public License Version 3" instead of the more typical
-"GNU Public License".  See the licenses for details, but in brief, if you
-change Verilator itself or the header files Verilator includes, you must
-make the source code available under the GNU Lesser Public License.
-However, Verilator output (the Verilated code) only "include"s the licensed
-files, and so you are **not** required to open-source release any output
-from Verilator.
+Your SystemVerilog, VPI/DPI, or main() C++ code remains under your own license.
+
+It's just like how using GCC on your programs does not change the copyright
+of your program; this is why Verilator uses the "GNU **Lesser** Public
+License Version 3" instead of the more typical "GNU Public License".  See
+the licenses for details.
+
+Some examples:
+
+* Any SystemVerilog or other input fed into Verilator remains your own.
+
+* Any of your VPI/DPI C++ routines that Verilator calls remain your own.
+
+* Any of your main() C++ code that calls into Verilator remains your own.
+
+* If you change Verilator itself, for example, changing or adding a file
+  under the src/ directory in the repository, you must make the source code
+  available under the GNU Lesser Public License.
+
+* If you change a header Verilator provides, for example, under include/ in
+  the repository, you must make the source code available under the GNU
+  Lesser Public License.

 You also have the option of using the Perl Artistic License, which again
-does not require you to release your Verilog or generated code, and also
-allows you to modify Verilator for internal use without distributing the
-modified version.  But please contribute back to the community!
+does not require you to release your Verilog, C++, or generated code. This
+license also allows you to modify Verilator for internal use without
+distributing the modified version.  But please contribute back to the
+community!

-One limit is that you cannot under either license release a closed-source
-Verilog simulation product incorporating Verilator. That is you can have a
-commercial product, but must make the source code available.
+Under both licenses, you can offer a commercial product based on
+Verilator directly or embedded within.  However, under both licenses,
+any changes you make to Verilator for such a product must be open-sourced.

 As is standard with Open Source, contributions back to Verilator will be
 placed under the Verilator copyright and LGPL/Artistic license.  Small test
@@ -97,11 +114,11 @@ and large tests under the LGPL/Artistic, unless requested otherwise.
 Why is running Verilator (to create a model) so slow?
 """""""""""""""""""""""""""""""""""""""""""""""""""""

-Verilator may require more memory than the resulting simulator will
-require, as Verilator internally creates all of the state of the resulting
-generated simulator in order to optimize it.  If it takes more than a few
+Verilator may require more memory than the resulting simulation,
+as Verilator internally creates all of the state of the resulting
+generated simulator to optimize it.  If it takes more than a few
 minutes or so (and you're not using :vlopt:`--debug` since debug mode is
-disk bound), see if your machine is paging; most likely you need to run it
+disk bound), see if your machine is paging; most likely, you need to run it
 on a machine with more memory. Very large designs are known to have topped
 64 GB resident set size.  Alternatively, see :ref:`Hierarchical Verilation`.

@@ -111,14 +128,14 @@ How do I generate waveforms (traces) in C++?

 See also the next question for tracing in SystemC mode.

-A. Pass the :vlopt:`--trace` option to Verilator, and in your top level C
+A. Pass the :vlopt:`--trace` option to Verilator, and in your top-level C
   code, call ``Verilated::traceEverOn(true)``.  Then you may use
-   ``$dumpfile`` and ``$dumpvars`` to enable traces, same as with any
+   ``$dumpfile`` and ``$dumpvars`` to enable traces, the same as with any
   Verilog simulator. See ``examples/make_tracing_c`` in the distribution.

 B. Or, for finer-grained control, or C++ files with multiple Verilated
-   modules you may also create the trace purely from C++.  Create a
-   VerilatedVcdC object, and in your main loop right after ``eval()`` call
+   modules, you may also create the trace purely from C++.  Create a
+   VerilatedVcdC object, and in your main loop, right after ``eval()`` call
   ``trace_object->dump(contextp->time())`` every time step, and finally
   call ``trace_object->close()``.

@@ -127,12 +144,13 @@ B. Or, for finer-grained control, or C++ files with multiple Verilated

      #include "verilated_vcd_c.h"
      ...
-      int main(int argc, char** argv, char** env) {
+      int main(int argc, char** argv) {
          const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
          ...
          Verilated::traceEverOn(true);
          VerilatedVcdC* tfp = new VerilatedVcdC;
-          topp->trace(tfp, 99);  // Trace 99 levels of hierarchy
+          topp->trace(tfp, 99);  // Trace 99 levels of hierarchy (or see below)
+          // tfp->dumpvars(1, "t");  // trace 1 level under "t"
          tfp->open("obj_dir/t_trace_ena_cc/simx.vcd");
          ...
          while (contextp->time() < sim_time && !contextp->gotFinish()) {
@@ -145,8 +163,8 @@ B. Or, for finer-grained control, or C++ files with multiple Verilated

 You also need to compile :file:`verilated_vcd_c.cpp` and add it to your
 link, preferably by adding the dependencies in your Makefile's
-:code:`$(VK_GLOBAL_OBJS)` link rule.  This is done for you if using the
-Verilator :vlopt:`--exe` option.
+:code:`$(VK_GLOBAL_OBJS)` link rule.  This is done for you if you are using
+the Verilator :vlopt:`--binary` or :vlopt:`--exe` option.

 you can call :code:`trace_object->trace()` on multiple Verilated objects
 with the same trace file if you want all data to land in the same output
@@ -156,22 +174,22 @@ file.
 How do I generate waveforms (traces) in SystemC?
 """"""""""""""""""""""""""""""""""""""""""""""""

-A. Pass the :vlopt:`--trace` option to Verilator, and in your top level
+A. Pass the :vlopt:`--trace` option to Verilator, and in your top-level
   :code:`sc_main()`, call :code:`Verilated::traceEverOn(true)`.  Then you
-   may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, same as
-   with any Verilog simulator, see the non-SystemC example in
+   may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, as
+   with any Verilog simulator; see the non-SystemC example in
   :file:`examples/make_tracing_c`. This will trace only the module
   containing the :code:`$dumpvar`.

 B. Or, you may create a trace purely from SystemC, which may trace all
   Verilated designs in the SystemC model. Create a VerilatedVcdSc object
-   as you would create a normal SystemC trace file.  For an example, see
+   as you would create a standard SystemC trace file.  For an example, see
   the call to ``VerilatedVcdSc`` in the
   :file:`examples/make_tracing_sc/sc_main.cpp` file of the distribution,
   and below.

-C. Alternatively you may use the C++ trace mechanism described in the
-   previous question, note the timescale and timeprecision will be
+C. Alternatively, you may use the C++ trace mechanism described in the
+   previous question; note that the timescale and timeprecision will be
   inherited from your SystemC settings.

   .. code-block:: C++
@@ -179,7 +197,7 @@ C. Alternatively you may use the C++ trace mechanism described in the

      #include "verilated_vcd_sc.h"
      ...
-      int main(int argc, char** argv, char** env) {
+      int main(int argc, char** argv) {
          ...
          Verilated::traceEverOn(true);
          VerilatedVcdSc* tfp = new VerilatedVcdSc;
@@ -196,13 +214,14 @@ C. Alternatively you may use the C++ trace mechanism described in the
 You also need to compile :file:`verilated_vcd_sc.cpp` and
 :file:`verilated_vcd_c.cpp` and add them to your link, preferably by adding
 the dependencies in your Makefile's :code:`$(VK_GLOBAL_OBJS)` link rule.
-This is done for you if using the Verilator :vlopt:`--exe` option.
+This is done for you if you are using the Verilator :vlopt:`--binary` or
+:vlopt:`--exe` option.

 You can call :code:`->trace()` on multiple Verilated objects with the same
 trace file if you want all data to land in the same output file.

 When using SystemC 2.3, the SystemC library must have been built with the
-experimental simulation phase callback based tracing disabled. This is
+experimental simulation phase callback-based tracing disabled. This is
 disabled by default when building SystemC with its configure based build
 system, but when building SystemC with CMake, you must pass
 ``-DENABLE_PHASE_CALLBACKS_TRACING=OFF`` to disable this feature.
@@ -224,7 +243,7 @@ Or, in C++ change the include described in the VCD example above:
      VerilatedFstC* tfp = new VerilatedFstC;


-Or, in SystemC change the include described in the VCD example above:
+Or, in SystemC, change the include described in the VCD example above:

 .. code-block:: C++

@@ -232,17 +251,16 @@ Or, in SystemC change the include described in the VCD example above:
      VerilatedFstC* tfp = new VerilatedFstSc;


-Note that currently supporting both FST and VCD in a single simulation is
-impossible, but such requirement should be rare.  You can however ifdef
-around the trace format in your C++ main loop, and select VCD or FST at
-build time, should you require.
+Currently, supporting FST and VCD in a single simulation is impossible, but
+such requirement should be rare.  You can however ifdef around the trace
+format in your C++ main loop, and select VCD or FST at compile time.


 How do I view waveforms (aka dumps or traces)?
 """"""""""""""""""""""""""""""""""""""""""""""

 Verilator creates standard VCD (Value Change Dump) and FST files.  VCD
-files are viewable with the open source GTKWave (recommended) or Dinotrace
+files are viewable with the open-source GTKWave (recommended), or Dinotrace
 (legacy) programs, or any of the many closed-source offerings; FST is
 supported only by GTKWave.

@@ -255,20 +273,20 @@ A. Instead of calling ``VerilatedVcdC->open`` or ``$dumpvars`` at the
   tracing to begin.

 B. Add the :option:`/*verilator&32;tracing_off*/` metacomment to any very
-   low level modules you never want to trace (such as perhaps library
+   low-level modules you never want to trace (such as perhaps library
   cells).

-C. Use the :vlopt:`--trace-depth` option to limit the depth of tracing, for
-   example :vlopt:`--trace-depth 1 <--trace-depth>` to see only the top
-   level signals.
+C. Use the :vlopt:`--trace-depth` option to limit the tracing depth, for
+   example :vlopt:`--trace-depth 1 <--trace-depth>` to see only the
+   top-level signals.

 D. You can also consider using FST tracing instead of VCD. FST dumps are a
   fraction of the size of the equivalent VCD. FST tracing can be slower
   than VCD tracing, but it might be the only option if the VCD file size
   is prohibitively large.

-E. Be sure you write your trace files to a local solid-state drive, instead
-   of to a network drive.  Network drives are generally far slower.
+E. Write your trace files to a machine-local solid-state drive instead of a
+   network drive.  Network drives are generally far slower.


 Where is the translate_off command?  (How do I ignore a construct?)
@@ -295,7 +313,7 @@ Why do I get "unexpected 'do'" or "unexpected 'bit'" errors?

 The words \ ``do``\ , \ ``bit``\ , \ ``ref``\ , \ ``return``\ , and others
 are reserved keywords in SystemVerilog.  Older Verilog code might use these
-as identifiers.  You should change your code to not use them to ensure it
+as identifiers, and you should change your code to not use them to ensure it
 works with newer tools.  Alternatively, surround them by the Verilog
 2005/SystemVerilog begin_keywords pragma to indicate Verilog 2001 code.

@@ -307,7 +325,7 @@ works with newer tools.  Alternatively, surround them by the Verilog
   `end_keywords


-If you want the whole design to be parsed as Verilog 2001, see the
+If you want the whole design parsed as Verilog 2001, see the
 :vlopt:`--default-language` option.


@@ -324,11 +342,11 @@ Why do I get "undefined reference to sc_time_stamp()?

 In Verilator 4.200 and later, using the timeInc function is recommended
 instead.  See the :ref:`Connecting to C++` examples.  Some linkers (MSVC++)
-still require :code:`sc_time_stamp()` to be defined, either define this
+still require :code:`sc_time_stamp()` to be defined; either define this
 with :code:`double sc_time_stamp() { return 0; }` or compile the Verilated
 code with :code:`-CFLAGS -DVL_TIME_CONTEXT`.

-Prior to Verilator 4.200, the :code:`sc_time_stamp()` function needs to be
+Before Verilator 4.200, the :code:`sc_time_stamp()` function needs to be
 defined in C++ (non SystemC) to return the current simulation time.


@@ -351,17 +369,17 @@ also use the "import DPI" SystemVerilog feature to call C code (see the
 chapter above).  There is also limited VPI access to public signals.

 If you want something more complex, since Verilator emits standard C++
-code, you can simply write your own C++ routines that can access and modify
-signal values without needing any PLI interface code, and call it with
+code, you can write C++ routines that can access and modify signal
+values without needing any PLI interface code, and call it with
 $c("{any_c++_statement}").

 See the :ref:`Connecting` section.


-How do I make a Verilog module that contain a C++ object?
-"""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+How do I make a Verilog module that contains a C++ object?
+""""""""""""""""""""""""""""""""""""""""""""""""""""""""""

-You need to add the object to the structure that Verilator creates, then
+You need to add the object to the structure Verilator creates, then
 use $c to call a method inside your object.  The
 :file:`test_regress/t/t_extend_class` files in the distribution show an
 example of how to do this.
@@ -370,9 +388,9 @@ example of how to do this.
 How do I get faster build times?
 """"""""""""""""""""""""""""""""

-* When running make, pass the make variable VM_PARALLEL_BUILDS=1 so that
+* When running make, pass the make variable VM_PARALLEL_BUILDS=1, so that
  builds occur in parallel. Note this is now set by default if an output
-  file was large enough to be split due to the :vlopt:`--output-split`
+  file is large enough to be split due to the :vlopt:`--output-split`
  option.

 * Verilator emits any infrequently executed "cold" routines into separate
@@ -383,17 +401,17 @@ How do I get faster build times?
 * Use a recent compiler.  Newer compilers tend to be faster.

 * Compile in parallel on many machines and use caching; see the web for the
-  ccache, distcc and icecream packages. ccache will skip GCC runs between
+  ccache, distcc, and icecream packages. ccache will skip GCC runs between
  identical source builds, even across different users.  If ccache was
-  installed when Verilator was built it is used, or see OBJCACHE
+  installed when Verilator was built, it is used, or see OBJCACHE
  environment variable to override this. Also see the
-  :vlopt:`--output-split` option and :ref: `Profiling ccache efficiency`
+  :vlopt:`--output-split` option and :ref: `Profiling ccache efficiency`.

-* To reduce the compile time of classes that use a Verilated module (e.g. a
+* To reduce the compile time of classes that use a Verilated module (e.g., a
  top CPP file) you may wish to add a
-  :option:`/*verilator&32;no_inline_module*/` metacomment to your top level
+  :option:`/*verilator&32;no_inline_module*/` metacomment to your top-level
  module. This will decrease the amount of code in the model's Verilated
-  class, improving compile times of any instantiating top level C++ code,
+  class, improving compile times of any instantiating top-level C++ code,
  at a relatively small cost of execution performance.

 * Use :ref:`hierarchical verilation`.
@@ -403,7 +421,7 @@ Why do so many files need to recompile when I add a signal?
 """""""""""""""""""""""""""""""""""""""""""""""""""""""""""

 Adding a new signal requires the symbol table to be recompiled.  Verilator
-uses one large symbol table, as that results in 2-3 less assembly
+uses one large symbol table, resulting in 2-3 fewer assembly
 instructions for each signal access.  This makes the execution time 10-15%
 faster, but can result in more compilations when something changes.

@@ -431,8 +449,8 @@ How do I access signals in C?

 The best thing to do is to make a SystemVerilog "export DPI" task or
 function that accesses that signal, as described in the DPI chapter in the
-manual and DPI tutorials on the web.  This will allow Verilator to better
-optimize the model and should be portable across simulators.
+manual and DPI tutorials on the web.  This will allow Verilator to
+optimize the model better and should be portable across simulators.

 If you really want raw access to the signals, declare the signals you will
 be accessing with a :option:`/*verilator&32;public*/` metacomment before
@@ -441,17 +459,17 @@ the signal, as you would any other member variable.

 Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t),
 16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or
-64-bit unsigned long longs (uint64_t) that fits the width of the signal.
-Generally, you can use just uint32_t's for 1 to 32 bits, or vluint64_t for
+64-bit unsigned long longs (uint64_t) that fit the width of the signal.
+Generally, you can use just uint32_t's for 1 to 32 bits, or uint64_t for
 1 to 64 bits, and the compiler will properly up-convert smaller entities.
-Note even signed ports are declared as unsigned; you must sign extend
+Note that even signed ports are declared as unsigned; you must sign extend
 yourself to the appropriate signal width.

 Signals wider than 64 bits are stored as an array of 32-bit uint32_t's.
-Thus to read bits 31:0, access signal[0], and for bits 63:32, access
-signal[1].  Unused bits (for example bit numbers 65-96 of a 65-bit vector)
-will always be zero.  If you change the value you must make sure to pack
-zeros in the unused bits or core-dumps may result, because Verilator strips
+Thus, to read bits 31:0, access signal[0], and for bits 63:32, access
+signal[1].  Unused bits (for example, bit numbers 65-96 of a 65-bit vector)
+will always be zero.  If you change the value, you must pack
+zeros in the unused bits, or core-dumps may result because Verilator strips
 array bound checks where it believes them to be unnecessary to improve
 performance.

@@ -472,16 +490,16 @@ From the sc_main.cpp file, you'd then:


 In this example, clk is a bool you can read or set as any other variable.
-The value of normal signals may be set, though clocks shouldn't be changed
-by your code or you'll get strange results.
+The value of normal signals may be set, though your code shouldn't change
+clocks, or you'll get strange results.


 Should a module be in Verilog or SystemC?
 """""""""""""""""""""""""""""""""""""""""

-Sometimes there is a block that just interconnects instances, and have a
-choice as to if you write it in Verilog or SystemC.  Everything else being
-equal, best performance is when Verilator sees all of the design.  So, look
+Sometimes there is a block that only interconnects instances, and you have a
+choice if you write it in Verilog or SystemC.  Everything else being
+equal, the best performance is when Verilator sees all of the design.  So, look
 at the hierarchy of your design, labeling instances as to if they are
 SystemC or Verilog.  Then:

@@ -492,6 +510,6 @@ SystemC or Verilog.  Then:

 * A module with only Verilog instances below can be either, but for best
  performance should be Verilog.  (The exception is if you have a design
-  that is instantiated many times; in this case Verilating one of the lower
+  that is instantiated many times; in this case, Verilating one of the lower
  modules and instantiating that Verilated instances multiple times into a
  SystemC module *may* be faster.)
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 *****
@@ -50,7 +50,7 @@ For --cc/--sc, it creates:
     - Make include file with class names (from --make gmake)
   * - *{prefix}*\ _hier.mk
     - Make file for hierarchy blocks (from --make gmake)
-   * - *{prefix|*\ _hierMkArgs.f
+   * - *{prefix}*\ _hierMkArgs.f
     - Arguments for hierarchical Verilation (from --make gmake)
   * - *{prefix}*\ _hierCMakeArgs.f
     - Arguments for hierarchical Verilation (from --make cmake)
@@ -59,16 +59,20 @@ For --cc/--sc, it creates:
   * - *{prefix}*\ .cpp
     - Model C++ file
   * - *{prefix}*\ ___024root.h
-     - Top level (SystemVerilog $root) internal header file
+     - Top-level internal header file (from SystemVerilog $root)
   * - *{prefix}*\ ___024root.cpp
-     - Top level (SystemVerilog $root) internal C++ file
-   * - *{prefix}*___024root*{__n}*\ .cpp
-     - Additional top level internal C++ files (from --output-split)
+     - Top-level internal C++ file (from SystemVerilog $root)
+   * - *{prefix}*\ ___024root\ *{__n}*\ .cpp
+     - Additional top-level internal C++ files
+   * - *{prefix}*\ ___024root\ *{__DepSet_hash__n}*\ .cpp
+     - Additional top-level internal C++ files (hashed to reduce build times)
   * - *{prefix}*\ ___024root__Slow\ *{__n}*\ .cpp
     - Infrequent cold routines
-   * - *{prefix}*\ ___024root__Trace{__n}*\ .cpp
+   * - *{prefix}*\ ___024root\ *{__DepSet_hash__n}*\ .cpp
+     - Infrequent cold routines (hashed to reduce build times)
+   * - *{prefix}*\ ___024root__Trace\ *{__n}*\ .cpp
     - Wave file generation code (from --trace)
-   * - *{prefix}*\ ___024root__Trace__Slow{__n}*\ .cpp
+   * - *{prefix}*\ ___024root__Trace__Slow\ *{__n}*\ .cpp
     - Wave file generation code (from --trace)
   * - *{prefix}*\ __Dpi.h
     - DPI import and export declarations (from --dpi)
@@ -87,7 +91,9 @@ For --cc/--sc, it creates:
   * - *{prefix}{each_verilog_module}*\ .cpp
     - Lower level internal C++ files
   * - *{prefix}{each_verilog_module}{__n}*\ .cpp
-     - Additional lower C++ files (from --output-split)
+     - Additional lower C++ files
+   * - *{prefix}{each_verilog_module}{__DepSet_hash__n}*\ .cpp
+     - Additional lower C++ files (hashed to reduce build times)

 For --hierarchy mode, it creates:

@@ -100,7 +106,7 @@ For --hierarchy mode, it creates:
   * - *{prefix}*\ __hier.dir
     - Directory to store .dot, .vpp, .tree of top module (from --hierarchy)

-In certain debug and other modes, it also creates:
+In specific debug and other modes, it also creates:

 .. list-table::

@@ -120,7 +126,7 @@ In certain debug and other modes, it also creates:
     - Debugging graph files (from --debug)
   * - *{prefix}{misc}*\ .tree
     - Debugging files (from --debug)
-   * - {mod_prefix}_{each_verilog_module}*{__n}*\ .vpp
+   * - {mod_prefix}_{each_verilog_base_filename}*\ .vpp
     - Pre-processed verilog (from --debug)

 After running Make, the C++ compiler may produce the following:
@@ -155,13 +161,13 @@ The Verilated executable may produce the following:
   * - gmon.out
     - GCC/clang code profiler output, often fed into :command:`verilator_profcfunc`
   * - profile.vlt
-     - -profile data file for :ref:`Thread PGO`
-   * - profile_threads.dat
-     - -profile-threads data file for :command:`verilator_gnatt`
+     - --prof-pgo data file for :ref:`Thread PGO`
+   * - profile_exec.dat
+     - --prof-exec data file for :command:`verilator_gantt`

 Verilator_gantt may produce the following:

 .. list-table::

-   * - profile_threads.vcd
+   * - profile_exec.vcd
     - Gantt report waveform output
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 ######################
@@ -12,6 +12,7 @@ Verilator User's Guide
   overview.rst
   examples.rst
   install.rst
+   install-cmake.rst


 .. toctree::
@@ -0,0 +1,72 @@
+.. Copyright 2003-2023 by Wilson Snyder.
+.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+.. _CMakeInstallation:
+
+******************
+CMake Installation
+******************
+
+This section discusses how to build and install Verilator using cmake.
+Currently cmake is only officially supported for Windows builds (not Linux).
+
+.. _Tools Install:
+
+Quick Install
+=============
+
+1. Install Python for your platform from https://www.python.org/downloads/.
+2. Install CMake for your platform from https://cmake.org/download/ or build it from source.
+3. If the compiler of your choice is MSVC, then install https://visualstudio.microsoft.com/downloads/.
+   If the compiler of your choice is Clang, then install https://releases.llvm.org/download.html or build it from source.
+4. For flex and bison use https://github.com/lexxmark/winflexbison to build and install.
+5. For build on Windows using MSVC set environment variable WIN_FLEX_BISON to install directory.
+   For build on Windows/Linux/OS-X using ninja set the environment variable
+   FLEX_INCLUDE to the directory containing FlexLexer.h and ensure that flex/bison
+   is available within the PATH.
+
+To obtain verilator sources download https://github.com/verilator/verilator/archive/refs/heads/master.zip
+or clone https://github.com/verilator/verilator using git :ref:`Obtain Sources`.
+
+To build using MSVC:
+
+::
+
+   cd verilator  # directory containing source files of verilator
+   mkdir build
+   cmake .. -DCMAKE_BUILD_TYPE=Release --install-prefix $PWD/../install
+   cmake --build . --config Release
+   cmake --install . --prefix $PWD/../install
+
+
+To build using ninja:
+
+::
+
+    cd verilator
+    mkdir build
+    cmake -G Ninja .. -DCMAKE_BUILD_TYPE=Release --install-prefix $PWD/../install -DCMAKE_MAKE_PROGRAM=<path to ninja binary> -DBISON_EXECUTABLE=<path to bison> -DFLEX_EXECUTABLE=<path to flex>
+    <path to ninja binary> #execute ninja
+    cmake --install . --prefix $PWD/../install
+
+
+.. _CMake Usage:
+
+Usage
+=====
+
+To use Verilator set the environment variable ``VERILATOR_ROOT`` to the
+install directory specified in the above build.
+
+Example
+=======
+
+::
+
+    cd verilator/examples
+    cd cmake_hello_c
+    mkdir build
+    cd build
+    cmake ..  # cmake -G Ninja ..
+    cmake --build . --config Release # ninja
+    # execute the generated binary
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 .. _Installation:
@@ -16,14 +16,14 @@ Package Manager Quick Install

 Using a distribution's package manager is the easiest way to get
 started. (Note packages are unlikely to have the most recent version, so
-:ref:`Git Install`, might be a better alternative.) To install as a
+:ref:`Git Install` might be a better alternative.) To install as a
 package:

 ::

   apt-get install verilator   # On Ubuntu

-For other distributions refer to `Repology Verilator Distro Packages
+For other distributions, refer to `Repology Verilator Distro Packages
 <https://repology.org/project/verilator>`__.

 .. _Git Install:
@@ -31,8 +31,8 @@ For other distributions refer to `Repology Verilator Distro Packages
 Git Quick Install
 =================

-Installing Verilator from Git provides the most flexibility. For additional
-options and details see :ref:`Detailed Build Instructions` below.
+Installing Verilator from Git provides the most flexibility; for additional
+options and details, see :ref:`Detailed Build Instructions` below.

 In brief, to install from git:

@@ -68,7 +68,7 @@ In brief, to install from git:
 Detailed Build Instructions
 ===========================

-This section describes details of the build process, and assumes you are
+This section describes details of the build process and assumes you are
 building from Git. For using a pre-built binary for your Linux
 distribution, see instead :ref:`Package Manager Quick Install`.

@@ -77,34 +77,41 @@ OS Requirements
 ---------------

 Verilator is developed and has primary testing on Ubuntu, with additional
-testing on FreeBSD and Apple OS-X. Versions have also built on Redhat
-Linux, HPUX and Solaris. It should run with minor porting on any
-GNU/Linux-ish platform. Verilator also works on Windows under Cygwin, and
-Windows under MinGW (gcc -mno-cygwin). Verilated output (not Verilator
-itself) compiles under all the options above, plus using MSVC++.
+testing on FreeBSD and Apple OS-X. Versions have also been built on Red Hat
+Linux, other flavors of GNU/Linux-ish platforms, Windows Subsystem for
+Linux (WSL2), Windows under Cygwin, and Windows under MinGW (gcc
+-mno-cygwin). Verilated output (not Verilator itself) compiles under all
+the options above, plus using MSVC++.


 Install Prerequisites
 ---------------------

-To build or run Verilator you need these standard packages:
+To build or run Verilator, you need these standard packages:

 ::

-   sudo apt-get install git perl python3 make
+   sudo apt-get install git help2man perl python3 make
   sudo apt-get install g++  # Alternatively, clang
   sudo apt-get install libgz  # Non-Ubuntu (ignore if gives error)
   sudo apt-get install libfl2  # Ubuntu only (ignore if gives error)
   sudo apt-get install libfl-dev  # Ubuntu only (ignore if gives error)
   sudo apt-get install zlibc zlib1g zlib1g-dev  # Ubuntu only (ignore if gives error)

-To build or run the following are optional but should be installed for good
-performance:
+To build or run Verilator, the following are optional but should be installed
+for good performance:

 ::

   sudo apt-get install ccache  # If present at build, needed for run
-   sudo apt-get install libgoogle-perftools-dev numactl perl-doc
+   sudo apt-get install libgoogle-perftools-dev numactl
+
+The following is optional but is recommended for nicely rendered command line
+help when running Verilator:
+
+::
+
+   sudo apt-get install perl-doc

 To build Verilator you will need to install these packages; these do not
 need to be present to run Verilator:
@@ -117,8 +124,9 @@ Those developing Verilator itself may also want these (see internals.rst):

 ::

-   sudo apt-get install gdb graphviz cmake clang clang-format-11 gprof lcov
-   sudo pip3 install sphinx sphinx_rtd_theme breathe
+   sudo apt-get install gdb graphviz cmake clang clang-format-14 gprof lcov
+   sudo apt-get install libclang-dev yapf3
+   sudo pip3 install clang sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe
   cpan install Pod::Perldoc
   cpan install Parallel::Forker

@@ -142,16 +150,18 @@ To make use of Verilator FST tracing you will want `GTKwave
 required at Verilator build time.


+.. _Obtain Sources:
+
 Obtain Sources
 --------------

-Get the sources from the git repository: (You need do this only once,
+Get the sources from the git repository: (You need to do this only once,
 ever.)

 ::

   git clone https://github.com/verilator/verilator   # Only first time
-   ## Note the URL above is not a page you can see with a browser, it's for git only
+   ## Note the URL above is not a page you can see with a browser; it's for git only

 Enter the checkout and determine what version/branch to use:

@@ -178,7 +188,7 @@ Create the configuration script:
 Eventual Installation Options
 -----------------------------

-Before configuring the build, you have to decide how you're going to
+Before configuring the build, you must decide how you're going to
 eventually install Verilator onto your system. Verilator will be compiling
 the current value of the environment variables :option:`VERILATOR_ROOT`,
 :option:`SYSTEMC_INCLUDE`, and :option:`SYSTEMC_LIBDIR` as defaults into
@@ -212,8 +222,8 @@ the path to all needed files.

 You may eventually be installing onto a project/company-wide "CAD" tools
 disk that may support multiple versions of every tool. Tell configure the
-eventual destination directory name.  We recommend the destination location
-include the Verilator version name:
+eventual destination directory name.  We recommend that the destination
+location include the Verilator version name:

 ::

@@ -247,7 +257,7 @@ as most GNU tools support:
   unsetenv VERILATOR_ROOT   # if your shell is csh
   ./configure --prefix /opt/verilator-VERSION

-Then after installing (below steps) you will need to add
+Then after installing (below steps), you will need to add
 ``/opt/verilator-VERSION/bin`` to your ``$PATH`` environment variable.


@@ -263,7 +273,7 @@ configure's default system paths:
   unsetenv VERILATOR_ROOT   # if your shell is csh
   ./configure

-Then after installing (below) the binaries should be in a location that is
+Then after installing (below), the binaries should be in a location
 already in your ``$PATH`` environment variable.


@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 ***************
@@ -41,7 +41,7 @@ union, var, void, priority case/if, and unique case/if.
 It also supports .name and .\* interconnection.

 Verilator partially supports concurrent assert and cover statements; see
-the enclosed coverage tests for the syntax which is allowed.
+the enclosed coverage tests for the allowed syntax.

 Verilator has limited support for class and related object-oriented
 constructs.
@@ -58,8 +58,8 @@ function call-like preprocessor defines, default define arguments,
 SystemVerilog 2017 (IEEE 1800-2017) Support
 -------------------------------------------

-Verilator supports the 2017 "for" loop constructs, and several minor
-cleanups IEEE made in 1800-2017.
+Verilator supports the 2017 "for" loop constructs and several cleanups IEEE
+made in 1800-2017.


 Verilog AMS Support
@@ -67,32 +67,97 @@ Verilog AMS Support

 Verilator implements a very small subset of Verilog AMS (Verilog Analog and
 Mixed-Signal Extensions) with the subset corresponding to those VMS
-keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009
-languages.
+keywords with near-equivalents in Verilog 2005 or SystemVerilog 2017.

 AMS parsing is enabled with :vlopt:`--language VAMS <--language>` or
 :vlopt:`--language 1800+VAMS <--language>`.

-At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt,
-string, and wreal.
+Verilator implements ceil, exp, floor, ln, log, pow, sqrt, string, and
+wreal.


 Synthesis Directive Assertion Support
 -------------------------------------

-With the :vlopt:`--assert` option, Verilator reads any :code:`//synopsys
-full_case` or :code:`//synopsys parallel_case` directives.  The same
-applies to any :code:`//ambit synthesis`, :code:`//cadence` or
-:code:`//pragma` directives of the same form.
+With the :vlopt:`--assert` option, Verilator reads any
+
+:code:`//synopsys full_case` or :code:`//synopsys parallel_case`
+directives.  The same applies to any :code:`//ambit synthesis`,
+:code:`//cadence` or :code:`//pragma` directives of the same form.

 When these synthesis directives are discovered, Verilator will either
-formally prove the directive to be true, or failing that, will insert the
+formally prove the directive to be true, or, failing that, will insert the
 appropriate code to detect failing cases at simulation runtime and print an
 "Assertion failed" error message.

 Verilator likewise also asserts any "unique" or "priority" SystemVerilog
-keywords on case statement, as well as "unique" on if statements.  However,
-"priority if" is currently simply ignored.
+keywords on case statements, as well as "unique" on if statements.  However,
+"priority if" is currently ignored.
+
+
+Time
+====
+
+With :vlopt:`--timing`, all timing controls are supported:
+
+* delay statements,
+* event control statements not only at the top of a process,
+* intra-assignment timing controls,
+* net delays,
+* :code:`wait` statements,
+
+as well as all flavors of :code:`fork`.
+
+Compiling a Verilated design that uses these features requires a
+compiler with C++20 coroutine support, e.g. Clang 5, GCC 10, or newer.
+
+:code:`#0` delays cause Verilator to issue the :option:`ZERODLY` warning, as
+they work differently than described in the LRM. They do not schedule process
+resumption in the Inactive region, though the process will get resumed in the
+same time slot.
+
+Rising/falling/turn-off delays are currently unsupported and cause the
+:option:`RISEFALLDLY` warning.
+
+Minimum/typical/maximum delays are currently unsupported. The typical delay is
+always the one chosen. Such expressions cause the :option:`MINTYPMAX` warning.
+
+Another consequence of using :vlopt:`--timing` is that the :vlopt:`--main`
+option generates a main file with a proper timing eval loop, eliminating the
+need for writing any driving C++ code. You can simply compile the
+simulation (perhaps using :vlopt:`--build`) and run it.
+
+With :vlopt:`--no-timing`, all timing controls cause the :option:`NOTIMING`
+error, except:
+
+* delay statements - they are ignored (as they are in synthesis), though they
+  do issue a :option:`STMTDLY` warning,
+* intra-assignment timing controls - they are ignored, though they do issue an
+  :option:`ASSIGNDLY` warning,
+* net delays - they are ignored,
+* event controls at the top of the procedure,
+
+Forks cause this error as well, except:
+
+* forks with no statements,
+* :code:`fork..join` or :code:`fork..join_any` with one statement,
+* forks with :vlopt:`--bbox-unsup`.
+
+If neither :vlopt:`--timing` nor :vlopt:`--no-timing` is specified, all
+timing controls cause the :option:`NEEDTIMINGOPT` error, except event
+controls at the top of the process. Forks cause this error as well, except:
+
+* forks with no statements,
+* :code:`fork..join` or :code:`fork..join_any` with one statement,
+* forks with :vlopt:`--bbox-unsup`.
+
+Timing controls and forks can also be ignored in specific files or parts of
+files. The :option:`/*verilator&32;timing_off*/` and
+:option:`/*verilator&32;timing_off*/` metacomments will make Verilator ignore
+the encompassed timing controls and forks, regardless of the chosen
+:vlopt:`--timing` or :vlopt:`--no-timing` option. This can also be achieved
+using the :option:`timing_off` and :option:`timing_off` options in Verilator
+configuration files.


 .. _Language Limitations:
@@ -108,15 +173,15 @@ Synthesis Subset

 Verilator supports the Synthesis subset with other verification constructs
 being added over time. Verilator also simulates events as Synopsys's Design
-Compiler would; namely given a block of the form:
+Compiler would, namely given a block of the form:

 .. code-block:: sv

        always @(x) y = x & z;

-This will recompute y when there is even a potential for change in x or a
-change in z, that is when the flops computing x or z evaluate (which is
-what Design Compiler will synthesize.)  A compliant simulator would only
+This will recompute y when there is a potential for change in x or a change
+in z; that is when the flops computing x or z evaluate (which is what
+Design Compiler will synthesize.)  A compliant simulator will only
 calculate y if x changes.  We recommend using always_comb to make the code
 run the same everywhere.  Also avoid putting $displays in combo blocks, as
 they may print multiple times when not desired, even on compliant
@@ -129,14 +194,14 @@ Signal Naming
 To avoid conflicts with C symbol naming, any character in a signal name
 that is not alphanumeric nor a single underscore will be replaced by __0hh
 where hh is the hex code of the character. To avoid conflicts with
-Verilator's internal symbols, any double underscore are replaced with
+Verilator's internal symbols, any double underscore is replaced with
 ___05F (5F is the hex code of an underscore.)


 Bind
 ----

-sVerilator only supports bind to a target module name, not to an
+Verilator only supports bind to a target module name, not to an
 instance path.


@@ -144,14 +209,13 @@ Class
 -----

 Verilator class support is limited but in active development.  Verilator
-supports members, and methods. Verilator does not support class static
-members, class extend, or class parameters.
+supports members, methods, class extend, and class parameters.


 Dotted cross-hierarchy references
 ---------------------------------

-Verilator supports dotted references to variables, functions and tasks in
+Verilator supports dotted references to variables, functions, and tasks in
 different modules. The portion before the dot must have a constant value;
 for example a[2].b is acceptable, while a[x].b is generally not.

@@ -165,7 +229,7 @@ code.
 Latches
 -------

-Verilator is optimized for edge sensitive (flop based) designs.  It will
+Verilator is optimized for edge-sensitive (flop-based) designs.  It will
 attempt to do the correct thing for latches, but most performance
 optimizations will be disabled around the latch.

@@ -174,55 +238,49 @@ Structures and Unions
 ---------------------

 Presently Verilator only supports packed structs and packed unions.  Rand
-and randc tags on members are simply ignored.  All structures and unions
-are represented as a single vector, which means that generating one member
-of a structure from blocking, and another from non-blocking assignments is
+and randc tags on members are ignored.  All structures and unions are
+represented as a single vector, which means that generating one member of a
+structure from blocking, and another from non-blocking assignments is
 unsupported.


-Time
----
-
-All delays (#) are ignored, as they are in synthesis.
-
-
 .. _Unknown States:

 Unknown States
 --------------

-Verilator is mostly a two state simulator, not a four state simulator.
-However, it has two features which uncover most initialization bugs
-(including many that a four state simulator will miss.)
+Verilator is mostly a two-state simulator, not a four-state simulator.
+However, it has two features that uncover most initialization bugs
+(including many that a four-state simulator will miss.)

 Identity comparisons (=== or !==) are converted to standard ==/!= when
 neither side is a constant.  This may make the expression yield a different
-result compared to a four state simulator.  An === comparison to X will
+result than a four-state simulator.  An === comparison to X will
 always be false, so that Verilog code which checks for uninitialized logic
 will not fire.

-Assigning X to a variable will actually assign a constant value as
-determined by the :vlopt:`--x-assign` option.  This allows runtime
-randomization, thus if the value is actually used, the random value should
-cause downstream errors.  Integers also get randomized, even though the
-Verilog 2001 specification says they initialize to zero.  Note however that
-randomization happens at initialization time and hence during a single
-simulation run, the same constant (but random) value will be used every
-time the assignment is executed.
+Assigning X to a variable will assign a constant value as determined by the
+:vlopt:`--x-assign` option.  This allows runtime randomization; thus, if
+the value is used, the random value should cause downstream errors.
+Integers also get randomized, even though the Verilog 2001 specification
+says they initialize to zero.  However, randomization happens at
+initialization time; hence, during a single simulation run, the same
+constant (but random) value will be used every time the assignment is
+executed.

 All variables, depending on :vlopt:`--x-initial` setting, are typically
-randomly initialized using a function.  By running several random
-simulation runs you can determine that reset is working correctly.  On the
-first run, have the function initialize variables to zero.  On the second,
-have it initialize variables to one.  On the third and following runs have
-it initialize them randomly.  If the results match, reset works.  (Note
-this is what the hardware will really do.)  In practice, just setting all
-variables to one at startup finds most problems (since typically control
-signals are active-high).
+randomly initialized using a function.  You can determine that reset is
+working correctly by running several random simulation runs.  On the first
+run, have the function initialize variables to zero.  On the second, have
+it initialize variables to one.  On the third and following runs, have it
+initialize them randomly.  If the results match, reset works.  (Note that
+this is what the hardware will do.)  In practice, setting all variables to
+one at startup finds the most problems (since control signals are typically
+active-high).

 :vlopt:`--x-assign` applies to variables explicitly initialized or assigned
 an X. Uninitialized clocks are initialized to zero, while all other state
-holding variables are initialized to a random value.  Event driven
+holding variables are initialized to a random value.  Event-driven
 simulators will generally trigger an edge on a transition from X to 1
 (posedge) or X to 0 (negedge). However, by default, since clocks are
 initialized to zero, Verilator will not trigger an initial negedge. Some
@@ -258,35 +316,24 @@ External logic will be needed to combine these signals with any external
 drivers.

 Tristate drivers are not supported inside functions and tasks; an inout
-there will be considered a two state variable that is read and written
-instead of a four state variable.
+there will be considered a two-state variable that is read and written
+instead of a four-state variable.


 Functions & Tasks
 -----------------

 All functions and tasks will be inlined (will not become functions in C.)
-The only support provided is for simple statements in tasks (which may
+The only support provided is simple statements in tasks (which may
 affect global variables).

 Recursive functions and tasks are not supported.  All inputs and outputs
-are automatic, as if they had the Verilog 2001 "automatic" keyword
+are automatic as if they had the Verilog 2001 "automatic" keyword
 prepended.  (If you don't know what this means, Verilator will do what you
 probably expect, what C does. The default behavior of Verilog is
 different.)


-Generated Clocks
----------------
-
-Verilator attempts to deal with generated and gated clocks correctly,
-however some cases cause problems in the scheduling algorithm which is
-optimized for performance.  The safest option is to have all clocks as
-primary inputs to the model, or wires directly attached to primary inputs.
-For proper behavior clock enables may also need the
-:option:`/*verilator&32;clock_enable*/` metacomment.
-
-
 Gate Primitives
 ---------------

@@ -313,14 +360,14 @@ error for more information.
 Array Out of Bounds
 -------------------

-Writing a memory element that is outside the bounds specified for the array
-may cause a different memory element inside the array to be written
-instead.  For power-of-2 sized arrays, Verilator will give a width warning
-and the address.  For non-power-of-2-sizes arrays, index 0 will be written.
+Writing a memory element outside the bounds specified for the array may
+cause a different memory element inside the array to be written instead.
+For power-of-2 sized arrays, Verilator will give a width warning and the
+address.  For non-power-of-2-sizes arrays, index 0 will be written.

-Reading a memory element that is outside the bounds specified for the array
-will give a width warning and wrap around the power-of-2 size.  For
-non-power-of-2 sizes, it will return a unspecified constant of the
+Reading a memory element outside the bounds specified for the array will
+give a width warning and wrap around the power-of-2 size.  For
+non-power-of-2 sizes, it will return an unspecified constant of the
 appropriate width.


@@ -336,10 +383,28 @@ Verilator does not support SEREs yet.  All assertion and coverage
 statements must be simple expressions that complete in one cycle.


+Force statement
+---------------
+
+Verilator supports the procedural `force` (and corresponding `release`)
+statement. However, the behavior of the `force` statement does not entirely
+comply with IEEE 1800. According to the standard,
+when a procedural statement of the form `force a = b;` is executed, the
+simulation should behave as if, from that point forwards, a continuous
+assignment `assign a = b;` has been added to override the drivers of `a`.
+More specifically: the value of `a` should be updated whenever the value of
+`b` changes, until a `release a;` statement is executed.
+Verilator instead evaluates the current value of `b` when the `force`
+statement is executed, and forces `a` to that value, without updating it
+until a new `force` or `release` statement is encountered that applies to
+`a`. This non-standard behavior is nevertheless consistent with some other
+simulators.
+
+
 Encrypted Verilog
 -----------------

-Open source simulators like Verilator are unable to use encrypted RTL
+Open-source simulators like Verilator cannot use encrypted RTL
 (i.e. IEEE P1735).  Talk to your IP vendor about delivering IP blocks via
 Verilator's :vlopt:`--protect-lib` feature.

@@ -380,12 +445,12 @@ This section describes specific limitations for each language keyword.
  certain limited cases.

 '{} operator
-  Assignment patterns with order based, default, constant integer (array)
+  Assignment patterns with an order based, default, constant integer (array)
  or member identifier (struct/union) keys are supported.  Data type keys
-  and keys which are computed from a constant expression are not supported.
+  and keys computed from a constant expression are not supported.

 \`uselib
-  Uselib, a vendor specific library specification method, is ignored along
+  Uselib, a vendor-specific library specification method, is ignored along
  with anything following it until the end of that line.

 cast operator
@@ -393,8 +458,8 @@ cast operator
  unsigned, not arrays nor structs.

 chandle
-  Treated as a "longint"; does not yet warn about operations that are
-  specified as illegal on chandles.
+  Treated as a "longint"; does not yet warn about operations specified as
+  illegal on chandles.

 disable
  Disable statements may be used only if the block being disabled is a
@@ -407,7 +472,7 @@ inside
  upper bound.  Case inside and case matches are also unsupported.

 interface
-  Interfaces and modports, including with generated data types are
+  Interfaces and modports, including generated data types are
  supported.  Generate blocks around modports are not supported, nor are
  virtual interfaces nor unnamed interfaces.

@@ -419,25 +484,25 @@ specify specparam
  All specify blocks and timing checks are ignored.

 uwire
-  Verilator does not perform warning checking on uwires, it treats the
+  Verilator does not perform warning checking on uwires; it treats the
  uwire keyword as if it were the normal wire keyword.

 $bits, $countbits, $countones, $finish, $isunknown, $onehot, $onehot0, $signed, $stime, $stop, $time, $unsigned,
  Generally supported.

 $dump/$dumpports and related
-  $dumpfile or $dumpports will create a VCD or FST file (which is based on
+  $dumpfile or $dumpports will create a VCD or FST file (based on
  the :vlopt:`--trace` option given when the model was Verilated). This
  will take effect starting at the next eval() call.  If you have multiple
-  Verilated designs under the same C model, then this will dump signals
+  Verilated designs under the same C model, this will dump signals
  only from the design containing the $dumpvars.

  $dumpvars and $dumpports module identifier is ignored; the traced
  instances will always start at the top of the design. The levels argument
-  is also ignored, use tracing_on/tracing_off pragmas instead.
+  is also ignored; use tracing_on/tracing_off pragmas instead.

  $dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename
-  argument is ignored, only a single trace file may be active at once.
+  argument is ignored; only a single trace file may be active at once.

  $dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and
  $dumplimit/$dumpportlimit are currently ignored.
@@ -446,7 +511,7 @@ $error, $fatal, $info, $warning.
  Generally supported.

 $exit, $finish, $stop
-  The rarely used optional parameter to $finish and $stop is ignored. $exit
+  The rarely used optional parameter to $finish and $stop is ignored; $exit
  is aliased to $finish.

 $fopen, $fclose, $fdisplay, $ferror, $feof, $fflush, $fgetc, $fgets, $fscanf, $fwrite, $fscanf, $sscanf
@@ -462,8 +527,8 @@ $random, $urandom, $urandom_range
  per object for random stability of $urandom/$urandom_range.

 $readmemb, $readmemh
-  Read memory commands are supported.  Note Verilator and the Verilog
-  specification does not include support for readmem to multi-dimensional
+  Read memory commands are supported.  Verilator and the Verilog
+  specification do not include support for readmem to multi-dimensional
  arrays.

 $test$plusargs, $value$plusargs
@@ -471,7 +536,7 @@ $test$plusargs, $value$plusargs

  .. code-block:: C++

-        Verilated::commandArgs(argc, argv);
+        {VerilatedContext*} ->commandArgs(argc, argv);

  to register the command line before calling $test$plusargs or
  $value$plusargs.
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 ********
@@ -8,30 +8,30 @@ Overview
 Welcome to Verilator!

 The Verilator package converts Verilog [#]_ and SystemVerilog [#]_ hardware
-description language (HDL) designs into a C++ or SystemC model that after
-compiling can be executed.  Verilator is not a traditional simulator, but a
+description language (HDL) designs into a C++ or SystemC model that, after
+compiling, can be executed.  Verilator is not a traditional simulator but a
 compiler.

 Verilator is typically used as follows:

 1. The :command:`verilator` executable is invoked with parameters similar
-to GCC, or other simulators such as Cadence Verilog-XL/NC-Verilog, or
+to GCC or other simulators such as Cadence Verilog-XL/NC-Verilog, or
 Synopsys VCS.  Verilator reads the specified SystemVerilog code, lints it,
 optionally adds coverage and waveform tracing support, and compiles the
-design into a source level multithreaded C++ or SystemC "model".  The
+design into a source-level multithreaded C++ or SystemC "model".  The
 resulting model's C++ or SystemC code is output as .cpp and .h files. This
-is referred to as "Verilating" and the process is "to Verilate"; the output
-is a "Verilated" model.
+is referred to as "Verilating", and the process is "to Verilate"; the
+output is a "Verilated" model.

-2. For simulation, a small user written C++ wrapper file is required, the
-"wrapper".  This wrapper defines the C++ standard function "main()" which
+2. For simulation, a small-user written C++ wrapper file is required, the
+"wrapper".  This wrapper defines the C++ standard function "main()", which
 instantiates the Verilated model as a C++/SystemC object.

 3. The user C++ wrapper, the files created by Verilator, a "runtime
-library" provided by Verilator, and if applicable SystemC libraries are
+library" provided by Verilator, and, if applicable SystemC libraries are
 then compiled using a C++ compiler to create a simulation executable.

-4. The resulting executable will perform the actual simulation, during
+4. The resulting executable will perform the actual simulation during
 "simulation runtime".

 5. If appropriately enabled, the executable may also generate waveform
@@ -44,12 +44,12 @@ The best place to get started is to try the :ref:`Examples`.
 .. [#] Verilog is defined by the `Institute of Electrical and Electronics
       Engineers (IEEE) Standard for Verilog Hardware Description
       Language`, Std. 1364, released in 1995, 2001, and 2005.  The
-       Verilator documentation uses the shorthand e.g. "IEEE 1394-2005" to
-       refer to the e.g. 2005 version of this standard.
+       Verilator documentation uses the shorthand, e.g., "IEEE 1394-2005",
+       to refer to the, e.g., 2005 version of this standard.

 .. [#] SystemVerilog is defined by the `Institute of Electrical and
       Electronics Engineers (IEEE) Standard for SystemVerilog - Unified
       Hardware Design, Specification, and Verification Language`, Standard
       1800, released in 2005, 2009, 2012, and 2017.  The Verilator
-       documentation uses the shorthand e.g. "IEEE 1800-2017" to refer to
-       the e.g. 2017 version of this standard.
+       documentation uses the shorthand e.g., "IEEE 1800-2017", to refer to
+       the, e.g., 2017 version of this standard.
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 .. _Simulating:
@@ -7,9 +7,9 @@
 Simulating (Verilated-Model Runtime)
 ************************************

-This section describes items related to simulating, that using a Verilated
-model's executable.  For the runtime arguments to a simulated model, see
-:ref:`Simulation Runtime Arguments`.
+This section describes items related to simulating, that is, using a
+Verilated model's executable.  For the runtime arguments to a simulated
+model, see :ref:`Simulation Runtime Arguments`.


 .. _Benchmarking & Optimization:
@@ -18,30 +18,32 @@ Benchmarking & Optimization
 ===========================

 For best performance, run Verilator with the :vlopt:`-O3`
-:vlopt:`--x-assign fast <--x-assign>` :vlopt:`--x-initial fast
-<--x-initial>` :vlopt:`--noassert <--assert>` options.  The :vlopt:`-O3`
-option will require longer time to run Verilator, and :vlopt:`--x-assign
-fast <--x-assign>` :vlopt:`--x-initial fast <--x-assign>` may increase the
-risk of reset bugs in trade for performance; see the above documentation
-for these options.
+:vlopt:`--x-assign fast <--x-assign>`
+:vlopt:`--x-initial fast <--x-initial>`
+:vlopt:`--noassert <--assert>` options.  The :vlopt:`-O3`
+option will require a longer time to run Verilator, and
+:vlopt:`--x-assign fast <--x-assign>`
+:vlopt:`--x-initial fast <--x-assign>`
+may increase the risk of reset bugs in trade for performance; see the above
+documentation for these options.

-If using Verilated multithreaded, use ``numactl`` to ensure you are using
-non-conflicting hardware resources. See :ref:`Multithreading`. Also
-consider using profile-guided optimization, see :ref:`Thread PGO`.
+If using Verilated multithreaded, use ``numactl`` to ensure you use
+non-conflicting hardware resources. See :ref:`Multithreading`. Also,
+consider using profile-guided optimization; see :ref:`Thread PGO`.

 Minor Verilog code changes can also give big wins.  You should not have any
-UNOPTFLAT warnings from Verilator.  Fixing these warnings can result in
-huge improvements; one user fixed their one UNOPTFLAT warning by making a
-simple change to a clock latch used to gate clocks and gained a 60%
-performance improvement.
+:option:`UNOPTFLAT` warnings from Verilator.  Fixing these warnings can
+result in huge improvements; one user fixed their one UNOPTFLAT warning by
+making a simple change to a clocked latch used to gate clocks and gained a
+60% performance improvement.

-Beyond that, the performance of a Verilated model depends mostly on your
-C++ compiler and size of your CPU's caches. Experience shows that large
-models are often limited by the size of the instruction cache, and as such
-reducing code size if possible can be beneficial.
+Beyond that, the performance of a Verilated model depends primarily on your
+C++ compiler and the size of your CPU's caches. Experience shows that the
+instruction cache size often limits large models, and reducing code size,
+if possible, can be beneficial.

 The supplied $VERILATOR_ROOT/include/verilated.mk file uses the OPT,
-OPT_FAST, OPT_SLOW and OPT_GLOBAL variables to control optimization. You
+OPT_FAST, OPT_SLOW, and OPT_GLOBAL variables to control optimization. You
 can set these when compiling the output of Verilator with Make, for
 example:

@@ -49,17 +51,17 @@ example:

     make OPT_FAST="-Os -march=native" -f Vour.mk Vour__ALL.a

-OPT_FAST specifies optimization options for those parts of the model that
-are on the fast path. This is mostly code that is executed every
-cycle. OPT_SLOW applies to slow-path code, which executes rarely, often
-only once at the beginning or end of simulation. Note that OPT_SLOW is
+OPT_FAST specifies optimization options for those parts of the model
+on the fast path. This is mostly code that is executed every
+cycle. OPT_SLOW applies to slow-path code, which rarely executes, often
+only once at the beginning or end of the simulation. OPT_SLOW is
 ignored if VM_PARALLEL_BUILDS is not 1, in which case all generated code
 will be compiled in a single compilation unit using OPT_FAST. See also the
 Verilator :vlopt:`--output-split` option. The OPT_GLOBAL variable applies
 to common code in the runtime library used by Verilated models (shipped in
 $VERILATOR_ROOT/include). Additional C++ files passed on the verilator
 command line use OPT_FAST. The OPT variable applies to all compilation
-units in addition to the specific "OPT" variables described above.
+units and the specific "OPT" variables described above.

 You can also use the :vlopt:`-CFLAGS` and/or :vlopt:`-LDFLAGS` options on
 the verilator command line to pass arguments directly to the compiler or
@@ -68,53 +70,53 @@ linker.
 The default values of the "OPT" variables are chosen to yield good
 simulation speed with reasonable C++ compilation times. To this end,
 OPT_FAST is set to "-Os" by default. Higher optimization such as "-O2" or
-"-O3" may help (though often they provide only a very small performance
-benefit), but compile times may be excessively large even with medium sized
+"-O3" may help (though often they provide only a minimal performance
+benefit), but compile times may be excessively large even with medium-sized
 designs. Compilation times can be improved at the expense of simulation
-speed by reducing optimization, for example with OPT_FAST="-O0". Often good
-simulation speed can be achieved with OPT_FAST="-O1 -fstrict-aliasing" but
-with improved compilation times. Files controlled by OPT_SLOW have little
-effect on performance and therefore OPT_SLOW is empty by default
-(equivalent to "-O0") for improved compilation speed. In common use-cases
+speed by reducing optimization, for example, with OPT_FAST="-O0". Often
+good simulation speed can be achieved with OPT_FAST="-O1 -fstrict-aliasing"
+but with improved compilation times.  Files controlled by OPT_SLOW have
+little effect on performance, and therefore OPT_SLOW is empty by default
+(equivalent to "-O0") for improved compilation speed. In common use cases,
 there should be little benefit in changing OPT_SLOW.  OPT_GLOBAL is set to
-"-Os" by default and there should rarely be a need to change it. As the
-runtime library is small in comparison to a lot of Verilated models,
-disabling optimization on the runtime library should not have a serious
-effect on overall compilation time, but may have detrimental effect on
-simulation speed, especially with tracing. In addition to the above, for
-best results use OPT="-march=native", the latest Clang compiler (about 10%
-faster than GCC), and link statically.
+"-Os" by default, and there should rarely be a need to change it. As the
+runtime library is small compared to many Verilated models, disabling
+optimization on the runtime library should not seriously affect overall
+compilation time but may have a detrimental effect on simulation speed,
+especially with tracing. In addition to the above, for best results, use
+OPT="-march=native", the latest Clang compiler (about 10% faster than GCC),
+and link statically.

-Generally the answer to which optimization level gives the best user
-experience depends on the use case and some experimentation can pay
+Generally, the answer to which optimization level gives the best user
+experience depends on the use case, and some experimentation can pay
 dividends. For a speedy debug cycle during development, especially on large
 designs where C++ compilation speed can dominate, consider using lower
-optimization to get to an executable faster. For throughput oriented use
-cases, for example regressions, it is usually worth spending extra
+optimization to get to an executable faster. For throughput-oriented use
+cases, for example, regressions, it is usually worth spending extra
 compilation time to reduce total CPU time.

 If you will be running many simulations on a single model, you can
-investigate profile guided optimization. See :ref:`Compiler PGO`.
+investigate profile-guided optimization. See :ref:`Compiler PGO`.

-Modern compilers also support link-time optimization (LTO), which can help
+Modern compilers also support link-time optimization (LTO), which can help,
 especially if you link in DPI code. To enable LTO on GCC, pass "-flto" in
-both compilation and link. Note LTO may cause excessive compile times on
-large designs.
+both compilation and link. Note that LTO may cause excessive compile times
+on large designs.

 Unfortunately, using the optimizer with SystemC files can result in
 compilation taking several minutes. (The SystemC libraries have many little
 inlined functions that drive the compiler nuts.)

-If you are using your own makefiles, you may want to compile the Verilated
+If using your own makefiles, you may want to compile the Verilated
 code with ``--MAKEFLAGS -DVL_INLINE_OPT=inline``. This will inline
-functions, however this requires that all cpp files be compiled in a single
+functions; however, this requires that all cpp files be compiled in a single
 compiler run.

 You may uncover further tuning possibilities by profiling the Verilog code.
 See :ref:`profiling`.

 When done optimizing, please let the author know the results.  We like to
-keep tabs on how Verilator compares, and may be able to suggest additional
+keep tabs on how Verilator compares and may be able to suggest additional
 improvements.


@@ -141,14 +143,14 @@ Functional Coverage
 -------------------

 With :vlopt:`--coverage` or :vlopt:`--coverage-user`, Verilator will
-translate functional coverage points which the user has inserted manually
-into the SystemVerilog design, into the Verilated model.
+translate functional coverage points the user has inserted manually win
+SystemVerilog code through into the Verilated model.

 Currently, all functional coverage points are specified using SystemVerilog
-assertion syntax which must be separately enabled with :vlopt:`--assert`.
+assertion syntax, which must be separately enabled with :vlopt:`--assert`.

 For example, the following SystemVerilog statement will add a coverage
-point, under the coverage name "DefaultClock":
+point under the coverage name "DefaultClock":

 .. code-block:: sv

@@ -161,13 +163,13 @@ Line Coverage
 -------------

 With :vlopt:`--coverage` or :vlopt:`--coverage-line`, Verilator will
-automatically add coverage analysis at each code flow change point (e.g. at
-branches).  At each such branch a unique counter is incremented.  At the
-end of a test, the counters along with the filename and line number
-corresponding to each counter are written into the coverage file.
+automatically add coverage analysis at each code flow change point (e.g.,
+at branches).  At each such branch, a counter is incremented.  At the end
+of a test, the counters, filename, and line number corresponding to each
+counter are written into the coverage file.

-Verilator automatically disables coverage of branches that have a $stop in
-them, as it is assumed $stop branches contain an error check that should
+Verilator automatically disables coverage of branches with a $stop in
+them, as it is assumed that $stop branches contain an error check that should
 not occur.  A :option:`/*verilator&32;coverage_block_off*/` metacomment
 will perform a similar function on any code in that block or below, or
 :option:`/*verilator&32;coverage_off*/` and
@@ -175,8 +177,9 @@ will perform a similar function on any code in that block or below, or
 respectively around a block of code.

 Verilator may over-count combinatorial (non-clocked) blocks when those
-blocks receive signals which have had the UNOPTFLAT warning disabled; for
-most accurate results do not disable this warning when using coverage.
+blocks receive signals which have had the :option:`UNOPTFLAT` warning
+disabled; for the most accurate results, do not disable this warning when
+using coverage.


 .. _Toggle Coverage:
@@ -187,8 +190,8 @@ Toggle Coverage
 With :vlopt:`--coverage` or :vlopt:`--coverage-toggle`, Verilator will
 automatically add toggle coverage analysis  into the Verilated model.

-Every bit of every signal in a module has a counter inserted.  The counter
-will increment on every edge change of the corresponding bit.
+Every bit of every signal in a module has a counter inserted, and the
+counter will increment on every edge change of the corresponding bit.

 Signals that are part of tasks or begin/end blocks are considered local
 variables and are not covered.  Signals that begin with underscores (see
@@ -196,17 +199,17 @@ variables and are not covered.  Signals that begin with underscores (see
 total storage across all dimensions, see :vlopt:`--coverage-max-width`) are
 also not covered.

-Hierarchy is compressed, such that if a module is instantiated multiple
-times, coverage will be summed for that bit across **all** instantiations
-of that module with the same parameter set.  A module instantiated with
-different parameter values is considered a different module, and will get
-counted separately.
+Hierarchy is compressed, so if a module is instantiated multiple times,
+coverage will be summed for that bit across **all** instantiations of that
+module with the same parameter set.  A module instantiated with different
+parameter values is considered a different module and will get counted
+separately.

 Verilator makes a minimally-intelligent decision about what clock domain
 the signal goes to, and only looks for edges in that clock domain.  This
-means that edges may be ignored if it is known that the edge could never be
-seen by the receiving logic.  This algorithm may improve in the future.
-The net result is coverage may be lower than what would be seen by looking
+means that edges may be ignored if it is known that the receiving logic
+could never see the edge.  This algorithm may improve in the future. The
+net result is that coverage may be lower than what would be seen by looking
 at traces, but the coverage is a more accurate representation of the
 quality of stimulus into the design.

@@ -224,7 +227,7 @@ signals that do not need toggle analysis, such as RAMs and register files.
 Coverage Collection
 -------------------

-When any coverage flag was used to Verilate, Verilator will add appropriate
+When any coverage flag is used to Verilate, Verilator will add appropriate
 coverage point insertions into the model and collect the coverage data.

 To get the coverage data from the model, in the user wrapper code,
@@ -237,23 +240,23 @@ Run each of your tests in different directories, potentially in parallel.
 Each test will create a :file:`logs/coverage.dat` file.

 After running all of the tests, execute the :command:`verilator_coverage`
-command, passing arguments pointing to the filenames of all of the
-individual coverage files.  :command:`verilator_coverage` will reads the
+command, passing arguments pointing to the filenames of all the
+individual coverage files.  :command:`verilator_coverage` will read the
 :file:`logs/coverage.dat` file(s), and create an annotated source code
 listing showing code coverage details.

-:command:`verilator_coverage` may also be used for test grading, that is
-computing which tests are important to fully cover the design.
+:command:`verilator_coverage` may also be used for test grading, computing
+which tests are important to give full verification coverage on the design.

 For an example, see the :file:`examples/make_tracing_c/logs` directory.
 Grep for lines starting with '%' to see what lines Verilator believes need
 more coverage.

-Additional options of :command:`verilator_coverage` allow for merging of
-coverage data files or other transformations.
+Additional options of :command:`verilator_coverage` allow for the merging
+of coverage data files or other transformations.

 Info files can be written by verilator_coverage for import to
-:command:`lcov`.  This enables use of :command:`genhtml` for HTML reports
+:command:`lcov`.  This enables using :command:`genhtml` for HTML reports
 and importing reports to sites such as `https://codecov.io
 <https://codecov.io>`_.

@@ -274,35 +277,33 @@ To use profiling:
 #. Build and run the simulation model.
 #. The model will create gmon.out.
 #. Run :command:`gprof` to see where in the C++ code the time is spent.
-#. Run the gprof output through the :command:`verilator_profcfunc` program
+#. Run the gprof output through the :command:`verilator_profcfunc` program,
   and it will tell you what Verilog line numbers on which most of the time
   is being spent.


-.. _Thread Profiling:
+.. _Execution Profiling:

-Thread Profiling
-================
+Execution Profiling
+===================

-When using multithreaded mode (:vlopt:`--threads`), it is useful to see
-statistics and visualize how well the multiple CPUs are being utilized.
+For performance optimization, it is helpful to see statistics and visualize how
+execution time is distributed in a verilated model.

-With the :vlopt:`--prof-threads` option, Verilator will:
+With the :vlopt:`--prof-exec` option, Verilator will:

-* Add code to the Verilated model to record the start and end time of each
-  macro-task across a number of calls to eval. (What is a macro-task?  See
-  the Verilator internals document (:file:`docs/internals.rst` in the
-  distribution.)
+* Add code to the Verilated model to record execution flow.

 * Add code to save profiling data in non-human-friendly form to the file
-  specified with :vlopt:`+verilator+prof+threads+file+\<filename\>`.
+  specified with :vlopt:`+verilator+prof+exec+file+\<filename\>`.

-* Add code to save profiling data for thread profile-guided
-  optimization. See :ref:`Thread PGO`.
+* In multithreaded models, add code to record each macro-task's start and
+  end time across several calls to eval. (What is a macro-task?  See the
+  Verilator internals document (:file:`docs/internals.rst` in the
+  distribution.)

 The :command:`verilator_gantt` program may then be run to transform the
-saved profiling file into a nicer visual format and produce some related
-statistics.
+saved profiling file into a visual format and produce related statistics.

 .. figure:: figures/fig_gantt_min.png

@@ -310,11 +311,11 @@ statistics.

   The measured_parallelism shows the number of CPUs being used at a given moment.

-   The cpu_thread section shows which thread is executing on each of the physical CPUs.
+   The cpu_thread section shows which thread is executing on each physical CPU.

   The thread_mtask section shows which macro-task is running on a given thread.

-For more information see :command:`verilator_gantt`.
+For more information, see :command:`verilator_gantt`.


 .. _Profiling ccache efficiency:
@@ -322,12 +323,11 @@ For more information see :command:`verilator_gantt`.
 Profiling ccache efficiency
 ===========================

-The Verilator generated Makefile provides support for basic profiling of
-ccache behavior during the build. This can be used to track down files that
-might be unnecessarily rebuilt, though as of today even small code changes
-will usually require rebuilding a large number of files. Improving ccache
-efficiency during the edit/compile/test loop is an active area of
-development.
+The Verilator-generated Makefile supports basic profiling of ccache
+behavior during the build. This can be used to track down files that might
+be unnecessarily rebuilt, though as of today, even minor code changes will
+usually require rebuilding a large number of files. Improving ccache
+efficiency during the edit/compile/test loop is an active development area.

 To get a basic report of how well ccache is doing, add the `ccache-report`
 target when invoking the generated Makefile:
@@ -351,17 +351,17 @@ releases.
 Save/Restore
 ============

-The intermediate state of a Verilated model may be saved, so that it may
+The intermediate state of a Verilated model may be saved so that it may
 later be restored.

 To enable this feature, use :vlopt:`--savable`.  There are limitations in
 what language features are supported along with :vlopt:`--savable`; if you
-attempt to use an unsupported feature Verilator will throw an error.
+attempt to use an unsupported feature, Verilator will throw an error.

 To use save/restore, the user wrapper code must create a VerilatedSerialize
-or VerilatedDeserialze object then calling the :code:`<<` or :code:`>>`
-operators on the generated model and any other data the process needs
-saved/restored.  These functions are not thread safe, and are typically
+or VerilatedDeserialze object and then call the :code:`<<` or :code:`>>`
+operators on the generated model and any other data the process needs to be
+saved/restored.  These functions are not thread-safe and are typically
 called only by a main thread.

 For example:
@@ -371,7 +371,7 @@ For example:
     void save_model(const char* filenamep) {
         VerilatedSave os;
         os.open(filenamep);
-         os << main_time;  // user code must save the timestamp, etc
+         os << main_time;  // user code must save the timestamp
         os << *topp;
     }
     void restore_model(const char* filenamep) {
@@ -386,11 +386,11 @@ Profile-Guided Optimization
 ===========================

 Profile-guided optimization is the technique where profiling data is
-collected by running your simulation executable, then this information is
+collected by running your simulation executable; then this information is
 used to guide the next Verilation or compilation.

-There are two forms of profile-guided optimizations.  Unfortunately for
-best results they must each be performed from the highest level code to the
+There are two forms of profile-guided optimizations.  Unfortunately, for
+best results, they must each be performed from the highest level code to the
 lowest, which means performing them separately and in this order:

 * :ref:`Thread PGO`
@@ -398,7 +398,7 @@ lowest, which means performing them separately and in this order:

 Other forms of PGO may be supported in the future, such as clock and reset
 toggle rate PGO, branch prediction PGO, statement execution time PGO, or
-others as they prove beneficial.
+others, as they prove beneficial.


 .. _Thread PGO:
@@ -406,8 +406,8 @@ others as they prove beneficial.
 Thread Profile-Guided Optimization
 ----------------------------------

-Verilator supports thread profile-guided optimization (Thread PGO) to
-improve multithreaded performance.
+Verilator supports profile-guided optimization (Verilation) of multithreaded
+models (Thread PGO) to improve performance.

 When using multithreading, Verilator computes how long macro tasks take and
 tries to balance those across threads.  (What is a macro-task?  See the
@@ -417,30 +417,31 @@ balanced, leading to decreased performance.  Thread PGO allows collecting
 profiling data to replace the estimates and better optimize these
 decisions.

-To use Thread PGO, Verilate the model with the :vlopt:`--prof-threads`
-option.
+To use Thread PGO, Verilate the model with the :vlopt:`--prof-pgo` option. This
+will code to the verilated model to save profiling data for profile-guided
+optimization.

 Run the model executable. When the executable exits, it will create a
 profile.vlt file.

-Rerun Verilator, optionally omitting the :vlopt:`--prof-threads` option,
-and adding the profile.vlt generated earlier to the command line.
+Rerun Verilator, optionally omitting the :vlopt:`--prof-pgo` option and
+adding the :file:`profile.vlt` generated earlier to the command line.

-Note there is no Verilator equivalent to GCC's --fprofile-use. Verilator's
-profile data file (profile.vlt) can be placed on the verilator command line
-directly without any prefix.
+Note there is no Verilator equivalent to GCC's --fprofile-use.  Verilator's
+profile data file (:file:`profile.vlt`) can be placed directly on the
+verilator command line without any option prefix.

 If results from multiple simulations are to be used in generating the
 optimization, multiple simulation's profile.vlt may be concatenated
-externally, or each of the files may be fed as separate command line
-options into Verilator.  Verilator will simply sum the profile results, so
-a longer running test will have proportionally more weight for optimization
-than a shorter running test.
+externally, or each file may be fed as separate command line options into
+Verilator.  Verilator will sum the profile results, so a long-running test
+will have more weight for optimization proportionally than a
+shorter-running test.

-If you provide any profile feedback data to Verilator, and it cannot use
+If you provide any profile feedback data to Verilator and it cannot use
 it, it will issue the :option:`PROFOUTOFDATE` warning that threads were
 scheduled using estimated costs.  This usually indicates that the profile
-data was generated from different Verilog source code than Verilator is
+data was generated from a different Verilog source code than Verilator is
 currently running against. Therefore, repeat the data collection phase to
 create new profiling data, then rerun Verilator with the same input source
 files and that new profiling data.
@@ -452,12 +453,12 @@ Compiler Profile-Guided Optimization
 ------------------------------------

 GCC and Clang support compiler profile-guided optimization (PGO). This
-optimizes any C/C++ program including Verilated code.  Using compiler PGO
+optimizes any C/C++ program, including Verilated code.  Using compiler PGO
 typically yields improvements of 5-15% on both single-threaded and
-multi-threaded models.
+multithreaded models.

-To use compiler PGO with GCC or Clang, please see the appropriate compiler
-documentation.  The process in GCC 10 was as follows:
+Please see the appropriate compiler documentation to use PGO with GCC or
+Clang.  The process in GCC 10 was as follows:

 1. Compile the Verilated model with the compiler's "-fprofile-generate"
   flag:
@@ -467,7 +468,7 @@ documentation.  The process in GCC 10 was as follows:
      verilator [whatever_flags] --make \
          -CFLAGS -fprofile-generate -LDFLAGS -fprofile-generate

-   or, if calling make yourself, add -fprofile-generate appropriately to your
+   Or, if calling make yourself, add -fprofile-generate appropriately to your
   Makefile.

 2. Run your simulation. This will create \*.gcda file(s) in the same
@@ -494,6 +495,6 @@ documentation.  The process in GCC 10 was as follows:
   or, if calling make yourself, add these CFLAGS switches appropriately to
   your Makefile.

-Clang and GCC also support -fauto-profile which uses sample-based
+Clang and GCC also support -fauto-profile, which uses sample-based
 feedback-directed optimization.  See the appropriate compiler
 documentation.
@@ -1,4 +1,4 @@
-.. Copyright 2003-2021 by Wilson Snyder.
+.. Copyright 2003-2023 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

 **********
@@ -8,7 +8,7 @@ Verilating
 Verilator may be used in five major ways:

 * With the :vlopt:`--cc` or :vlopt:`--sc` options, Verilator will translate
-  the design into C++ or SystemC code respectively.  See :ref:`C++ and
+  the design into C++ or SystemC code, respectively.  See :ref:`C++ and
  SystemC Generation`.

 * With the :vlopt:`--lint-only` option, Verilator will lint the design to
@@ -19,8 +19,8 @@ Verilator may be used in five major ways:
  :file:`docs/xml.rst` in the distribution.

 * With the :vlopt:`-E` option, Verilator will preprocess the code according
-  to IEEE preprocessing rules, and write the output to standard out. This
-  is useful to feed other tools, and to debug how "\`define" statements are
+  to IEEE preprocessing rules and write the output to standard out. This
+  is useful to feed other tools and to debug how "\`define" statements are
  expanded.


@@ -34,10 +34,10 @@ Verilator will translate a SystemVerilog design into C++ with the

 When using these options:

-#. Verilator reads the input Verilog code, determines all "top modules" that
-   is modules or programs that are not used as instances under other cells.
-   If :vlopt:`--top-module` is used, then that determines the top module and
-   all other top modules are removed, otherwise a :vlopt:`MULTITOP` warning
+#. Verilator reads the input Verilog code and determines all "top modules", that
+   is, modules or programs that are not used as instances under other cells.
+   If :vlopt:`--top-module` is used, then that determines the top module, and
+   all other top modules are removed; otherwise a :vlopt:`MULTITOP` warning
   is given.

 #. Verilator writes the C++/SystemC code to output files into the
@@ -46,13 +46,13 @@ When using these options:
   top module.

 #. If :vlopt:`--exe` is used, Verilator creates makefiles to generate a
-   simulation executable, otherwise it creates makefiles to generate an
+   simulation executable, otherwise, it creates makefiles to generate an
   archive (.a) containing the objects.

 #. If :vlopt:`--build` option was used, it calls :ref:`GNU Make` or
   :ref:`CMake` to build the model.

-Once a model is built it is then typically run, see :ref:`Simulating`.
+Once a model is built, it is then typically run, see :ref:`Simulating`.


 .. _Hierarchical Verilation:
@@ -60,35 +60,34 @@ Once a model is built it is then typically run, see :ref:`Simulating`.
 Hierarchical Verilation
 =======================

-Large designs may take long (e.g. 10+ minutes) and huge memory (e.g. 100+
+Large designs may take long (e.g., 10+ minutes) and huge memory (e.g., 100+
 GB) to Verilate.  In hierarchical mode, the user manually selects some
 large lower-level hierarchy blocks to separate from the larger design. For
-example a core may be the hierarchy block, and separated out of a
-multi-core SoC.
+example, a core may be the hierarchy block separated out of a multi-core
+SoC design.

 Verilator is run in hierarchical mode on the whole SoC.  Verilator will
-make two models, one for the CPU hierarchy block, and one for the SoC.  The
-Verialted code for the SoC will automatically call the CPU Verilated model.
+make two models, one for the CPU hierarchy block and one for the SoC.  The
+Verilated code for the SoC will automatically call the CPU Verilated model.

-The current hierarchical Verilation is based on protect-lib. Each hierarchy
-block is Verilated to a protect-lib. User modules of the hierarchy blocks
-will see a tiny wrapper generated by protect-lib instead of the actual
-design.
+The current hierarchical Verilation is based on :vlopt:`--lib-create`. Each
+hierarchy block is Verilated into a library. User modules of the hierarchy
+blocks will see a tiny wrapper generated by :vlopt:`--lib-create`.


 Usage
 -----

-Users need to mark one or more moderate size module as hierarchy block(s).
+Users need to mark one or more moderate-size modules as hierarchy block(s).
 There are two ways to mark a module:

 * Write :option:`/*verilator&32;hier_block*/` metacomment in HDL code.

-* Add a :option:`hier_block` line in a the :ref:`Configuration Files`.
+* Add a :option:`hier_block` line in the :ref:`Configuration Files`.

-Then pass the :vlopt:`--hierarchical` option to Verilator
+Then pass the :vlopt:`--hierarchical` option to Verilator.

-Compilation is the same as when not using hierarchical mode.
+The compilation is the same as when not using hierarchical mode.

 .. code-block:: bash

@@ -98,21 +97,22 @@ Compilation is the same as when not using hierarchical mode.
 Limitations
 -----------

-Hierarchy blocks have some limitations including:
+Hierarchy blocks have some limitations, including:

-* The hierarchy block cannot be accessed using dot (.) from upper module(s)
-  or other hierarchy blocks.
+* The hierarchy block cannot be accessed using dot (.) from the upper
+  module(s) or other hierarchy blocks.

 * Signals in the block cannot be traced.

 * Modport cannot be used at the hierarchical block boundary.

-* The simulation speed is likely to not be as fast as flat Verilation, in
-  which all modules are globally scheduled.
+* The simulation speed is likely not as fast as flat Verilation, in which
+  all modules are globally scheduled.

-* Generated clocks may not work correctly if they are generated in the
-  hierarchical model and pass up into another hierarchical model or the top
-  module.
+* Generated clocks may not work correctly if generated in the hierarchical
+  model and passed into another hierarchical model or the top module.
+
+* Delays are not allowed in hierarchy blocks.

 But, the following usage is supported:

@@ -129,8 +129,8 @@ Overlapping Verilation and Compilation
 --------------------------------------

 Verilator needs to run 2 + *N* times in hierarchical Verilation, where *N*
-is the number of hierarchy blocks. One of the two is for the top module
-which refers wrappers of all other hierarchy blocks.  The second one of the
+is the number of hierarchy blocks. One of the two is for the top module,
+which refers to the wrappers of all other hierarchy blocks.  The second of the
 two is the initial run that searches modules marked with
 :option:`/*verilator&32;hier_block*/` metacomment and creates a plan and
 write in :file:`{prefix}_hier.mk`.  This initial run internally invokes
@@ -152,19 +152,19 @@ Verilator supports cross-compiling Verilated code.  This is generally used
 to run Verilator on a Linux system and produce C++ code that is then compiled
 on Windows.

-Cross compilation involves up to three different OSes.  The build system is
-where you configured and compiled Verilator, the host system where you run
-Verilator, and the target system where you compile the Verilated code and
-run the simulation.
+Cross-compilation involves up to three different OSes.  The build system is
+where you configure and compile Verilator, the host system is where you run
+Verilator, and the target system is where you compile the Verilated code
+and run the simulation.

-Currently, Verilator requires the build and host system type to be the
+Verilator requires the build and host system types to be the
 same, though the target system type may be different.  To support this,
 :command:`./configure` and make Verilator on the build system.  Then, run
 Verilator on the host system.  Finally, the output of Verilator may be
 compiled on the different target system.

 To support this, none of the files that Verilator produces will reference
-any configure generated build-system specific files, such as
+any configure-generated build-system-specific files, such as
 :file:`config.h` (which is renamed in Verilator to :file:`config_build.h`
 to reduce confusion.)  The disadvantage of this approach is that
 :file:`include/verilatedos.h` must self-detect the requirements of the
@@ -182,109 +182,101 @@ Multithreading

 Verilator supports multithreaded simulation models.

-With :vlopt:`--no-threads`, the default, the model is not thread safe, and
-any use of more than one thread calling into one or even different
-Verilated models may result in unpredictable behavior. This gives the
-highest single thread performance.
-
-With :vlopt:`--threads 1 <--threads>`, the generated model is single
-threaded, however the support libraries are multithread safe. This allows
-different instantiations of model(s) to potentially each be run under a
-different thread. All threading is the responsibility of the user's C++
-testbench.
+With :vlopt:`--threads 1 <--threads>`, the generated model is
+single-threaded; however, the support libraries are multithread safe. This
+allows different instantiations of the model(s) to potentially each be run
+under a different thread. All threading is the responsibility of the user's
+C++ testbench.

 With :vlopt:`--threads {N} <--threads>`, where N is at least 2, the
 generated model will be designed to run in parallel on N threads. The
 thread calling eval() provides one of those threads, and the generated
 model will create and manage the other N-1 threads. It's the client's
 responsibility not to oversubscribe the available CPU cores. Under CPU
-oversubscription, the Verilated model should not livelock nor deadlock,
+oversubscription, the Verilated model should not livelock nor deadlock;
 however, you can expect performance to be far worse than it would be with
-proper ratio of threads and CPU cores.
-
-The remainder of this section describe behavior with :vlopt:`--threads 1
-<--threads>` or :vlopt:`--threads {N} <--threads>` (not
-:vlopt:`--no-threads`).
-
-:code:`VL_THREADED` is defined in the C++ code when compiling a threaded
-Verilated module, causing the Verilated support classes become threadsafe.
+the proper ratio of threads and CPU cores.

 The thread used for constructing a model must be the same thread that calls
-:code:`eval()` into the model, this is called the "eval thread". The thread
-used to perform certain global operations such as saving and tracing must
-be done by a "main thread". In most cases the eval thread and main thread
+:code:`eval()` into the model; this is called the "eval thread". The thread
+used to perform certain global operations, such as saving and tracing, must
+be done by a "main thread". In most cases, the eval thread and main thread
 are the same thread (i.e. the user's top C++ testbench runs on a single
 thread), but this is not required.

-When making frequent use of DPI imported functions in a multi-threaded
+When making frequent use of DPI imported functions in a multithreaded
 model, it may be beneficial to performance to adjust the
 :vlopt:`--instr-count-dpi` option based on some experimentation. This
 influences the partitioning of the model by adjusting the assumed execution
 time of DPI imports.

-The :vlopt:`--trace-threads` options can be used to produce trace dumps
-using multiple threads. If :vlopt:`--trace-threads` is set without
-:vlopt:`--threads`, then :vlopt:`--trace-threads` will imply
-:vlopt:`--threads 1 <--threads>`, i.e.: the support libraries will be
+When using :vlopt:`--trace` to perform VCD tracing, the VCD trace
+construction is parallelized using the same number of threads as specified
+with :vlopt:`--threads`, and is executed on the same thread pool as the model.
+
+The :vlopt:`--trace-threads` options can be used with :vlopt:`--trace-fst`
+to offload FST tracing using multiple threads. If :vlopt:`--trace-threads` is
+given without :vlopt:`--threads`, then :vlopt:`--trace-threads` will imply
+:vlopt:`--threads 1 <--threads>`, i.e., the support libraries will be
 thread safe.

 With :vlopt:`--trace-threads 0 <--trace-threads>`, trace dumps are produced
-on the main thread. This again gives the highest single thread performance.
+on the main thread. This again gives the highest single-thread performance.

 With :vlopt:`--trace-threads {N} <--trace-threads>`, where N is at least 1,
-N additional threads will be created and managed by the trace files (e.g.:
-VerilatedVcdC or VerilatedFstC), to generate the trace dump. The main
-thread will be released to proceed with execution as soon as possible,
-though some blocking of the main thread is still necessary while capturing
-the trace. Different trace formats can utilize a various number of
-threads. See the :vlopt:`--trace-threads` option.
+up to N additional threads will be created and managed by the trace files
+(e.g., VerilatedFstC), to offload construction of the trace dump. The main
+thread will be released to proceed with execution as soon as possible, though
+some main thread blocking is still necessary while capturing the
+trace. FST tracing can utilize up to 2 offload threads, so there is no use
+of setting :vlopt:`--trace-threads` higher than 2 at the moment.

 When running a multithreaded model, the default Linux task scheduler often
-works against the model, by assuming threads are short lived, and thus
-often schedules threads using multiple hyperthreads within the same
-physical core. For best performance use the :command:`numactl` program to
+works against the model by assuming short-lived threads and thus
+it often schedules threads using multiple hyperthreads within the same
+physical core. For best performance, use the :command:`numactl` program to
 (when the threading count fits) select unique physical cores on the same
 socket. The same applies for :vlopt:`--trace-threads` as well.

-As an example, if a model was Verilated with :vlopt:`--threads 4
-<--threads>`, we consult:
+As an example, if a model was Verilated with
+:vlopt:`--threads 4 <--threads>`, we consult:

 .. code-block:: bash

    egrep 'processor|physical id|core id' /proc/cpuinfo

 To select cores 0, 1, 2, and 3 that are all located on the same socket (0)
-but different physical cores.  (Also useful is :command:`numactl
--hardware`, or :command:`lscpu` but those doesn't show Hyperthreading
-cores.) Then we execute:
+but have different physical cores.  (Also useful is
+:command:`numactl --hardware`, or :command:`lscpu`, but those don't show
+hyperthreading cores.)  Then we execute:

 .. code-block:: bash

    numactl -m 0 -C 0,1,2,3 -- verilated_executable_name

 This will limit memory to socket 0, and threads to cores 0, 1, 2, 3,
-(presumably on socket 0) optimizing performance.  Of course this must be
-adjusted if you want another simulator using e.g. socket 1, or if you
+(presumably on socket 0), optimizing performance.  Of course, this must be
+adjusted if you want another simulator to use, e.g., socket 1, or if you
 Verilated with a different number of threads.  To see what CPUs are
-actually used, use :vlopt:`--prof-threads`.
+actually used, use :vlopt:`--prof-exec`.


 Multithreaded Verilog and Library Support
 -----------------------------------------

-$display/$stop/$finish are delayed until the end of an eval() call in order
+$display/$stop/$finish are delayed until the end of an eval() call
 to maintain ordering between threads. This may result in additional tasks
 completing after the $stop or $finish.

-If using :vlopt:`--coverage`, the coverage routines are fully thread safe.
+If using :vlopt:`--coverage`, the coverage routines are fully thread-safe.

-If using the DPI, Verilator assumes pure DPI imports are thread safe,
+If using the DPI, Verilator assumes pure DPI imports are thread-safe,
 balancing performance versus safety. See :vlopt:`--threads-dpi`.

 If using :vlopt:`--savable`, the save/restore classes are not multithreaded
 and must be called only by the eval thread.

-If using :vlopt:`--sc`, the SystemC kernel is not thread safe, therefore
+If using :vlopt:`--sc`, the SystemC kernel is not thread-safe; therefore,
 the eval thread and main thread must be the same.

 If using :vlopt:`--trace`, the tracing classes must be constructed and
@@ -304,8 +296,8 @@ Verilator defaults to creating GNU Make makefiles for the model.  Verilator
 will call make automatically when the :vlopt:'--build' option is used.

 If calling Verilator from a makefile, the :vlopt:'-MMD' option will create
-a dependency file which will allow Make to only run Verilator if input
-Verilog files change.
+a dependency file, allowing Make to only run Verilator if input Verilog
+files change.

 .. _CMake:

@@ -314,8 +306,8 @@ CMake

 Verilator can be run using CMake, which takes care of both running
 Verilator and compiling the output. There is a CMake example in the
-examples/ directory. The following is a minimal CMakeLists.txt that would
-build the code listed in :ref:`Example C++ Execution`
+:file:`examples/` directory. The following is a minimal CMakeLists.txt that
+would build the code listed in :ref:`Example C++ Execution`

 .. code-block:: CMake

@@ -327,8 +319,8 @@ build the code listed in :ref:`Example C++ Execution`
 :code:`find_package` will automatically find an installed copy of
 Verilator, or use a local build if VERILATOR_ROOT is set.

-It is recommended to use CMake >= 3.12 and the Ninja generator, though
-other combinations should work. To build with CMake, change to the folder
+Using CMake >= 3.12 and the Ninja generator is recommended, though other
+combinations should work. To build with CMake, change to the folder
 containing CMakeLists.txt and run:

 .. code-block:: bash
@@ -347,14 +339,14 @@ Or to build with your system default generator:
     cmake ..
     cmake --build .

-If you're building the example you should have an executable to run:
+If you're building the example, you should have an executable to run:

 .. code-block:: bash

     ./Vour

-The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT and
-VERILATOR_BIN to the appropriate values, and also creates a verilate()
+The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT,
+and VERILATOR_BIN to the appropriate values and creates a verilate()
 function. verilate() will automatically create custom commands to run
 Verilator and add the generated C++ sources to the target specified.

@@ -369,14 +361,14 @@ Verilate in CMake
              [OPT_GLOBAL ..] [DIRECTORY dir] [THREADS num]
              [TRACE_THREADS num] [VERILATOR_ARGS ...])

-Lowercase and ... should be replaced with arguments, the uppercase parts
-delimit the arguments and can be passed in any order, or left out entirely
+Lowercase and ... should be replaced with arguments; the uppercase parts
+delimit the arguments and can be passed in any order or left out entirely
 if optional.

 verilate(target ...) can be called multiple times to add other Verilog
 modules to an executable or library target.

-When generating Verilated SystemC sources, you should also include the
+When generating Verilated SystemC sources, you should list the
 SystemC include directories and link to the SystemC libraries.

 .. describe:: target
@@ -386,7 +378,7 @@ SystemC include directories and link to the SystemC libraries.
 .. describe:: COVERAGE

   Optional. Enables coverage if present, equivalent to "VERILATOR_ARGS
-   --coverage"
+   --coverage".

 .. describe:: DIRECTORY

@@ -414,22 +406,22 @@ SystemC include directories and link to the SystemC libraries.
 .. describe:: PREFIX

   Optional. Sets the Verilator output prefix. Defaults to the name of the
-   first source file with a "V" prepended. Must be unique in each call to
-   verilate(), so this is necessary if you build a module multiple times
-   with different parameters. Must be a valid C++ identifier, i.e. contains
-   no white space and only characters A-Z, a-z, 0-9 or _.
+   first source file with a "V" prepended. It must be unique in each call
+   to verilate(), so this is necessary if you build a module multiple times
+   with different parameters. It must be a valid C++ identifier, i.e., it
+   contains no white space and only characters A-Z, a-z, 0-9 or _.

 .. describe:: SOURCES

-   List of Verilog files to Verilate. Must have at least one file.
+   List of Verilog files to Verilate. You must provide at least one file.

 .. describe:: SYSTEMC

   Optional. Enables SystemC mode, defaults to C++ if not specified.

   When using Accellera's SystemC with CMake support, a CMake target is
-   available that simplifies the SystemC steps. This will only work if the
-   SystemC installation can be found by CMake. This can be configured by
+   available that simplifies the SystemC steps. This will only work if
+   CMake can find the SystemC installation, and this can be configured by
   setting the CMAKE_PREFIX_PATH variable during CMake configuration.

   Don't forget to set the same C++ standard for the Verilated sources as
@@ -438,12 +430,11 @@ SystemC include directories and link to the SystemC libraries.

 .. describe:: THREADS

-   Optional. Generated a multi-threaded model, same as "--threads".
+   Optional. Enable a multithreaded model; see :vlopt:`--threads`.

 .. describe:: TRACE_THREADS

-   Optional. Generated multi-threaded trace dumping, same as
-   "--trace-threads".
+   Optional. Enable multithreaded FST trace; see :vlopt:`--trace-threads`.

 .. describe:: TOP_MODULE

@@ -463,7 +454,7 @@ SystemC include directories and link to the SystemC libraries.
 .. describe:: VERILATOR_ARGS

   Optional. Extra arguments to Verilator. Do not specify :vlopt:`--Mdir`
-   or :vlopt:`--prefix` here, use DIRECTORY or PREFIX.
+   or :vlopt:`--prefix` here; use DIRECTORY or PREFIX.


 SystemC Link in CMake
@@ -2,15 +2,19 @@ ABCp
 Accellera
 Affe
 Aleksander
+Alexandre
 Ami
 Amir
 Anastasiadis
+Anikin
+Antmicro
 Antonin
 Antwerpen
 Arasanipalai
 Arjen
 Asciidoc
 Ashutosh
+Ast
 Atmel
 Aurelien
 Bagri
@@ -41,6 +45,7 @@ Cochrane
 Cuan
 Cygwin
 DErrico
+DFG
 Da
 Danilo
 Dannoritzer
@@ -70,6 +75,7 @@ Eda
 Eddleston
 Egbert
 Egil
+Ehab
 Eiler
 Eivind
 El
@@ -82,6 +88,7 @@ Fabrizio
 Fekete
 Ferrandi
 Flachs
+Flavien
 Foletto
 Forker
 Francillon
@@ -104,7 +111,10 @@ Goessling
 Gonnen
 Goorah
 Gossner
+Graphviz
+Graybeal
 Grobman
+Grulfen
 Gunter
 Guo
 Hao
@@ -121,10 +131,12 @@ Hornung
 Hossell
 Hsu
 Hyperthreading
+Ibrahim
 Iles
 Inlines
 Inout
 Iru
+Iyer
 Iztok
 Jacko
 Jae
@@ -134,6 +146,7 @@ Jannis
 Jens
 Jeras
 Jiuyang
+Joannou
 Joly
 Jullien
 Junji
@@ -147,8 +160,10 @@ Kamendje
 Kandadi
 Kaplan
 Karge
+Karlsson
 Katz
 Katzman
+Kelin
 Keren
 Keyi
 Kimmitt
@@ -161,6 +176,7 @@ Kolecki
 Koonce
 Korteland
 Koszek
+Kouping
 Kravitz
 Krolnik
 Kruse
@@ -194,8 +210,10 @@ Mednick
 Michiels
 Microsystems
 Milanovic
+Millis
 MinW
 Mindspeed
+MingW
 Miodrag
 ModelSim
 Modport
@@ -209,6 +227,7 @@ Nalbantis
 Narayan
 Nauticus
 Newgard
+Nigam
 Nikana
 Niranjan
 Nitza
@@ -223,18 +242,22 @@ Patricio
 Petr
 Piechotka
 Piersall
+Platzer
 Plunkett
+Popolon
 Popov
 Prabhat
 Prabhu
 Prateek
 Pre
 Preprocess
+Pretet
 Priyadharshini
 Pullup
 Pulver
 Puri
 Questa
+Rachit
 Ralf
 Rapp
 Redhat
@@ -262,12 +285,15 @@ Shi
 Shinkarovsky
 Shirakawa
 Shuba
+Shunyao
 Slatter
 SoC
 Sobhan
 Sokorac
 Solaris
 Solomatnikov
+Solt
+Southwell
 Srini
 Stamness
 Stephane
@@ -286,6 +312,7 @@ SystemVerilog
 Takatsukasa
 Tambe
 Tariq
+Tejada
 Tengstrand
 Terpstra
 Thiede
@@ -293,8 +320,10 @@ Thierry
 Thyer
 Tichelaar
 Tomov
+Tood
 Topa
 Tota
+Trefor
 Tresidder
 Tri
 Tristate
@@ -304,11 +333,13 @@ Ubixum
 Uints
 Undefines
 Unsized
+Urbach
 Uselib
 Usha
 Usuario
 VERILATOR
 Vasu
+Vdeeptemp
 Vdly
 Vemumtab
 Vemuri
@@ -320,6 +351,7 @@ Verilating
 Verilation
 Verilator
 Verilog
+Vighnesh
 Viktor
 Vm
 Vukobratovic
@@ -351,9 +383,13 @@ Zhang
 abirkmanis
 accessor
 accessors
+adrienlemasle
 agrobman
+ahouska
 al
 ala
+alejandro
+algrobman
 andit
 ar
 architected
@@ -372,11 +408,16 @@ backtrace
 backtraces
 basename
 bbox
+benchmarking
 biguint
 biops
+bisonpre
+bitOpTree
+bitop
 bitstoreal
 blackbox
 bokke
+bool
 brancoliticus
 buf
 bufif
@@ -387,8 +428,10 @@ callValueCbs
 casex
 casez
 casted
+castro
 cb
 ccache
+ccall
 cdc
 ceil
 celldefine
@@ -411,7 +454,10 @@ concat
 concats
 config
 const
+constexpr
+constpool
 coredump
+coroutine
 countbits
 countones
 cout
@@ -423,9 +469,11 @@ cutable
 cygwin
 dM
 da
+danbone
 dat
 datadir
 datafiles
+david
 ddd
 deassign
 debugi
@@ -433,7 +481,9 @@ defenv
 defname
 defparam
 demangling
+dep
 der
+dereference
 desassign
 destructor
 detections
@@ -449,6 +499,7 @@ dsvf
 dtor
 dumpall
 dumpfile
+dumpi
 dumplimit
 dumpoff
 dumpon
@@ -462,6 +513,7 @@ dumpvars
 dut
 dx
 elab
+elike
 elsif
 endcase
 endcelldefine
@@ -480,15 +532,18 @@ enums
 env
 envvar
 eof
+errae
 erroring
 et
 eval
+evals
 exe
 executables
 expr
 extern
 fanin
 fasttrace
+fauto
 fbranch
 fclose
 fdisplay
@@ -502,7 +557,9 @@ filesystem
 filt
 flto
 flushCall
+fno
 fopen
+forceable
 foreach
 fprintf
 fprofile
@@ -521,6 +578,7 @@ funcs
 fwrite
 gantt
 gcc
+gcda
 gdb
 genblk
 genvar
@@ -540,6 +598,7 @@ hierCMakeArgs
 hierMkArgs
 hierVer
 hx
+hyperthreading
 hyperthreads
 icecream
 idmap
@@ -550,8 +609,10 @@ ifndef
 impot
 incdir
 includer
+incrementing
 inferfaces
 inhibitSim
+initarray
 initializer
 initializers
 inits
@@ -562,14 +623,17 @@ inouts
 inserted
 instantiation
 instantiations
+intra
 iostream
 ish
 isunbounded
 isunknown
+jobserver
 killua
 lang
 lcov
 ld
+leavinel
 len
 libext
 libgoogle
@@ -584,8 +648,10 @@ ln
 loc
 localparam
 localparams
+localtime
 logicals
 longint
+lossy
 lsb
 lvalue
 lxt
@@ -595,6 +661,7 @@ makefiles
 manpages
 metacomment
 metacomments
+miree
 mis
 misconnected
 misconversion
@@ -603,6 +670,7 @@ mk
 mno
 modport
 modports
+mpb
 msg
 msvc
 mtask
@@ -618,6 +686,7 @@ multithreaded
 multithreading
 mutexes
 mux
+myftptoyman
 mysignal
 namespace
 nand
@@ -641,16 +710,21 @@ nullptr
 onehot
 ooo
 oprofile
+ortegon
 oversubscription
+parallelized
 param
 parameterized
 params
 parens
+pawel
 pc
 pdf
 perf
 perftools
+pgo
 picoChip
+pinIndex
 pinout
 plusargs
 pmos
@@ -660,6 +734,8 @@ portlists
 posedge
 posix
 postfix
+postincreemnt
+postincrement
 pragma
 pragmas
 pre
@@ -676,9 +752,11 @@ prev
 printf
 printtimescale
 profcfunc
+profiler
 prototyptes
 ps
 pthread
+ptr
 pulldown
 pulldowns
 pullup
@@ -687,6 +765,7 @@ pwd
 qrq
 radix
 randc
+randcase
 rarr
 rdtsc
 reStructuredText
@@ -703,12 +782,15 @@ regs
 reloop
 resetall
 respecified
+rodata
+rolloverSize
 rr
 rst
 runtime
 runtimes
 rw
 sVerilator
+sawatzke
 sc
 scalared
 sccanf
@@ -716,6 +798,7 @@ seg
 setuphold
 sformat
 sformatf
+shareefj
 shortint
 shortreal
 signame
@@ -724,6 +807,7 @@ specparam
 splitme
 spp
 sqrt
+src
 srcdir
 srcfile
 sscanf
@@ -741,8 +825,10 @@ structs
 subcell
 subcells
 subexpressions
+submakes
 submodule
 submodules
+substring
 sv
 svBitVal
 svBitVecVal
@@ -777,6 +863,7 @@ trunc
 txt
 typ
 typedef
+typedef'ed
 typedefed
 typedefs
 typename
@@ -790,6 +877,7 @@ uniquified
 unistd
 unlink
 unlinked
+unnamedblk
 unopt
 unoptflat
 unoptimizable
@@ -839,11 +927,15 @@ writeme
 writemem
 writememb
 writememh
+xiak
 xin
 xml
 xnor
 xout
 xuejiazidi
 yanx
+ypq
 yurivict
 zdave
+Øyvind
+
@@ -1,4 +1,4 @@
-PROJECT_NAME           = "Verilog to Routing - ABC"
+PROJECT_NAME           = "Verilator"
 INPUT                  = ../../include
 OUTPUT_DIRECTORY       = _build/doxygen/verilated

@@ -37,5 +37,4 @@ PREDEFINED             = \
                         "VL_NOT_FINAL=" \
                         "VL_PURE=" \
                         "VL_REQUIRES()=" \
-                         "VL_THREAD_LOCAL=" \
                         "__restrict=" \
@@ -46,9 +46,6 @@ The XML document consists of 4 sections within the top level
   hierarchy. Each instance is represented with the ``<cell>`` element
   with the following attributes:

-   -  ``fl`` (deprecated): The file id and line number where the module
-      was instanced. Use ``loc`` instead.
-
   -  ``loc``: The file id, first line number, last line number, first
      column number and last column number of the identifier where the
      module was instanced, separated by commas.
@@ -73,8 +70,10 @@ The XML document consists of 4 sections within the top level
 Distribution
 ============

-Copyright 2020-2021 by Wilson Snyder. Verilator is free software; you can
+Copyright 2020-2023 by Wilson Snyder. Verilator is free software; you can
 redistribute it and/or modify it under the terms of either the GNU Lesser
 General Public License Version 3 or the Perl Artistic License Version 2.0.

+SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
 .. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png
@@ -39,30 +39,12 @@ ifneq ($(CMAKE_GT_3_8),true)
 TARGET := oldcmake
 else

-# Test existence of SYSTEMC_INCLUDE and SYSTEMC_LIBDIR environment variabless
-ifneq (,$(SYSTEMC_INCLUDE))
-ifneq (,${SYSTEMC_LIBDIR})
-SYSTEMC_SET := true
-endif
-endif
-
-# Test existence of SYSTEMC_ROOT environment variable
-ifneq (SYSTEMC_SET, true)
-ifneq (,${SYSTEMC_ROOT})
-SYSTEMC_SET := true
-endif
-endif
-
-# Test existence of SYSTEMC environment variable
-ifneq (SYSTEMC_SET, true)
-ifneq (,${SYSTEMC})
-SYSTEMC_SET := true
-endif
-endif
+# Check if SC exists via a verilator call (empty if not)
+SYSTEMC_EXISTS := $(shell $(VERILATOR) --get-supported SYSTEMC)

 # Test whether SystemC is installed with CMake support
 # This will print a CMake error about processing arguments that can (currently) be ignored.
-ifneq (SYSTEMC_SET, true)
+ifneq (,$(SYSTEMC_EXISTS))
 FINDSC := $(shell mkdir -p build && cd build && cmake --find-package -DNAME=SystemCLanguage -DCMAKE_USE_PTHREADS_INIT=ON -DCOMPILER_ID=GNU -DLANGUAGE=CXX -DMODE=EXIST -DThreads_FOUND=ON)
 ifneq (,$(findstring SystemCLanguage found,$(FINDSC)))
 SYSTEMC_SET := true
@@ -99,7 +81,7 @@ run:

 	@echo "-- DONE --------------------"
 	@echo "Note: Once this example is understood, see examples/cmake_tracing_sc."
-	@echo "Note: Also see the EXAMPLE section in the verilator manpage/document."
+	@echo "Note: See also https://verilator.org/guide/latest/examples.html"

 clean mostlyclean distclean maintainer-clean:
 	@rm -rf build logs
@@ -33,5 +33,5 @@ add_executable(example ../make_tracing_c/sim_main.cpp)
 # Add the Verilated circuit to the target
 verilate(example COVERAGE TRACE
  INCLUDE_DIRS "../make_tracing_c"
-  VERILATOR_ARGS -f ../make_tracing_c/input.vc -Os -x-assign 0
+  VERILATOR_ARGS -f ../make_tracing_c/input.vc -x-assign fast
  SOURCES ../make_tracing_c/top.v)
@@ -45,7 +45,7 @@ set_property(
 # Add the Verilated circuit to the target
 verilate(example SYSTEMC COVERAGE TRACE
  INCLUDE_DIRS "../make_tracing_sc"
-  VERILATOR_ARGS -f ../make_tracing_sc/input.vc -Os -x-assign 0
+  VERILATOR_ARGS -f ../make_tracing_sc/input.vc -x-assign fast
  SOURCES ../make_tracing_sc/top.v)

 verilator_link_systemc(example)
@@ -39,30 +39,12 @@ ifneq ($(CMAKE_GT_3_8),true)
 TARGET := oldcmake
 else

-# Test existence of SYSTEMC_INCLUDE and SYSTEMC_LIBDIR environment variabless
-ifneq (,$(SYSTEMC_INCLUDE))
-ifneq (,${SYSTEMC_LIBDIR})
-SYSTEMC_SET := true
-endif
-endif
-
-# Test existence of SYSTEMC_ROOT environment variable
-ifneq (SYSTEMC_SET, true)
-ifneq (,${SYSTEMC_ROOT})
-SYSTEMC_SET := true
-endif
-endif
-
-# Test existence of SYSTEMC environment variable
-ifneq (SYSTEMC_SET, true)
-ifneq (,${SYSTEMC})
-SYSTEMC_SET := true
-endif
-endif
+# Check if SC exists via a verilator call (empty if not)
+SYSTEMC_EXISTS := $(shell $(VERILATOR) --get-supported SYSTEMC)

 # Test whether SystemC is installed with CMake support
 # This will print a CMake error about processing arguments that can (currently) be ignored.
-ifneq (SYSTEMC_SET, true)
+ifneq (,$(SYSTEMC_EXISTS))
 FINDSC := $(shell mkdir -p build && cd build && cmake --find-package -DNAME=SystemCLanguage -DCMAKE_USE_PTHREADS_INIT=ON -DCOMPILER_ID=GNU -DLANGUAGE=CXX -DMODE=EXIST -DThreads_FOUND=ON)
 ifneq (,$(findstring SystemCLanguage found,$(FINDSC)))
 SYSTEMC_SET := true
@@ -0,0 +1,6 @@
+*.dmp
+*.log
+*.csrc
+*.vcd
+obj_*
+logs
@@ -0,0 +1,49 @@
+######################################################################
+#
+# DESCRIPTION: Verilator Example: Small Makefile
+#
+# This calls the object directory makefile.  That allows the objects to
+# be placed in the "current directory" which simplifies the Makefile.
+#
+# This file ONLY is placed under the Creative Commons Public Domain, for
+# any use, without warranty, 2020 by Wilson Snyder.
+# SPDX-License-Identifier: CC0-1.0
+#
+######################################################################
+# Check for sanity to avoid later confusion
+
+ifneq ($(words $(CURDIR)),1)
+ $(error Unsupported: GNU Make cannot build in directories containing spaces, build elsewhere: '$(CURDIR)')
+endif
+
+######################################################################
+
+# This is intended to be a minimal example.  Before copying this to start a
+# real project, it is better to start with a more complete example,
+# e.g. examples/make_tracing_c.
+
+# If $VERILATOR_ROOT isn't in the environment, we assume it is part of a
+# package install, and verilator is in your path. Otherwise find the
+# binary relative to $VERILATOR_ROOT (such as when inside the git sources).
+ifeq ($(VERILATOR_ROOT),)
+VERILATOR = verilator
+else
+export VERILATOR_ROOT
+VERILATOR = $(VERILATOR_ROOT)/bin/verilator
+endif
+
+default:
+	@echo "-- Verilator hello-world simple binary example"
+	@echo "-- VERILATE & BUILD --------"
+	$(VERILATOR) --binary -j 0 top.v
+	@echo "-- RUN ---------------------"
+	obj_dir/Vtop
+	@echo "-- DONE --------------------"
+	@echo "Note: Once this example is understood, see examples/make_hello_c."
+	@echo "Note: See also https://verilator.org/guide/latest/examples.html"
+
+######################################################################
+
+maintainer-copy::
+clean mostlyclean distclean maintainer-clean::
+	-rm -rf obj_dir *.log *.dmp *.vpd core
@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog example module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2017 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// See also https://verilator.org/guide/latest/examples.html"
+
+module top;
+   initial begin
+      $display("Hello World!");
+      $finish;
+   end
+endmodule
@@ -40,7 +40,7 @@ default:
 	obj_dir/Vtop
 	@echo "-- DONE --------------------"
 	@echo "Note: Once this example is understood, see examples/make_tracing_c."
-	@echo "Note: Also see the EXAMPLE section in the verilator manpage/document."
+	@echo "Note: See also https://verilator.org/guide/latest/examples.html"

 ######################################################################

@@ -11,21 +11,25 @@
 // Include model header, generated from Verilating "top.v"
 #include "Vtop.h"

-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
    // See a similar example walkthrough in the verilator manpage.

    // This is intended to be a minimal example.  Before copying this to start a
    // real project, it is better to start with a more complete example,
    // e.g. examples/c_tracing.

-    // Prevent unused variable warnings
-    if (false && argc && argv && env) {}
+    // Construct a VerilatedContext to hold simulation time, etc.
+    VerilatedContext* contextp = new VerilatedContext;
+
+    // Pass arguments so Verilated code can see them, e.g. $value$plusargs
+    // This needs to be called before you create any model
+    contextp->commandArgs(argc, argv);

    // Construct the Verilated model, from Vtop.h generated from Verilating "top.v"
-    Vtop* top = new Vtop;
+    Vtop* top = new Vtop{contextp};

    // Simulate until $finish
-    while (!Verilated::gotFinish()) {
+    while (!contextp->gotFinish()) {

        // Evaluate model
        top->eval();
@@ -4,7 +4,8 @@
 // any use, without warranty, 2017 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0

-// See also the EXAMPLE section in the verilator manpage/document.
+// See also https://verilator.org/guide/latest/examples.html"
+
 module top;
   initial begin
      $display("Hello World!");
@@ -33,7 +33,7 @@ VERILATOR = $(VERILATOR_ROOT)/bin/verilator
 endif

 # Check if SC exists via a verilator call (empty if not)
-SYSTEMC_EXISTS := $(shell $(VERILATOR) --getenv SYSTEMC_INCLUDE)
+SYSTEMC_EXISTS := $(shell $(VERILATOR) --get-supported SYSTEMC)

 ifneq ($(SYSTEMC_EXISTS),)
 default: run
@@ -49,7 +49,7 @@ run:
 	obj_dir/Vtop
 	@echo "-- DONE --------------------"
 	@echo "Note: Once this example is understood, see examples/make_tracing_sc."
-	@echo "Note: Also see the EXAMPLE section in the verilator manpage/document."
+	@echo "Note: See also https://verilator.org/guide/latest/examples.html"

 ######################################################################

@@ -22,12 +22,13 @@ int sc_main(int argc, char* argv[]) {
    // real project, it is better to start with a more complete example,
    // e.g. examples/c_tracing.

-    // Prevent unused variable warnings
-    if (false && argc && argv) {}
-
    // Construct the Verilated model, from Vtop.h generated from Verilating "top.v"
    Vtop* top = new Vtop{"top"};

+    // Pass arguments so Verilated code can see them, e.g. $value$plusargs
+    // This needs to be called before you create any model
+    Verilated::commandArgs(argc, argv);
+
    // Initialize SC model
    sc_start(1, SC_NS);

@@ -4,7 +4,8 @@
 // any use, without warranty, 2017 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0

-// See also the EXAMPLE section in the verilator manpage/document.
+// See also https://verilator.org/guide/latest/examples.html"
+
 module top;
   initial begin
      $display("Hello World!");
@@ -33,7 +33,7 @@ VERILATOR_FLAGS =
 # Generate C++
 VERILATOR_FLAGS += -cc
 # Optimize
-VERILATOR_FLAGS += -Os -x-assign 0
+VERILATOR_FLAGS += -x-assign fast
 # Warn abount lint issues; may not want this on less solid designs
 VERILATOR_FLAGS += -Wall
 # This example does not use vl_time_stamp but rather
@@ -16,8 +16,8 @@
 #include <verilated_vcd_c.h>
 #endif

-int main(int argc, char** argv, char** env) {
-    if (false && argc && argv && env) {}
+int main(int argc, char** argv) {
+    if (false && argc && argv) {}

    // Construct context to hold simulation time, etc
    VerilatedContext* contextp = new VerilatedContext;
@@ -32,7 +32,7 @@ int main(int argc, char** argv, char** env) {
    // When tracing, the contents of the secret module will not be seen
    VerilatedVcdC* tfp = nullptr;
    const char* flag = contextp->commandArgsPlusMatch("trace");
-    if (flag && 0 == strcmp(flag, "+trace")) {
+    if (flag && 0 == std::strcmp(flag, "+trace")) {
        contextp->traceEverOn(true);
        VL_PRINTF("Enabling waves into logs/vlt_dump.vcd...\n");
        tfp = new VerilatedVcdC;
@@ -4,7 +4,8 @@
 // any use, without warranty, 2019 by Todd Strader.
 // SPDX-License-Identifier: CC0-1.0

-// See also the EXAMPLE section in the verilator manpage/document.
+// See also https://verilator.org/guide/latest/examples.html"
+
 module top (input clk);

   integer cyc = 0;
@@ -36,7 +36,7 @@ VERILATOR_FLAGS += -cc --exe
 # Generate makefile dependencies (not shown as complicates the Makefile)
 #VERILATOR_FLAGS += -MMD
 # Optimize
-VERILATOR_FLAGS += -Os -x-assign 0
+VERILATOR_FLAGS += -x-assign fast
 # Warn abount lint issues; may not want this on less solid designs
 VERILATOR_FLAGS += -Wall
 # Make waveforms
@@ -17,11 +17,11 @@
 // Legacy function required only so linking works on Cygwin and MSVC++
 double sc_time_stamp() { return 0; }

-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
    // This is a more complicated example, please also see the simpler examples/make_hello_c.

    // Prevent unused variable warnings
-    if (false && argc && argv && env) {}
+    if (false && argc && argv) {}

    // Create logs/ directory in case we have traces to put under it
    Verilated::mkdir("logs");
@@ -34,6 +34,8 @@ int main(int argc, char** argv, char** env) {
    // Using unique_ptr is similar to
    // "VerilatedContext* contextp = new VerilatedContext" then deleting at end.
    const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+    // Do not instead make Vtop as a file-scope static variable, as the
+    // "C++ static initialization order fiasco" may cause a crash

    // Set debug level, 0 is off, 9 is highest presently used
    // May be overridden by commandArgs argument parsing
@@ -69,7 +71,7 @@ int main(int argc, char** argv, char** env) {
        // Historical note, before Verilator 4.200 Verilated::gotFinish()
        // was used above in place of contextp->gotFinish().
        // Most of the contextp-> calls can use Verilated:: calls instead;
-        // the Verilated:: versions simply assume there's a single context
+        // the Verilated:: versions just assume there's a single context
        // being used (per thread).  It's faster and clearer to use the
        // newer contextp-> versions.

@@ -103,8 +105,8 @@ int main(int argc, char** argv, char** env) {
        top->eval();

        // Read outputs
-        VL_PRINTF("[%" VL_PRI64 "d] clk=%x rstl=%x iquad=%" VL_PRI64 "x"
-                  " -> oquad=%" VL_PRI64 "x owide=%x_%08x_%08x\n",
+        VL_PRINTF("[%" PRId64 "] clk=%x rstl=%x iquad=%" PRIx64 " -> oquad=%" PRIx64
+                  " owide=%x_%08x_%08x\n",
                  contextp->time(), top->clk, top->reset_l, top->in_quad, top->out_quad,
                  top->out_wide[2], top->out_wide[1], top->out_wide[0]);
    }
@@ -37,7 +37,7 @@ VERILATOR_FLAGS += -sc --exe
 # Generate makefile dependencies (not shown as complicates the Makefile)
 #VERILATOR_FLAGS += -MMD
 # Optimize
-VERILATOR_FLAGS += -Os -x-assign 0
+VERILATOR_FLAGS += -x-assign fast
 # Warn abount lint issues; may not want this on less solid designs
 VERILATOR_FLAGS += -Wall
 # Make waveforms
@@ -55,7 +55,7 @@ VERILATOR_FLAGS += --coverage
 VERILATOR_INPUT = -f input.vc top.v sc_main.cpp

 # Check if SC exists via a verilator call (empty if not)
-SYSTEMC_EXISTS := $(shell $(VERILATOR) --getenv SYSTEMC_INCLUDE)
+SYSTEMC_EXISTS := $(shell $(VERILATOR) --get-supported SYSTEMC)

 ######################################################################

@@ -58,11 +58,11 @@ int sc_main(int argc, char* argv[]) {

    // Define interconnect
    sc_signal<bool> reset_l;
-    sc_signal<vluint32_t> in_small;
-    sc_signal<vluint64_t> in_quad;
+    sc_signal<uint32_t> in_small;
+    sc_signal<uint64_t> in_quad;
    sc_signal<sc_bv<70>> in_wide;
-    sc_signal<vluint32_t> out_small;
-    sc_signal<vluint64_t> out_quad;
+    sc_signal<uint32_t> out_small;
+    sc_signal<uint64_t> out_quad;
    sc_signal<sc_bv<70>> out_wide;

    // Construct the Verilated model, from inside Vtop.h
@@ -82,15 +82,15 @@ int sc_main(int argc, char* argv[]) {

    // You must do one evaluation before enabling waves, in order to allow
    // SystemC to interconnect everything for testing.
-    sc_start(1, SC_NS);
+    sc_start(SC_ZERO_TIME);

 #if VM_TRACE
    // If verilator was invoked with --trace argument,
    // and if at run time passed the +trace argument, turn on tracing
    VerilatedVcdSc* tfp = nullptr;
    const char* flag = Verilated::commandArgsPlusMatch("trace");
-    if (flag && 0 == strcmp(flag, "+trace")) {
-        cout << "Enabling waves into logs/vlt_dump.vcd...\n";
+    if (flag && 0 == std::strcmp(flag, "+trace")) {
+        std::cout << "Enabling waves into logs/vlt_dump.vcd...\n";
        tfp = new VerilatedVcdSc;
        top->trace(tfp, 99);  // Trace 99 levels of hierarchy
        Verilated::mkdir("logs");
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 # -*- Python -*- See copyright, etc below
-# pylint: disable=C0114,C0115,R0903
+# pylint: disable=C0114,C0115,C0209,R0903
 ######################################################################

 import argparse
@@ -16,27 +16,26 @@ from shutil import copy2


 class VlFileCopy:
+
    def __init__(
-        self,
-        verilator_args,  # presently all verilator options are passed-thru
-        # ideally this script would check against options mentioned in help
-        debug=0,
-        output_dir='copied'):  # directory name we output file uses
+            self,
+            verilator_args,  # presently all verilator options are passed-thru
+            debug=0,
+            output_dir='copied'):  # directory name we output file uses

        self.debug = debug

-        xml_temp = tempfile.NamedTemporaryFile()
-
-        vargs = [
-            '--xml-output',
-            xml_temp.name,
-            '--bbox-sys',  # Parse some stuff can't translate
-            '--bbox-unsup',
-            '--prefix vlxml'
-        ]  # So we know name of .xml output
-        vargs += verilator_args
-        self.run_verilator(vargs)
-        self.tree = ET.parse(xml_temp.name)
+        with tempfile.NamedTemporaryFile() as xml_temp:
+            vargs = [
+                '--xml-output',
+                xml_temp.name,
+                '--bbox-sys',  # Parse some stuff can't translate
+                '--bbox-unsup',
+                '--prefix vlxml'
+            ]  # So we know name of .xml output
+            vargs += verilator_args
+            self.run_verilator(vargs)
+            self.tree = ET.parse(xml_temp.name)

        os.makedirs(output_dir, 0o777, True)

@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 # -*- Python -*- See copyright, etc below
-# pylint: disable=C0103,C0114,C0115,C0115,C0116,R0914
+# pylint: disable=C0103,C0114,C0115,C0115,C0116,C0209,R0914
 ######################################################################

 import argparse
@@ -14,30 +14,29 @@ import xml.etree.ElementTree as ET


 class VlHierGraph:
+
    def __init__(
-        self,
-        verilator_args,  # presently all verilator options are passed-thru
-        # ideally this script would check against options mentioned in help
-        debug=0,
-        output_filename='graph.dot'):  # output filename
+            self,
+            verilator_args,  # presently all verilator options are passed-thru
+            debug=0,
+            output_filename='graph.dot'):  # output filename
        self.debug = debug
        self.next_vertex_number = 0
        self.name_to_number = {}

-        xml_temp = tempfile.NamedTemporaryFile()
+        with tempfile.NamedTemporaryFile() as xml_temp:
+            vargs = [
+                '--xml-output',
+                xml_temp.name,
+                '--bbox-sys',  # Parse some stuff can't translate
+                '--bbox-unsup',
+                '--prefix vlxml'
+            ]  # So we know name of .xml output
+            vargs += verilator_args
+            self.run_verilator(vargs)
+            self.tree = ET.parse(xml_temp.name)

-        vargs = [
-            '--xml-output',
-            xml_temp.name,
-            '--bbox-sys',  # Parse some stuff can't translate
-            '--bbox-unsup',
-            '--prefix vlxml'
-        ]  # So we know name of .xml output
-        vargs += verilator_args
-        self.run_verilator(vargs)
-        self.tree = ET.parse(xml_temp.name)
-
-        with open(output_filename, "w") as fh:
+        with open(output_filename, "w", encoding="utf8") as fh:
            # For more serious purposes, use the python graphviz package instead
            fh.write("digraph {\n")
            fh.write("  dpi=300;\n")
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009-2018 Tony Bybell.
+ * Copyright (c) 2009-2023 Tony Bybell.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -140,6 +140,10 @@ void **JenkinsIns(void *base_i, const unsigned char *mem, uint32_t length, uint3
 #include <sys/sysctl.h>
 #endif

+#if defined(FST_MACOSX) || defined(__MINGW32__) || defined(__OpenBSD__) || defined(__FreeBSD__) || defined(__NetBSD__)
+#define FST_UNBUFFERED_IO
+#endif
+
 #ifdef __GNUC__
 /* Boolean expression more often true than false */
 #define FST_LIKELY(x) __builtin_expect(!!(x), 1)
@@ -4126,26 +4130,35 @@ if(xc->do_rewind)
 if(!(isfeof=feof(xc->fh)))
        {
        int tag = fgetc(xc->fh);
+	int cl;
        switch(tag)
                {
                case FST_ST_VCD_SCOPE:
                        xc->hier.htyp = FST_HT_SCOPE;
                        xc->hier.u.scope.typ = fgetc(xc->fh);
                        xc->hier.u.scope.name = pnt = xc->str_scope_nam;
+			cl = 0;
                        while((ch = fgetc(xc->fh)))
                                {
-                                *(pnt++) = ch;
+				if(cl <= FST_ID_NAM_SIZ)
+					{
+					pnt[cl++] = ch;
+					}
                                }; /* scopename */
-                        *pnt = 0;
-                        xc->hier.u.scope.name_length = pnt - xc->hier.u.scope.name;
+                        pnt[cl] = 0;
+                        xc->hier.u.scope.name_length = cl;

                        xc->hier.u.scope.component = pnt = xc->str_scope_comp;
+			cl = 0;
                        while((ch = fgetc(xc->fh)))
                                {
-                                *(pnt++) = ch;
+				if(cl <= FST_ID_NAM_SIZ)
+					{
+					pnt[cl++] = ch;
+					}
                                }; /* scopecomp */
-                        *pnt = 0;
-                        xc->hier.u.scope.component_length = pnt - xc->hier.u.scope.component;
+                        pnt[cl] = 0;
+                        xc->hier.u.scope.component_length = cl;
                        break;

                case FST_ST_VCD_UPSCOPE:
@@ -4157,12 +4170,16 @@ if(!(isfeof=feof(xc->fh)))
                        xc->hier.u.attr.typ = fgetc(xc->fh);
                        xc->hier.u.attr.subtype = fgetc(xc->fh);
                        xc->hier.u.attr.name = pnt = xc->str_scope_nam;
+			cl = 0;
                        while((ch = fgetc(xc->fh)))
                                {
-                                *(pnt++) = ch;
+				if(cl <= FST_ID_NAM_SIZ)
+					{
+					pnt[cl++] = ch;
+					}
                                }; /* scopename */
-                        *pnt = 0;
-                        xc->hier.u.attr.name_length = pnt - xc->hier.u.scope.name;
+			pnt[cl] = 0;
+                        xc->hier.u.attr.name_length = cl;

                        xc->hier.u.attr.arg = fstReaderVarint64(xc->fh);

@@ -4217,12 +4234,16 @@ if(!(isfeof=feof(xc->fh)))
                        xc->hier.u.var.typ = tag;
                        xc->hier.u.var.direction = fgetc(xc->fh);
                        xc->hier.u.var.name = pnt = xc->str_scope_nam;
+			cl = 0;
                        while((ch = fgetc(xc->fh)))
                                {
-                                *(pnt++) = ch;
+				if(cl <= FST_ID_NAM_SIZ)
+					{
+					pnt[cl++] = ch;
+					}
                                }; /* varname */
-                        *pnt = 0;
-                        xc->hier.u.var.name_length = pnt - xc->hier.u.var.name;
+                        pnt[cl] = 0;
+                        xc->hier.u.var.name_length = cl;
                        xc->hier.u.var.length = fstReaderVarint32(xc->fh);
                        if(tag == FST_VT_VCD_PORT)
                                {
@@ -4269,6 +4290,7 @@ unsigned int num_signal_dyn = 65536;
 int attrtype, subtype;
 uint64_t attrarg;
 fstHandle maxhandle_scanbuild;
+int cl;

 if(!xc) return(0);

@@ -4351,11 +4373,15 @@ while(!feof(xc->fh))
                        scopetype = fgetc(xc->fh);
                        if((scopetype < FST_ST_MIN) || (scopetype > FST_ST_MAX)) scopetype = FST_ST_VCD_MODULE;
                        pnt = str;
+			cl = 0;
                        while((ch = fgetc(xc->fh)))
                                {
-                                *(pnt++) = ch;
+				if(cl <= FST_ID_NAM_ATTR_SIZ)
+					{
+					pnt[cl++] = ch;
+					}
                                }; /* scopename */
-                        *pnt = 0;
+                        pnt[cl] = 0;
                        while(fgetc(xc->fh)) { }; /* scopecomp */

                        if(fv) fprintf(fv, "$scope %s %s $end\n", modtypes[scopetype], str);
@@ -4369,11 +4395,15 @@ while(!feof(xc->fh))
                        attrtype = fgetc(xc->fh);
                        subtype = fgetc(xc->fh);
                        pnt = str;
+			cl = 0;
                        while((ch = fgetc(xc->fh)))
                                {
-                                *(pnt++) = ch;
+				if(cl <= FST_ID_NAM_ATTR_SIZ)
+					{
+					pnt[cl++] = ch;
+					}
                                }; /* attrname */
-                        *pnt = 0;
+                        pnt[cl] = 0;

                        if(!str[0]) { strcpy(str, "\"\""); }

@@ -4454,11 +4484,15 @@ while(!feof(xc->fh))
                        vartype = tag;
                        /* vardir = */ fgetc(xc->fh); /* unused in VCD reader, but need to advance read pointer */
                        pnt = str;
+			cl = 0;
                        while((ch = fgetc(xc->fh)))
                                {
-                                *(pnt++) = ch;
+				if(cl <= FST_ID_NAM_ATTR_SIZ)
+					{
+					pnt[cl++] = ch;
+					}
                                }; /* varname */
-                        *pnt = 0;
+                        pnt[cl] = 0;
                        len = fstReaderVarint32(xc->fh);
                        alias = fstReaderVarint32(xc->fh);

@@ -4577,12 +4611,11 @@ if(sectype == FST_BL_ZWRAPPER)
                if(!fcomp) { tmpfile_close(&fcomp, &xc->f_nam); return(0); }
                }

-#if defined(FST_MACOSX)
+#if defined(FST_UNBUFFERED_IO)
        setvbuf(fcomp, (char *)NULL, _IONBF, 0);   /* keeps gzip from acting weird in tandem with fopen */
 #endif

 #ifdef __MINGW32__
-        setvbuf(fcomp, (char *)NULL, _IONBF, 0);   /* keeps gzip from acting weird in tandem with fopen */
        xc->filename_unpacked = hf;
 #else
        if(hf)
@@ -4880,7 +4913,7 @@ if((!nam)||(!(xc->f=fopen(nam, "rb"))))
        char *hf = (char *)calloc(1, flen + 6);
        int rc;

-#if defined(__MINGW32__) || defined(FST_MACOSX)
+#if defined(FST_UNBUFFERED_IO)
        setvbuf(xc->f, (char *)NULL, _IONBF, 0);   /* keeps gzip from acting weird in tandem with fopen */
 #endif

--- a/Show More
+++ b/Show More