V3MergeCond: Fix incorrect merge of assignments to the condition

src/V3MergeCond.cpp

@@ -790,6 +790,8 @@ private:
     // otherwise end the current merge. Return ture if added, false if ended merge.
     bool addIfHelpfulElseEndMerge(AstNodeStmt* nodep) {
         UASSERT_OBJ(m_mgFirstp, nodep, "List must be open");
+        if (!checkOrMakeMergeable(nodep)) return false;
+        if (!m_mgFirstp) return false;  // If 'checkOrMakeMergeable' closed the list
         if (m_mgNextp == nodep) {
             if (isSimplifiableNode(nodep)) {
                 if (addToList(nodep, nullptr)) return true;

test_regress/t/t_merge_cond_no_extend.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Geza Lore. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt_all => 1);
+
+compile(
+    verilator_flags2 => ["--stats"],
+    );
+
+file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/i, 0);
+
+ok(1);
+1;

test_regress/t/t_merge_cond_no_extend.v

@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Geza Lore.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (
+    input wire clk,
+    input wire [7:0] i,
+    input wire a,
+    output reg [7:0] o
+);
+
+   reg cond = 0;
+
+   always @(posedge clk) begin
+     if (cond) o = i;
+     cond = a;
+     if (cond) o = ~i;
+   end
+
+endmodule