Tests: Fix some internal code coverage holes

test_regress/t/t_assoc_wildcard_method.v

@@ -11,7 +11,7 @@
 module t (/*AUTOARG*/);
    initial begin
       int q[*];
-      int qe[*];  // Empty
+      int qe [ * ];  // Empty - Note spaces around [*] for parsing coverage
       int qv[$];  // Value returns
       int qi[$];  // Index returns
       int i;

test_regress/t/t_program_anonymous.out

@@ -0,0 +1,5 @@
+%Error-UNSUPPORTED: t/t_program_anonymous.v:7:1: Unsupported: Anonymous programs
+    7 | program;
+      | ^~~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to

test_regress/t/t_program_anonymous.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+execute(
+    check_finished => 1,
+    ) if !$Self->{vlt_all};
+
+ok(1);
+1;

test_regress/t/t_program_anonymous.v

@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+program;
+   task atask;
+   endtask
+   function int afunc(input int i);
+      return i+1;
+   endfunction
+class acls;
+   static int i = 10;
+endclass
+endprogram
+
+program t(/*AUTOARG*/);
+
+   int i;
+
+   initial begin
+      atask();
+
+      i = afunc(2);
+      if (i != 3) $stop;
+
+      if (acls::i != 10) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endprogram

test_regress/t/t_program_extern.out

@@ -0,0 +1,5 @@
+%Error-UNSUPPORTED: t/t_program_extern.v:7:1: Unsupported: extern program
+    7 | extern program pgm;
+      | ^~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to

test_regress/t/t_program_extern.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+execute(
+    check_finished => 1,
+    ) if !$Self->{vlt_all};
+
+ok(1);
+1;

test_regress/t/t_program_extern.v

@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+extern program pgm;
+
+program pgm;
+   task ptask;
+   endtask
+endprogram
+
+module t(/*AUTOARG*/);
+
+   pgm sub ();
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

test_regress/t/t_trace_two_a.v

@@ -32,7 +32,7 @@ module t (/*AUTOARG*/
 
 `ifdef TEST_DUMP
       $dumpfile(filename);
-      $dumpvars(0, top);
+      $dumpvars(0);  // Intentionally no ", top" for parsing coverage with just (expr)
       $dumplimit(10 * 1024 * 1024);
 `elsif TEST_DUMPPORTS
       $dumpports(top, filename);