Tests: Fix whitespace test and resulting fallout.

test_regress/t/t_dist_whitespace.pl

@@ -16,11 +16,12 @@ my $Debug;
 ### Must trim output before and after our file list
 my %files = %{get_source_files($root)};
 
+my $any = 0;
 foreach my $file (sort keys %files) {
     my $filename = "$root/$file";
-    next if !-f $file;  # git file might be deleted but not yet staged
+    next if !-f $filename;  # git file might be deleted but not yet staged
     my $contents = file_contents($filename);
-    if ($file =~ /\.out$/) {
+    if ($file =~ /(\.out|\.dat)$/) {
         # Ignore golden files
         next;
     } elsif ($contents =~ /[\001\002\003\004\005\006]/) {
@@ -61,7 +62,9 @@ foreach my $file (sort keys %files) {
             $warns{$file} = "Trailing newlines at EOF in $file";
         }
     }
+    ++$any;
 }
+$any > 50 or error("Too few source files found");
 
 if (keys %warns) {
     # First warning lists everything as that's shown in the driver summary

test_regress/t/t_dpi_export_scope_bad.v

@@ -18,4 +18,4 @@ module s;
    task dpix_task();
       $write("Hello in %m\n");
    endtask
-endmodule   
+endmodule

test_regress/t/t_enum_type_bad.v

@@ -5,7 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t;
-   
+
    typedef enum {ZERO, ONE, TWO} e_t;
 
    typedef enum {THREE=3, FOUR, FIVE} o_t;

test_regress/t/t_math_signed_calc.v

@@ -29,7 +29,7 @@ module t (/*AUTOARG*/
 `endif
       if (out !== 'hfffe) $stop;
       $write("*-* All Finished *-*\n");
-      $finish; 
+      $finish;
    end
 
 endmodule
@@ -45,5 +45,3 @@ module Test(in0, in1, out);
 
   assign out = $signed({1'b0, in0}) * in1;      // this operator should be  signed multiplication
 endmodule
-
-

test_regress/t/t_order_dpi_export_1.v

@@ -33,4 +33,3 @@ module testbench;
    end
 
 endmodule
-

test_regress/t/t_order_dpi_export_2.v

@@ -40,4 +40,3 @@ module testbench(
    end
 
 endmodule
-

test_regress/t/t_order_dpi_export_3.v

@@ -53,4 +53,3 @@ module testbench(
    end
 
 endmodule
-

test_regress/t/t_order_dpi_export_4.v

@@ -55,4 +55,3 @@ module testbench(
    end
 
 endmodule
-

test_regress/t/t_order_dpi_export_5.v

@@ -43,4 +43,3 @@ module testbench(
    end
 
 endmodule
-

test_regress/t/t_param_in_func.v

@@ -127,4 +127,3 @@ function automatic logic [7:0] getType(logic[3:0] d);
                          {"9", "8", "7", "6", "5", "4", "3", "2", "1", "0"};
    return digits[d];
 endfunction
-

test_regress/t/t_profcfunc.gprof

@@ -2,8 +2,8 @@ Flat profile:
 
  Note all numbers below were faked for this test, so might not be consistent.
 
-  %   cumulative   self              self     total           
- time   seconds   seconds    calls  Ts/call  Ts/call  name    
+  %   cumulative   self              self     total
+ time   seconds   seconds    calls  Ts/call  Ts/call  name
   1.99      1.99     0.99   200578     0.00     0.00  VL_EXTENDS_QQ(int, int, unsigned long)
   1.98      0.00     0.98   100000     0.00     0.00  VL_POWSS_QQQ(int, int, int, unsigned long, unsigned long, bool, bool)
   1.89      0.00     0.89     1407     0.00     0.00  Verilated::debug()
@@ -41,4 +41,3 @@ Flat profile:
   1.25      0.00     0.25        3     0.00     0.00  unsigned long const& std::max<unsigned long>(unsigned long const&, unsigned long const&)
   1.19      0.00     0.19        1     0.00     0.00  vl_finish(char const*, int, char const*)
   1.18      0.00     0.18        2     0.00     0.00  vl_time_pow10(int)
-

test_regress/t/t_split_var_5.pl

@@ -23,4 +23,3 @@ file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 0);
 file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 0);
 ok(1);
 1;
-

test_regress/t/t_sys_rand_concat.v

@@ -28,7 +28,7 @@ module t;
    initial begin
       for (int i = 0; i < `TRIES; ++i) begin
          // verilator lint_off WIDTH
-         // Optimize away extracts 
+         // Optimize away extracts
          b5a = {$random}[4:0];
          b5b = {$random}[14:10];
          // Optimize away concats
@@ -52,7 +52,7 @@ module t;
       `checkh(max_b7d, 7'h1f);
       `checkh(max_b60c, ~ 60'h0);
       `checkh(max_b90c, ~ 90'h0);
-      
+
       $write("*-* All Finished *-*\n");
       $finish;
    end

test_regress/t/t_sys_rand_seed.v

@@ -29,7 +29,7 @@ module t;
       valuec = $random(seedc);
       if (valuea == valueb && valueb == valuec) $stop;  // May false fail 1 in 1^64
       if (seeda == seedb && seedb == seedc) $stop;  // May false fail 1 in 1^64
-       
+
       valuea = $urandom(10);
       valueb = $urandom(10);
       if (valuea !== valueb) $stop;