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docs: Fix grammar.

This commit is contained in:
Wilson Snyder 2022-12-10 20:09:47 -05:00
parent a9ff0a0f32
commit b6cdae30f6
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16
bin/verilator
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@ -287,7 +287,7 @@ detailed descriptions of these arguments.
=for VL_SPHINX_EXTRACT "_build/gen/args_verilator.rst"
<file.v> Verilog package, module and top module filenames
<file.v> Verilog package, module, and top module filenames
<file.c/cc/cpp> Optional C++ files to compile in
<file.a/o/so> Optional C++ files to link in
@ -379,7 +379,7 @@ detailed descriptions of these arguments.
--MP Create phony dependency targets
+notimingchecks Ignored
-O0 Disable optimizations
-O3 High performance optimizations
-O3 High-performance optimizations
-O<optimization-letter> Selectable optimizations
-o <executable> Name of final executable
--no-order-clock-delay Disable ordering clock enable assignments
@ -387,14 +387,14 @@ detailed descriptions of these arguments.
--output-split-cfuncs <statements> Split model functions
--output-split-ctrace <statements> Split tracing functions
-P Disable line numbers and blanks with -E
--pins-bv <bits> Specify types for top level ports
--pins-sc-biguint Specify types for top level ports
--pins-sc-uint Specify types for top level ports
--pins-uint8 Specify types for top level ports
--pins-bv <bits> Specify types for top-level ports
--pins-sc-biguint Specify types for top-level ports
--pins-sc-uint Specify types for top-level ports
--pins-uint8 Specify types for top-level ports
--no-pins64 Don't use uint64_t's for 33-64 bit sigs
--pipe-filter <command> Filter all input through a script
--pp-comments Show preprocessor comments with -E
--prefix <topname> Name of top level class
--prefix <topname> Name of top-level class
--private Debugging; see docs
--prof-c Compile C++ code with profiling
--prof-cfuncs Name functions for profiling
@ -426,7 +426,7 @@ detailed descriptions of these arguments.
--timescale <timescale> Sets default timescale
--timescale-override <timescale> Overrides all timescales
--top <topname> Alias of --top-module
--top-module <topname> Name of top level input module
--top-module <topname> Name of top-level input module
--trace Enable waveform creation
--trace-coverage Enable tracing of coverage
--trace-depth <levels> Depth of tracing

5
ci/docker/run/README.rst
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@ -62,12 +62,11 @@ Internals
---------
The Dockerfile builds Verilator and removes the tree when completed to
reduce the image size. The entrypoint is set as a wrapper script
reduce the image size. The entrypoint is a wrapper script
(``verilator-wrap.sh``). That script 1. calls Verilator, and 2. copies the
Verilated runtime files to the ``obj_dir`` or the ``-Mdir``
respectively. This allows the user to have the files to they may later
build the C++ output with the matching runtime files. The wrapper also
patches the Verilated Makefile accordingly.
There is also a hook defined that is run by docker hub via automated
builds.
A hook is also defined and run by Docker Hub via automated builds.

29
docs/guide/contributors.rst
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@ -11,7 +11,7 @@ Authors
When possible, please instead report bugs at `Verilator Issues
<https://verilator.org/issues>`_.
Primary author is Wilson Snyder <wsnyder@wsnyder.org>.
The primary author is Wilson Snyder <wsnyder@wsnyder.org>.
Major concepts by Paul Wasson, Duane Galbi, John Coiner, Geza Lore, Yutetsu
Takatsukasa, and Jie Xu.
@ -22,18 +22,18 @@ Contributors
Many people have provided ideas and other assistance with Verilator.
Verilator is receiving major development support from the `CHIPS Alliance
<https://chipsalliance.org>`_, `Antmicro Ltd <https://antmicro.com>`_ and
`Shunyao CAD <https://shunyaocad.com>`_.
Verilator is receiving significant development support from the `CHIPS
Alliance <https://chipsalliance.org>`_, `Antmicro Ltd
<https://antmicro.com>`_ and `Shunyao CAD <https://shunyaocad.com>`_.
Previous major corporate sponsors of Verilator, by providing significant
contributions of time or funds included include: Atmel Corporation, Cavium
contributions of time or funds include: Atmel Corporation, Cavium
Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd.,
Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune
Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc.,
SiCortex Inc, and Shunyao CAD.
The people who have contributed major functionality are: Krzysztof
The contributors of major functionality are: Krzysztof
Bieganski, Byron Bradley, Jeremy Bennett, Lane Brooks, John Coiner, Duane
Galbi, Geza Lore, Todd Strader, Stefan Wallentowitz, Paul Wasson, Jie Xu,
and Wilson Snyder. Major testers included Jeff Dutton, Jonathon Donaldson,
@ -129,8 +129,9 @@ Jeff Winston, Joshua Wise, Clifford Wolf, Tobias Wolfel, Johan Wouters,
Paul Wright, Junyi Xi, Ding Xiaoliang, Jie Xu, Mandy Xu, Yinan Xu, Luke
Yang, Amir Yazdanbakhsh, Keyi Zhang, and Xi Zhang.
Thanks to them, and all those we've missed including above, or wished to
remain anonymous.
Thanks to them, and all those we've missed mentioning above, and to those
whom have wished to remain anonymous.
Historical Origins
==================
@ -140,10 +141,10 @@ Digital Equipment Corporation. The Verilog code that was converted to C
was then merged with a C-based CPU model of the Alpha processor and
simulated in a C-based environment called CCLI.
In 1995 Verilator started being also used for Multimedia and Network
Processor development inside Digital. Duane Galbi took over the active
development of Verilator, and added several performance enhancements. CCLI
was still being used as the shell.
In 1995 Verilator started being used for Multimedia and Network Processor
development inside Digital. Duane Galbi took over the active development
of Verilator, and added several performance enhancements, and CCLI was
still being used as the shell.
In 1998, through the efforts of existing DECies, mainly Duane Galbi,
Digital graciously agreed to release the source code. (Subject to the code
@ -168,5 +169,5 @@ fork/join, delay handling, DFG performance optimizations, and other
improvements.
Currently, various language features and performance enhancements are added
as the need arises, with a focus on getting to complete Universal
Verification Methodology (UVM, IEEE 1800.2-2017) support.
as the need arises, focusing on completing Universal Verification
Methodology (UVM, IEEE 1800.2-2017) support.

8
docs/guide/environment.rst
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@ -10,7 +10,7 @@ associated programs.
.. option:: LD_LIBRARY_PATH
A generic Linux/OS variable specifying what directories have shared
object (.so) files. This path should include SystemC and any other
object (.so) files. This path should include SystemC and other
shared objects needed at simulation runtime.
.. option:: MAKE
@ -54,14 +54,14 @@ associated programs.
.. option:: SYSTEMC_INCLUDE
If set, specifies the directory containing the systemc.h header file. If
not specified, it will come from a default optionally specified at
If set, specifies the directory containing the systemc.h header file.
If not specified, it will come from a default optionally specified at
configure time (before Verilator was compiled), or computed from
SYSTEMC/include.
.. option:: SYSTEMC_LIBDIR
If set, specifies the directory containing the libsystemc.a library. If
If set, specifies the directory containing the libsystemc.a library. If
not specified, it will come from a default optionally specified at
configure time (before Verilator was compiled), or computed from
SYSTEMC/lib-SYSTEMC_ARCH.

10
docs/guide/example_binary.rst
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@ -42,7 +42,7 @@ Breaking this command down:
#. :vlopt:`-Wall` so Verilator has stronger lint warnings
enabled.
#. An finally, :command:`our.v` which is our SystemVerilog design file.
#. An finally, :command:`our.v`, which is our SystemVerilog design file.
And now we run it:
@ -57,7 +57,7 @@ And we get as output:
Hello World
- our.v:2: Verilog $finish
Really, you're better off using a Makefile to run the steps for you so when
your source changes it will automatically run all of the appropriate steps.
To aid this Verilator can create a makefile dependency file. For examples
that do this see the :file:`examples` directory in the distribution.
You're better off using a Makefile to run the steps for you, so when your
source changes, it will automatically run all of the appropriate steps. To
aid this, Verilator can create a makefile dependency file. For examples
that do this, see the :file:`examples` directory in the distribution.

15
docs/guide/example_cc.rst
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@ -12,7 +12,7 @@ of what this C++ code is doing, see
.. include:: example_common_install.rst
Now, let's create an example Verilog, and C++ wrapper file:
Now, let's create an example Verilog and C++ wrapper file:
.. code-block:: bash
@ -39,7 +39,7 @@ Now, let's create an example Verilog, and C++ wrapper file:
}
EOF
Now we run Verilator on our little example.
Now we run Verilator on our little example;
.. code-block:: bash
@ -47,8 +47,7 @@ Now we run Verilator on our little example.
Breaking this command down:
#. :vlopt:`--cc` to get C++ output (versus e.g. SystemC
or only linting).
#. :vlopt:`--cc` to get C++ output (versus e.g., SystemC, or only linting).
#. :vlopt:`--exe`, along with our :command:`sim_main.cpp` wrapper file, so
the build will create an executable instead of only a library.
@ -89,7 +88,7 @@ And we get as output:
Hello World
- our.v:2: Verilog $finish
Really, you're better off using a Makefile to run the steps for you so when
your source changes it will automatically run all of the appropriate steps.
To aid this Verilator can create a makefile dependency file. For examples
that do this see the :file:`examples` directory in the distribution.
You're better off using a Makefile to run the steps for you, so when your
source changes, it will automatically run all of the appropriate steps. To
aid this, Verilator can create a makefile dependency file. For examples
that do this, see the :file:`examples` directory in the distribution.

503
docs/guide/exe_verilator.rst
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35
docs/guide/exe_verilator_coverage.rst
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@ -12,8 +12,8 @@ coverage points exist on the same source code line, additional lines will
be inserted to report the additional points.
Additional Verilog-XL-style standard arguments specify the search paths
necessary to find the source code that the coverage analysis was performed
on.
necessary to find the source code on which the coverage analysis was
performed.
To filter those items to be included in coverage, you may read
logs/coverage.dat into an editor and do a M-x keep-lines to include only
@ -24,7 +24,7 @@ statement to the appropriate statement block, or see
:option:`/*verilator&32;coverage_off*/`. This will remove the coverage
points after the model is re-Verilated.
For an overview of use of verilator_coverage, see :ref:`Coverage Analysis`.
For an overview of the use of verilator_coverage, see :ref:`Coverage Analysis`.
verilator_coverage Example Usage
@ -50,25 +50,25 @@ verilator_coverage Arguments
.. option:: <filename>
Specifies the input coverage data file. Multiple filenames may be provided
to read multiple inputs. If no data file is specified, by default
to read multiple inputs. If no data file is specified, by default,
"coverage.dat" will be read.
.. option:: --annotate <output_directory>
Specifies the directory name that source files with annotated coverage data
should be written to.
Specifies the directory name to which source files with annotated coverage
data should be written.
.. option:: --annotate-all
Specifies all files should be shown. By default, only those source files
which have low coverage are written to the output directory.
with low coverage are written to the output directory.
.. option:: --annotate-min <count>
Specifies if the coverage point does not include the count number of
coverage hits, then the coverage point will be considered above the
threshold, and the coverage report will put a "%" to indicate the coverage
is not sufficient. Defaults to 10.
is insufficient. Defaults to 10.
.. option:: --help
@ -78,12 +78,12 @@ Displays a help summary, the program version, and exits.
Prints an experimental report listing the relative importance of each test
in covering all of the coverage points. The report shows "Covered" which
indicates the number of points that test covers; a test is considered to
indicates the number of points the test covers; a test is considered to
cover a point if it has a bucket count of at least 1. The "rank" column has
a higher number t indicate the test is more important, and rank 0 means the
a higher number t indicate the test is more critical, and rank 0 means the
test does not need to be run to cover the points. "RankPts" indicates the
number of coverage points this test will contribute to overall coverage if
all tests are run in the order of highest to lowest rank.
all tests are run in the order of highest to the lowest rank.
.. option:: --unlink
@ -98,8 +98,8 @@ Displays program version and exits.
Specifies the aggregate coverage results, summed across all the files,
should be written to the given filename in verilator_coverage data format.
This is useful for use in scripts to combine many coverage data files
(likely generated from random test runs) into one master coverage file.
This is useful in scripts to combine many coverage data files (likely
generated from random test runs) into one master coverage file.
.. option:: --write-info <filename.info>
@ -108,7 +108,8 @@ should be written to the given filename in :command:`lcov` .info format.
This may be used to feed into :command:`lcov` to aggregate or generate
reports.
The info format loses data compared to the Verilator coverage data format;
the info will all forms of coverage converted to line style coverage, and
if there are multiple coverage points on a single line, the minimum
coverage across those points will be used to report coverage of the line.
Converting from the Verilator coverage data format to the info format is
lossy; the info will have all forms of coverage merged line coverage, and
if there are multiple coverage points on a single line they will merge.
The minimum coverage across all merged points will be used to report
coverage of the line.

23
docs/guide/exe_verilator_gantt.rst
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@ -5,16 +5,16 @@ verilator_gantt
===============
Verilator_gantt creates a visual representation to help analyze Verilator
multithreaded simulation performance, by showing when each macro-task
starts and ends, and showing when each thread is busy or idle.
multithreaded simulation performance by showing when each macro-task
starts, ends, and when each thread is busy or idle.
For an overview of use of verilator_gantt, see :ref:`Profiling`.
For an overview of the use of verilator_gantt, see :ref:`Profiling`.
Gantt Chart VCD
---------------
Verilated_gantt creates a value change dump (VCD) format dump file which
may be viewed in a waveform viewer (e.g. C<GTKWave>):
may be viewed in a waveform viewer (e.g., C<GTKWave>):
.. figure:: figures/fig_gantt_min.png
@ -27,9 +27,8 @@ time tick of the system's high-performance counter.
Gantt Chart VCD Signals
-----------------------
In waveforms there are the following signals. In GTKWave, using a data
format of "decimal" will remove the leading zeros and make the traces
easier to read.
In waveforms, there are the following signals. In GTKWave, use "decimal"
data format to remove the leading zeros and make the traces easier to read.
evals
Increments each time when eval_step was measured to be active. This
@ -37,12 +36,12 @@ evals
eval_loop
Increments each time when the evaluation loop within eval_step was
measured to be active. For best performance there is only a single
evaluation loop within each eval_step call, that is the eval_loop
measured to be active. For best performance, there is only a single
evaluation loop within each eval_step call; that is, the eval_loop
waveform looks identical to the evals waveform.
measured_parallelism
The number of mtasks active at this time, for best performance this will
The number of mtasks active at this time, for best performance, this will
match the thread count. In GTKWave, use a data format of "analog step" to
view this signal.
@ -72,7 +71,7 @@ verilator_gantt Arguments
.. option:: <filename>
The filename to read data from, defaults to "profile_exec.dat".
The filename to read data from; the default is "profile_exec.dat".
.. option:: --help
@ -84,4 +83,4 @@ Disables creating a .vcd file.
.. option:: --vcd <filename>
Sets the output filename for vcd dump. Default is "verilator_gantt.vcd".
Sets the output filename for vcd dump; the default is "verilator_gantt.vcd".

8
docs/guide/exe_verilator_profcfunc.rst
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@ -6,14 +6,14 @@ verilator_profcfunc
Verilator_profcfunc reads a profile report created by gprof. The names of
the functions are then transformed, assuming the user used Verilator's
--prof-cfuncs, and a report printed showing the percentage of time, etc, in
each Verilog block.
--prof-cfuncs, and a report printed showing the percentage of the time,
etc., in each Verilog block.
Due to rounding errors in gprof reports, the input report's percentages may
not total to 100%. In the verilator_profcfunc report this will get
not total 100%. In the verilator_profcfunc report this will get
reported as a rounding error.
For an overview of use of verilator_profcfunc, see :ref:`Profiling`.
For an overview of the use of verilator_profcfunc, see :ref:`Profiling`.
verilator_profcfunc Arguments
-----------------------------

157
docs/guide/extensions.rst
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@ -12,14 +12,14 @@ or "`ifdef`"'s may break other tools.
.. option:: `__FILE__
The :option:`\`__FILE__` define expands to the current filename as a
string, like C++'s __FILE__. This Verilator feature added in 2006 was
incorporated into the IEEE 1800-2009 standard.
string, like C++'s __FILE__. This Verilator feature, added in 2006, was
incorporated into IEEE 1800-2009.
.. option:: `__LINE__
The :option:`\`__LINE__` define expands to the current filename as a
string, like C++'s __LINE__. This Verilator feature added in 2006 was
incorporated into the IEEE 1800-2009 standard.
incorporated into IEEE 1800-2009.
.. option:: `error [string]
@ -27,7 +27,7 @@ or "`ifdef`"'s may break other tools.
.. option:: """ [string] """
A triple-quoted block specifies a string which may include newlines and
A triple-quoted block specifies a string that may include newlines and
single quotes. This extension is experimental and may be removed
without deprecation.
@ -51,24 +51,24 @@ or "`ifdef`"'s may break other tools.
rather than hard-coding variable names in the string
:code:`$c("func(a)")`, instead pass the variable as an expression
::code:`$c("func(",a,")")`. This will allow the call to work inside
Verilog functions where the variable is flattened out, and also enable
other optimizations.
Verilog functions where the variable is flattened out and enable other
optimizations.
Verilator does not use any text inside the quotes for
ordering/scheduling. If you need the $c to be called at a specific
time, e.g. when a variable changes, then the $c must be under an
appropriate sensitivity statement, e.g.
:code:`always @(posedge clk) $c("func()")` to call it on every edge, or
e.g. :code:`always @* c("func(",a,")")` to call it when :code:`a`
time, e.g., when a variable changes, then the $c must be under an
appropriate sensitivity statement, e.g.,
:code:`always @(posedge clk) $c("func()")` to call it on every edge, or,
e.g., :code:`always @* c("func(",a,")")` to call it when :code:`a`
changes (the latter working because :code:`a` is outside the quotes).
If you will be reading or writing any Verilog variables inside the C++
functions, the Verilog signals must be declared with
:option:`/*verilator&32;public*/` metacomments.
You may also append an arbitrary number to $c, generally the width of
the output; :code:`signal_32_bits = $c32("...");`. This allows for
compatibility with other simulators which require a differently named
You may also append a number to $c, which specifies the bit width of
the output, e.g., :code:`signal_32_bits = $c32("...");`. This allows for
compatibility with other simulators, which require a differently named
PLI function name for each different output width.
.. option:: $display, $write, $fdisplay, $fwrite, $sformat, $swrite
@ -76,8 +76,8 @@ or "`ifdef`"'s may break other tools.
Format arguments may use C fprintf sizes after the % escape. Per the
Verilog standard, %x prints a number with the natural width, and %0x
prints a number with minimum width. Verilator extends this so %5x
prints 5 digits per the C standard (this is unspecified in Verilog, but
was incorporated into the 1800-2009).
prints 5 digits per the C standard. This extension was standardized into
1800-2009.
.. option:: $timeprecision
@ -92,55 +92,55 @@ or "`ifdef`"'s may break other tools.
.. option:: `coverage_block_off
Specifies the entire begin/end block should be ignored for coverage
analysis. Must be inside a code block, e.g. within a begin/end pair.
analysis. Must be inside a code block, e.g., within a begin/end pair.
Same as :option:`coverage_block_off` in :ref:`Configuration Files`.
.. option:: `systemc_header
Take remaining text up to the next :option:`\`verilog` or
Take the remaining text up to the next :option:`\`verilog` or
:option:`\`systemc_... <\`systemc_header>` mode switch and place it
verbatim into the output .h file's header. Must be placed as a module
item, e.g. directly inside a module/endmodule pair. Despite the name of
item, e.g., directly inside a module/endmodule pair. Despite the name of
this macro, this also works in pure C++ code.
.. option:: `systemc_ctor
Take remaining text up to the next :option:`\`verilog` or
Take the remaining text up to the next :option:`\`verilog` or
:option:`\`systemc_... <\`systemc_header>` mode switch and place it
verbatim into the C++ class constructor. Must be placed as a module
item, e.g. directly inside a module/endmodule pair. Despite the name of
item, e.g., directly inside a module/endmodule pair. Despite the name of
this macro, this also works in pure C++ code.
.. option:: `systemc_dtor
Take remaining text up to the next :option:`\`verilog` or
Take the remaining text up to the next :option:`\`verilog` or
:option:`\`systemc_... <\`systemc_header>` mode switch and place it
verbatim into the C++ class destructor. Must be placed as a module
item, e.g. directly inside a module/endmodule pair. Despite the name of
item, e.g., directly inside a module/endmodule pair. Despite the name of
this macro, this also works in pure C++ code.
.. option:: `systemc_interface
Take remaining text up to the next :option:`\`verilog` or
Take the remaining text up to the next :option:`\`verilog` or
:option:`\`systemc_... <\`systemc_header>` mode switch and place it
verbatim into the C++ class interface. Must be placed as a module item,
e.g. directly inside a module/endmodule pair. Despite the name of this
e.g., directly inside a module/endmodule pair. Despite the name of this
macro, this also works in pure C++ code.
.. option:: `systemc_imp_header
Take remaining text up to the next :option:`\`verilog` or
Take the remaining text up to the next :option:`\`verilog` or
:option:`\`systemc_... <\`systemc_header>` mode switch and place it
verbatim into the header of all files for this C++ class implementation.
Must be placed as a module item, e.g. directly inside a module/endmodule
Must be placed as a module item, e.g., directly inside a module/endmodule
pair. Despite the name of this macro, this also works in pure C++ code.
.. option:: `systemc_implementation
Take remaining text up to the next :option:`\`verilog` or
Take the remaining text up to the next :option:`\`verilog` or
:option:`\`systemc_... <\`systemc_header>` mode switch and place it
verbatim into a single file of the C++ class implementation. Must be
placed as a module item, e.g. directly inside a module/endmodule
placed as a module item, e.g., directly inside a module/endmodule
pair. Despite the name of this macro, this also works in pure C++ code.
If you will be reading or writing any Verilog variables in the C++
@ -150,7 +150,7 @@ or "`ifdef`"'s may break other tools.
.. option:: `SYSTEMVERILOG
The SYSTEMVERILOG, SV_COV_START and related standard defines are set by
The SYSTEMVERILOG, SV_COV_START, and related standard defines are set by
default when :vlopt:`--language <--language>` is "1800-\*".
.. option:: `VERILATOR
@ -164,13 +164,13 @@ or "`ifdef`"'s may break other tools.
.. option:: `verilator_config
Take remaining text up to the next :option:`\`verilog` mode switch and
Take the remaining text up to the next :option:`\`verilog` mode switch and
treat it as Verilator configuration commands. See :ref:`Configuration Files`.
.. option:: `VERILATOR_TIMING
The VERILATOR_TIMING define is set when :vlopt:`--timing` is used to
allow an "\`ifdef" of code dependent on this feature. Note this define
allow an "\`ifdef" of code dependent on this feature. Note that this define
is not affected by the :option:`timing_off` configuration file option
nor timing metacomments.
@ -185,10 +185,10 @@ or "`ifdef`"'s may break other tools.
Deprecated and has no effect (ignored).
In versions prior to 5.000:
In versions before 5.000:
Used after a signal declaration to indicate the signal is used to gate a
clock, and the user takes responsibility for insuring there are no races
clock, and the user is responsible for ensuring there are no races
related to it. (Typically by adding a latch, and running static timing
analysis.) For example:
@ -209,7 +209,7 @@ or "`ifdef`"'s may break other tools.
.. option:: /*verilator&32;no_clocker*/
Specifies that the signal is used as clock or not. See :vlopt:`--clk`.
Specifies whether the signal is used as clock or not. See :vlopt:`--clk`.
Same as :option:`clocker` and :option:`no_clocker` in configuration
files.
@ -223,12 +223,12 @@ or "`ifdef`"'s may break other tools.
.. option:: /*verilator&32;coverage_off*/
Specifies that following lines of code should have coverage disabled.
Specifies that that following lines of code should have coverage disabled.
Often used to ignore an entire module for coverage analysis purposes.
.. option:: /*verilator&32;coverage_on*/
Specifies that following lines of code should have coverage re-enabled
Specifies that that following lines of code should have coverage re-enabled
(if appropriate :vlopt:`--coverage` flags are passed) after being
disabled earlier with :option:`/*verilator&32;coverage_off*/`.
@ -236,7 +236,7 @@ or "`ifdef`"'s may break other tools.
Specifies that the signal (net or variable) should be made forceable from
C++ code by generating public `<signame>__VforceEn` and
`<signame>__VforceVal` signals The force control signals are created as
`<signame>__VforceVal` signals. The force control signals are created as
:option:`public_flat` signals.
To force a marked signal from C++, set the corresponding `__VforceVal`
@ -251,7 +251,7 @@ or "`ifdef`"'s may break other tools.
.. option:: /*verilator&32;hier_block*/
Specifies that the module is an unit of hierarchical Verilation. This
Specifies that the module is a unit of hierarchical Verilation. This
metacomment must be between :code:`module module_name(...);` and
:code:`endmodule`. The module will not be inlined nor uniquified for
each instance in hierarchical Verilation. Note that the metacomment is
@ -272,10 +272,10 @@ or "`ifdef`"'s may break other tools.
.. option:: /*verilator&32;isolate_assignments*/
Used after a signal declaration to indicate the assignments to this
signal in any blocks should be isolated into new blocks. When there is
a large combinatorial block that is resulting in an ``UNOPTFLAT``
warning, attaching this to the signal causing a false loop may clear up
the problem.
signal in any blocks should be isolated into new blocks. When large
combinatorial block results in a :option:`UNOPTFLAT` warning, attaching
this to the signal that was causing a false loop may work around the
warning.
IE, with the following:
@ -329,7 +329,7 @@ or "`ifdef`"'s may break other tools.
.. option:: /*verilator&32;lint_save*/
Push the current state of what lint messages are turned on or turned off
Push the current state of what lint messages are turned on or off
to a stack. Later meta-comments may then lint_on or lint_off specific
messages, then return to the earlier message state by using
:code:`/*verilator&32;lint_restore*/`. For example:
@ -341,8 +341,8 @@ or "`ifdef`"'s may break other tools.
... // code needing WIDTH turned off
// verilator lint_restore
If WIDTH was on before the lint_off, it will now be restored to on, and
if it was off before the lint_off it will remain off.
If WIDTH was on before the lint_off, it would now be restored to on, and
if it was off before the lint_off it would remain off.
.. option:: /*verilator&32;no_inline_module*/
@ -386,13 +386,12 @@ or "`ifdef`"'s may break other tools.
Used after an input, output, register, or wire declaration to indicate
the signal should be declared so that C code may read or write the value
of the signal. This will also declare this module public, otherwise use
of the signal. This will also declare this module public; otherwise, use
:code:`/*verilator&32;public_flat*/`.
Instead of using public variables, consider instead making a DPI or
public function that accesses the variable. This is nicer as it
provides an obvious entry point that is also compatible across
simulators.
Instead of using public variables, consider making a DPI or public
function that accesses the variable. This is nicer as it provides an
obvious entry point compatible across simulators.
Same as :option:`public` configuration file option.
@ -402,7 +401,7 @@ or "`ifdef`"'s may break other tools.
indicate the function or task should be made into a C++ function, public
to outside callers. Public tasks will be declared as a void C++
function, public functions will get the appropriate non-void (bool,
uint32_t, etc) return type. Any input arguments will become C++
uint32_t, etc.) return type. Any input arguments will become C++
arguments to the function. Any output arguments will become C++
reference arguments. Any local registers/integers will become function
automatic variables on the stack.
@ -440,10 +439,10 @@ or "`ifdef`"'s may break other tools.
.. option:: /*verilator&32;public_flat_rw @(<edge_list>)*/ (on variable)
Used after an input, output, register, or wire declaration to indicate
the signal should be declared public_flat_rd (see above), and also
writable, where writes should be considered to have the timing specified
by the given sensitivity edge list. Set for all variables, ports and
wires using the :vlopt:`--public-flat-rw` option.
the signal should be declared public_flat_rd (see above), and writable,
where writes should be considered to have the timing specified by the
given sensitivity edge list. Use of this is implied when using the
:vlopt:`--public-flat-rw` option.
Same as :option:`public_flat_rw` configuration file option.
@ -452,8 +451,8 @@ or "`ifdef`"'s may break other tools.
Used after a module statement to indicate the module should not be
inlined (unless specifically requested) so that C code may access the
module. Verilator automatically sets this attribute when the module
contains any public signals or \`systemc_ directives. Also set for all
modules when using the :vlopt:`--public` option.
contains public signals or \`systemc_ directives. Use of this is
implied when using the :vlopt:`--public` option.
Same as :option:`public` configuration file option.
@ -462,27 +461,26 @@ or "`ifdef`"'s may break other tools.
Deprecated and ignored. Previously used after an input declaration to
indicate the signal should be declared in SystemC as a sc_clock instead
of a bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0
and later do not require clock pins to be sc_clocks and this is no
and later do not require clock pins to be sc_clocks, and this is no
longer needed and is ignored.
.. option:: /*verilator&32;sc_bv*/
Used after a port declaration. It sets the port to be of
:code:`sc_bv<{width}>` type, instead of bool, uint32_t or uint64_t.
:code:`sc_bv<{width}>` type, instead of bool, uint32_t, or uint64_t.
This may be useful if the port width is parameterized and the
instantiating C++ code wants to always have a sc_bv so it can accept any
width. In general you should avoid using this attribute when not
necessary as with increasing usage of sc_bv the performance decreases
significantly.
instantiating C++ code always wants to have a sc_bv accept any width.
In general, you should avoid using this attribute when unnecessary, as
the performance decreases significantly with increasing usage of sc_bv.
Same as :option:`sc_bv` configuration file option.
.. option:: /*verilator&32;sformat*/
Attached to the final argument of type "input string" of a function or
task to indicate the function or task should pass all remaining
task to indicate that the function or task should pass all remaining
arguments through $sformatf. This allows creation of DPI functions with
$display like behavior. See the :file:`test_regress/t/t_dpi_display.v`
$display-like behavior. See the :file:`test_regress/t/t_dpi_display.v`
file for an example.
Same as :option:`sformat` configuration file option.
@ -492,7 +490,7 @@ or "`ifdef`"'s may break other tools.
Attached to a variable or a net declaration to break the variable into
multiple pieces typically to resolve ``UNOPTFLAT`` performance issues.
Typically the variables to attach this to are recommended by Verilator
itself, see :option:`UNOPTFLAT`.
itself; see :option:`UNOPTFLAT`.
For example, Verilator will internally convert a variable with the
metacomment such as:
@ -509,12 +507,12 @@ or "`ifdef`"'s may break other tools.
logic [7:0] x__BRA__1__KET__ /*verilator split_var*/;
Note that the generated packed variables retain the split_var
metacomment because they may be split into further smaller pieces
according to the access patterns.
metacomment because they may be split into smaller pieces according to
the access patterns.
This only supports unpacked arrays, packed arrays, and packed structs of
integer types (reg, logic, bit, byte, int...); otherwise if a split was
requested but cannot occur a SPLITVAR warning is issued. Splitting
integer types (reg, logic, bit, byte, int...); otherwise, if a split was
requested but cannot occur, a SPLITVAR warning is issued. Splitting
large arrays may slow down the Verilation speed, so use this only on
variables that require it.
@ -551,10 +549,10 @@ or "`ifdef`"'s may break other tools.
.. option:: /*verilator&32;tracing_off*/
Disable waveform tracing for all future signals that are declared in
this module, or instances below this module. Often this is placed just
after a primitive's module statement, so that the entire module and
instances below it are not traced.
Disable waveform tracing for all future signals declared in this module,
or instances below this module. Often this is placed just after a
primitive's module statement, so that the entire module and instances
below it are not traced.
.. option:: /*verilator&32;tracing_on*/
@ -565,9 +563,8 @@ or "`ifdef`"'s may break other tools.
Called as a task, print a stack trace. Called as a function, return a
string with a stack trace. This relies on the C++ system trace, which
may give less meaningful results if the model was not compiled with
debug symbols. Also the data represents the C++ stack, the
SystemVerilog functions/tasks involved may be renamed and/or inlined
before becoming the C++ functions that may be visible in the stack
trace. This extension is experimental and may be removed without
deprecation.
may give less meaningful results if the model is not compiled with debug
symbols. Also, the data represents the C++ stack; the SystemVerilog
functions/tasks involved may be renamed and/or inlined before becoming
the C++ functions that may be visible in the stack trace. This
extension is experimental and may be removed without deprecation.

156
docs/guide/faq.rst
View File

@ -14,8 +14,8 @@ Can I contribute?
"""""""""""""""""
Please contribute! Just submit a pull request, or raise an issue to
discuss if looking for something to help on. For more information see our
contributor agreement.
discuss if you are looking for something to help on. For more information
see our contributor agreement.
How widely is Verilator used?
@ -24,7 +24,7 @@ How widely is Verilator used?
Verilator is used by many of the largest silicon design companies, large
organizations such as CERN, and even by college student projects.
Verilator is one of the "big 4" simulators, meaning one of the 4 main
Verilator is one of the "big 4" simulators, meaning one of the four leading
SystemVerilog simulators available, namely the closed-source products Synopsys
VCS (tm), Mentor Questa/ModelSim (tm), Cadence
Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator.
@ -35,8 +35,8 @@ simulators.
Does Verilator run under Windows?
"""""""""""""""""""""""""""""""""
Yes, ideally run Ubuntu under Windows Subsystem for Linux (WSL2).
Alternatively use Cygwin, though this tends to be slower and is not
Yes, ideally, run Ubuntu under Windows Subsystem for Linux (WSL2).
Alternatively, use Cygwin, though this tends to be slower and is not
regularly tested. Verilated output also compiles under Microsoft Visual
C++, but this is also not regularly tested.
@ -58,14 +58,14 @@ How can it be faster than (name-a-big-3-closed-source-simulator)?
Generally, the implied part of the question is "... with all of the
manpower they can put into developing it."
Most simulators have to be compliant with the complete IEEE 1364 (Verilog)
and IEEE 1800 (SystemVerilog) standards, meaning they have to be event
driven. This prevents them from being able to reorder blocks and make
netlist-style optimizations, which are where most of the gains come from.
Most simulators must comply with the complete IEEE 1364 (Verilog) and IEEE
1800 (SystemVerilog) standards, meaning they have to be event-driven. This
prevents them from being able to reorder blocks and make netlist-style
optimizations, which are where most of the gains come from.
You should not be scared by non-compliance. Your synthesis tool isn't
compliant with the whole standard to start with, so your simulator need not
be either. Verilator is closer to the synthesis interpretation, so this is
be either. Verilator is closer to the synthesis interpretation, which is
a good thing for getting working silicon.
@ -81,17 +81,17 @@ the licenses for details.
Some examples:
* Any SystemVerilog or other input fed into Verilator remain your own.
* Any SystemVerilog or other input fed into Verilator remains your own.
* Any of your VPI/DPI C++ routines that Verilator calls remain your own.
* Any of your main() C++ code that calls into Verilator remain your own.
* Any of your main() C++ code that calls into Verilator remains your own.
* If you change Verilator itself, for example changing or adding a file
* If you change Verilator itself, for example, changing or adding a file
under the src/ directory in the repository, you must make the source code
available under the GNU Lesser Public License.
* If you change a header Verilator provides, for example under include/ in
* If you change a header Verilator provides, for example, under include/ in
the repository, you must make the source code available under the GNU
Lesser Public License.
@ -101,9 +101,9 @@ license also allows you to modify Verilator for internal use without
distributing the modified version. But please contribute back to the
community!
Under both license you can offer a commercial product that is based on
Verilator either directly or embedded within. However under both licenses,
any changes you make to Verilator for such a product must be open sourced.
Under both licenses, you can offer a commercial product based on
Verilator directly or embedded within. However, under both licenses,
any changes you make to Verilator for such a product must be open-sourced.
As is standard with Open Source, contributions back to Verilator will be
placed under the Verilator copyright and LGPL/Artistic license. Small test
@ -114,11 +114,11 @@ and large tests under the LGPL/Artistic, unless requested otherwise.
Why is running Verilator (to create a model) so slow?
"""""""""""""""""""""""""""""""""""""""""""""""""""""
Verilator may require more memory than the resulting simulator will
require, as Verilator internally creates all of the state of the resulting
generated simulator in order to optimize it. If it takes more than a few
Verilator may require more memory than the resulting simulation,
as Verilator internally creates all of the state of the resulting
generated simulator to optimize it. If it takes more than a few
minutes or so (and you're not using :vlopt:`--debug` since debug mode is
disk bound), see if your machine is paging; most likely you need to run it
disk bound), see if your machine is paging; most likely, you need to run it
on a machine with more memory. Very large designs are known to have topped
64 GB resident set size. Alternatively, see :ref:`Hierarchical Verilation`.
@ -128,14 +128,14 @@ How do I generate waveforms (traces) in C++?
See also the next question for tracing in SystemC mode.
A. Pass the :vlopt:`--trace` option to Verilator, and in your top level C
A. Pass the :vlopt:`--trace` option to Verilator, and in your top-level C
code, call ``Verilated::traceEverOn(true)``. Then you may use
``$dumpfile`` and ``$dumpvars`` to enable traces, same as with any
``$dumpfile`` and ``$dumpvars`` to enable traces, the same as with any
Verilog simulator. See ``examples/make_tracing_c`` in the distribution.
B. Or, for finer-grained control, or C++ files with multiple Verilated
modules you may also create the trace purely from C++. Create a
VerilatedVcdC object, and in your main loop right after ``eval()`` call
modules, you may also create the trace purely from C++. Create a
VerilatedVcdC object, and in your main loop, right after ``eval()`` call
``trace_object->dump(contextp->time())`` every time step, and finally
call ``trace_object->close()``.
@ -163,8 +163,8 @@ B. Or, for finer-grained control, or C++ files with multiple Verilated
You also need to compile :file:`verilated_vcd_c.cpp` and add it to your
link, preferably by adding the dependencies in your Makefile's
:code:`$(VK_GLOBAL_OBJS)` link rule. This is done for you if using the
Verilator :vlopt:`--exe` option.
:code:`$(VK_GLOBAL_OBJS)` link rule. This is done for you if you are using
the Verilator :vlopt:`--binary` or :vlopt:`--exe` option.
you can call :code:`trace_object->trace()` on multiple Verilated objects
with the same trace file if you want all data to land in the same output
@ -174,22 +174,22 @@ file.
How do I generate waveforms (traces) in SystemC?
""""""""""""""""""""""""""""""""""""""""""""""""
A. Pass the :vlopt:`--trace` option to Verilator, and in your top level
A. Pass the :vlopt:`--trace` option to Verilator, and in your top-level
:code:`sc_main()`, call :code:`Verilated::traceEverOn(true)`. Then you
may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, same as
with any Verilog simulator, see the non-SystemC example in
may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, as
with any Verilog simulator; see the non-SystemC example in
:file:`examples/make_tracing_c`. This will trace only the module
containing the :code:`$dumpvar`.
B. Or, you may create a trace purely from SystemC, which may trace all
Verilated designs in the SystemC model. Create a VerilatedVcdSc object
as you would create a normal SystemC trace file. For an example, see
as you would create a standard SystemC trace file. For an example, see
the call to ``VerilatedVcdSc`` in the
:file:`examples/make_tracing_sc/sc_main.cpp` file of the distribution,
and below.
C. Alternatively you may use the C++ trace mechanism described in the
previous question, note the timescale and timeprecision will be
C. Alternatively, you may use the C++ trace mechanism described in the
previous question; note that the timescale and timeprecision will be
inherited from your SystemC settings.
.. code-block:: C++
@ -214,13 +214,14 @@ C. Alternatively you may use the C++ trace mechanism described in the
You also need to compile :file:`verilated_vcd_sc.cpp` and
:file:`verilated_vcd_c.cpp` and add them to your link, preferably by adding
the dependencies in your Makefile's :code:`$(VK_GLOBAL_OBJS)` link rule.
This is done for you if using the Verilator :vlopt:`--exe` option.
This is done for you if you are using the Verilator :vlopt:`--binary` or
:vlopt:`--exe` option.
You can call :code:`->trace()` on multiple Verilated objects with the same
trace file if you want all data to land in the same output file.
When using SystemC 2.3, the SystemC library must have been built with the
experimental simulation phase callback based tracing disabled. This is
experimental simulation phase callback-based tracing disabled. This is
disabled by default when building SystemC with its configure based build
system, but when building SystemC with CMake, you must pass
``-DENABLE_PHASE_CALLBACKS_TRACING=OFF`` to disable this feature.
@ -242,7 +243,7 @@ Or, in C++ change the include described in the VCD example above:
VerilatedFstC* tfp = new VerilatedFstC;
Or, in SystemC change the include described in the VCD example above:
Or, in SystemC, change the include described in the VCD example above:
.. code-block:: C++
@ -250,17 +251,16 @@ Or, in SystemC change the include described in the VCD example above:
VerilatedFstC* tfp = new VerilatedFstSc;
Note that currently supporting both FST and VCD in a single simulation is
impossible, but such requirement should be rare. You can however ifdef
around the trace format in your C++ main loop, and select VCD or FST at
build time, should you require.
Currently, supporting FST and VCD in a single simulation is impossible, but
such requirement should be rare. You can however ifdef around the trace
format in your C++ main loop, and select VCD or FST at compile time.
How do I view waveforms (aka dumps or traces)?
""""""""""""""""""""""""""""""""""""""""""""""
Verilator creates standard VCD (Value Change Dump) and FST files. VCD
files are viewable with the open source GTKWave (recommended) or Dinotrace
files are viewable with the open-source GTKWave (recommended), or Dinotrace
(legacy) programs, or any of the many closed-source offerings; FST is
supported only by GTKWave.
@ -273,20 +273,20 @@ A. Instead of calling ``VerilatedVcdC->open`` or ``$dumpvars`` at the
tracing to begin.
B. Add the :option:`/*verilator&32;tracing_off*/` metacomment to any very
low level modules you never want to trace (such as perhaps library
low-level modules you never want to trace (such as perhaps library
cells).
C. Use the :vlopt:`--trace-depth` option to limit the depth of tracing, for
example :vlopt:`--trace-depth 1 <--trace-depth>` to see only the top
level signals.
C. Use the :vlopt:`--trace-depth` option to limit the tracing depth, for
example :vlopt:`--trace-depth 1 <--trace-depth>` to see only the
top-level signals.
D. You can also consider using FST tracing instead of VCD. FST dumps are a
fraction of the size of the equivalent VCD. FST tracing can be slower
than VCD tracing, but it might be the only option if the VCD file size
is prohibitively large.
E. Be sure you write your trace files to a local solid-state drive, instead
of to a network drive. Network drives are generally far slower.
E. Write your trace files to a machine-local solid-state drive instead of a
network drive. Network drives are generally far slower.
Where is the translate_off command? (How do I ignore a construct?)
@ -313,7 +313,7 @@ Why do I get "unexpected 'do'" or "unexpected 'bit'" errors?
The words \ ``do``\ , \ ``bit``\ , \ ``ref``\ , \ ``return``\ , and others
are reserved keywords in SystemVerilog. Older Verilog code might use these
as identifiers. You should change your code to not use them to ensure it
as identifiers, and you should change your code to not use them to ensure it
works with newer tools. Alternatively, surround them by the Verilog
2005/SystemVerilog begin_keywords pragma to indicate Verilog 2001 code.
@ -325,7 +325,7 @@ works with newer tools. Alternatively, surround them by the Verilog
`end_keywords
If you want the whole design to be parsed as Verilog 2001, see the
If you want the whole design parsed as Verilog 2001, see the
:vlopt:`--default-language` option.
@ -342,11 +342,11 @@ Why do I get "undefined reference to sc_time_stamp()?
In Verilator 4.200 and later, using the timeInc function is recommended
instead. See the :ref:`Connecting to C++` examples. Some linkers (MSVC++)
still require :code:`sc_time_stamp()` to be defined, either define this
still require :code:`sc_time_stamp()` to be defined; either define this
with :code:`double sc_time_stamp() { return 0; }` or compile the Verilated
code with :code:`-CFLAGS -DVL_TIME_CONTEXT`.
Prior to Verilator 4.200, the :code:`sc_time_stamp()` function needs to be
Before Verilator 4.200, the :code:`sc_time_stamp()` function needs to be
defined in C++ (non SystemC) to return the current simulation time.
@ -369,17 +369,17 @@ also use the "import DPI" SystemVerilog feature to call C code (see the
chapter above). There is also limited VPI access to public signals.
If you want something more complex, since Verilator emits standard C++
code, you can write your own C++ routines that can access and modify signal
code, you can write C++ routines that can access and modify signal
values without needing any PLI interface code, and call it with
$c("{any_c++_statement}").
See the :ref:`Connecting` section.
How do I make a Verilog module that contain a C++ object?
"""""""""""""""""""""""""""""""""""""""""""""""""""""""""
How do I make a Verilog module that contains a C++ object?
""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
You need to add the object to the structure that Verilator creates, then
You need to add the object to the structure Verilator creates, then
use $c to call a method inside your object. The
:file:`test_regress/t/t_extend_class` files in the distribution show an
example of how to do this.
@ -388,9 +388,9 @@ example of how to do this.
How do I get faster build times?
""""""""""""""""""""""""""""""""
* When running make, pass the make variable VM_PARALLEL_BUILDS=1 so that
* When running make, pass the make variable VM_PARALLEL_BUILDS=1, so that
builds occur in parallel. Note this is now set by default if an output
file was large enough to be split due to the :vlopt:`--output-split`
file is large enough to be split due to the :vlopt:`--output-split`
option.
* Verilator emits any infrequently executed "cold" routines into separate
@ -401,17 +401,17 @@ How do I get faster build times?
* Use a recent compiler. Newer compilers tend to be faster.
* Compile in parallel on many machines and use caching; see the web for the
ccache, distcc and icecream packages. ccache will skip GCC runs between
ccache, distcc, and icecream packages. ccache will skip GCC runs between
identical source builds, even across different users. If ccache was
installed when Verilator was built it is used, or see OBJCACHE
installed when Verilator was built, it is used, or see OBJCACHE
environment variable to override this. Also see the
:vlopt:`--output-split` option and :ref: `Profiling ccache efficiency`
:vlopt:`--output-split` option and :ref: `Profiling ccache efficiency`.
* To reduce the compile time of classes that use a Verilated module (e.g. a
* To reduce the compile time of classes that use a Verilated module (e.g., a
top CPP file) you may wish to add a
:option:`/*verilator&32;no_inline_module*/` metacomment to your top level
:option:`/*verilator&32;no_inline_module*/` metacomment to your top-level
module. This will decrease the amount of code in the model's Verilated
class, improving compile times of any instantiating top level C++ code,
class, improving compile times of any instantiating top-level C++ code,
at a relatively small cost of execution performance.
* Use :ref:`hierarchical verilation`.
@ -421,7 +421,7 @@ Why do so many files need to recompile when I add a signal?
"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
Adding a new signal requires the symbol table to be recompiled. Verilator
uses one large symbol table, as that results in 2-3 less assembly
uses one large symbol table, resulting in 2-3 fewer assembly
instructions for each signal access. This makes the execution time 10-15%
faster, but can result in more compilations when something changes.
@ -449,8 +449,8 @@ How do I access signals in C?
The best thing to do is to make a SystemVerilog "export DPI" task or
function that accesses that signal, as described in the DPI chapter in the
manual and DPI tutorials on the web. This will allow Verilator to better
optimize the model and should be portable across simulators.
manual and DPI tutorials on the web. This will allow Verilator to
optimize the model better and should be portable across simulators.
If you really want raw access to the signals, declare the signals you will
be accessing with a :option:`/*verilator&32;public*/` metacomment before
@ -459,17 +459,17 @@ the signal, as you would any other member variable.
Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t),
16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or
64-bit unsigned long longs (uint64_t) that fits the width of the signal.
64-bit unsigned long longs (uint64_t) that fit the width of the signal.
Generally, you can use just uint32_t's for 1 to 32 bits, or uint64_t for
1 to 64 bits, and the compiler will properly up-convert smaller entities.
Note even signed ports are declared as unsigned; you must sign extend
Note that even signed ports are declared as unsigned; you must sign extend
yourself to the appropriate signal width.
Signals wider than 64 bits are stored as an array of 32-bit uint32_t's.
Thus to read bits 31:0, access signal[0], and for bits 63:32, access
signal[1]. Unused bits (for example bit numbers 65-96 of a 65-bit vector)
will always be zero. If you change the value you must make sure to pack
zeros in the unused bits or core-dumps may result, because Verilator strips
Thus, to read bits 31:0, access signal[0], and for bits 63:32, access
signal[1]. Unused bits (for example, bit numbers 65-96 of a 65-bit vector)
will always be zero. If you change the value, you must pack
zeros in the unused bits, or core-dumps may result because Verilator strips
array bound checks where it believes them to be unnecessary to improve
performance.
@ -490,16 +490,16 @@ From the sc_main.cpp file, you'd then:
In this example, clk is a bool you can read or set as any other variable.
The value of normal signals may be set, though clocks shouldn't be changed
by your code or you'll get strange results.
The value of normal signals may be set, though your code shouldn't change
clocks, or you'll get strange results.
Should a module be in Verilog or SystemC?
"""""""""""""""""""""""""""""""""""""""""
Sometimes there is a block that only interconnects instances, and have a
choice as to if you write it in Verilog or SystemC. Everything else being
equal, best performance is when Verilator sees all of the design. So, look
Sometimes there is a block that only interconnects instances, and you have a
choice if you write it in Verilog or SystemC. Everything else being
equal, the best performance is when Verilator sees all of the design. So, look
at the hierarchy of your design, labeling instances as to if they are
SystemC or Verilog. Then:
@ -510,6 +510,6 @@ SystemC or Verilog. Then:
* A module with only Verilog instances below can be either, but for best
performance should be Verilog. (The exception is if you have a design
that is instantiated many times; in this case Verilating one of the lower
that is instantiated many times; in this case, Verilating one of the lower
modules and instantiating that Verilated instances multiple times into a
SystemC module *may* be faster.)

10
docs/guide/files.rst
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@ -59,13 +59,13 @@ For --cc/--sc, it creates:
* - *{prefix}*\ .cpp
- Model C++ file
* - *{prefix}*\ ___024root.h
- Top level (SystemVerilog $root) internal header file
- Top-level internal header file (from SystemVerilog $root)
* - *{prefix}*\ ___024root.cpp
- Top level (SystemVerilog $root) internal C++ file
- Top-level internal C++ file (from SystemVerilog $root)
* - *{prefix}*\ ___024root\ *{__n}*\ .cpp
- Additional top level internal C++ files
- Additional top-level internal C++ files
* - *{prefix}*\ ___024root\ *{__DepSet_hash__n}*\ .cpp
- Additional top level internal C++ files (hashed to reduce build times)
- Additional top-level internal C++ files (hashed to reduce build times)
* - *{prefix}*\ ___024root__Slow\ *{__n}*\ .cpp
- Infrequent cold routines
* - *{prefix}*\ ___024root\ *{__DepSet_hash__n}*\ .cpp
@ -106,7 +106,7 @@ For --hierarchy mode, it creates:
* - *{prefix}*\ __hier.dir
- Directory to store .dot, .vpp, .tree of top module (from --hierarchy)
In certain debug and other modes, it also creates:
In specific debug and other modes, it also creates:
.. list-table::

34
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@ -16,14 +16,14 @@ Package Manager Quick Install
Using a distribution's package manager is the easiest way to get
started. (Note packages are unlikely to have the most recent version, so
:ref:`Git Install`, might be a better alternative.) To install as a
:ref:`Git Install` might be a better alternative.) To install as a
package:
::
apt-get install verilator # On Ubuntu
For other distributions refer to `Repology Verilator Distro Packages
For other distributions, refer to `Repology Verilator Distro Packages
<https://repology.org/project/verilator>`__.
.. _Git Install:
@ -31,8 +31,8 @@ For other distributions refer to `Repology Verilator Distro Packages
Git Quick Install
=================
Installing Verilator from Git provides the most flexibility. For additional
options and details see :ref:`Detailed Build Instructions` below.
Installing Verilator from Git provides the most flexibility; for additional
options and details, see :ref:`Detailed Build Instructions` below.
In brief, to install from git:
@ -68,7 +68,7 @@ In brief, to install from git:
Detailed Build Instructions
===========================
This section describes details of the build process, and assumes you are
This section describes details of the build process and assumes you are
building from Git. For using a pre-built binary for your Linux
distribution, see instead :ref:`Package Manager Quick Install`.
@ -77,11 +77,11 @@ OS Requirements
---------------
Verilator is developed and has primary testing on Ubuntu, with additional
testing on FreeBSD and Apple OS-X. Versions have also built on Red Hat
Linux, and other flavors of GNU/Linux-ish platforms. Verilator also works
on Windows Subsystem for Linux (WSL2), Windows under Cygwin, and Windows
under MinGW (gcc -mno-cygwin). Verilated output (not Verilator itself)
compiles under all the options above, plus using MSVC++.
testing on FreeBSD and Apple OS-X. Versions have also been built on Red Hat
Linux, other flavors of GNU/Linux-ish platforms, Windows Subsystem for
Linux (WSL2), Windows under Cygwin, and Windows under MinGW (gcc
-mno-cygwin). Verilated output (not Verilator itself) compiles under all
the options above, plus using MSVC++.
Install Prerequisites
@ -153,13 +153,13 @@ required at Verilator build time.
Obtain Sources
--------------
Get the sources from the git repository: (You need do this only once,
Get the sources from the git repository: (You need to do this only once,
ever.)
::
git clone https://github.com/verilator/verilator # Only first time
## Note the URL above is not a page you can see with a browser, it's for git only
## Note the URL above is not a page you can see with a browser; it's for git only
Enter the checkout and determine what version/branch to use:
@ -186,7 +186,7 @@ Create the configuration script:
Eventual Installation Options
-----------------------------
Before configuring the build, you have to decide how you're going to
Before configuring the build, you must decide how you're going to
eventually install Verilator onto your system. Verilator will be compiling
the current value of the environment variables :option:`VERILATOR_ROOT`,
:option:`SYSTEMC_INCLUDE`, and :option:`SYSTEMC_LIBDIR` as defaults into
@ -220,8 +220,8 @@ the path to all needed files.
You may eventually be installing onto a project/company-wide "CAD" tools
disk that may support multiple versions of every tool. Tell configure the
eventual destination directory name. We recommend the destination location
include the Verilator version name:
eventual destination directory name. We recommend that the destination
location include the Verilator version name:
::
@ -255,7 +255,7 @@ as most GNU tools support:
unsetenv VERILATOR_ROOT # if your shell is csh
./configure --prefix /opt/verilator-VERSION
Then after installing (below steps) you will need to add
Then after installing (below steps), you will need to add
``/opt/verilator-VERSION/bin`` to your ``$PATH`` environment variable.
@ -271,7 +271,7 @@ configure's default system paths:
unsetenv VERILATOR_ROOT # if your shell is csh
./configure
Then after installing (below) the binaries should be in a location that is
Then after installing (below), the binaries should be in a location
already in your ``$PATH`` environment variable.

155
docs/guide/languages.rst
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@ -41,7 +41,7 @@ union, var, void, priority case/if, and unique case/if.
It also supports .name and .\* interconnection.
Verilator partially supports concurrent assert and cover statements; see
the enclosed coverage tests for the syntax which is allowed.
the enclosed coverage tests for the allowed syntax.
Verilator has limited support for class and related object-oriented
constructs.
@ -58,8 +58,8 @@ function call-like preprocessor defines, default define arguments,
SystemVerilog 2017 (IEEE 1800-2017) Support
-------------------------------------------
Verilator supports the 2017 "for" loop constructs, and several minor
cleanups IEEE made in 1800-2017.
Verilator supports the 2017 "for" loop constructs and several cleanups IEEE
made in 1800-2017.
Verilog AMS Support
@ -67,14 +67,13 @@ Verilog AMS Support
Verilator implements a very small subset of Verilog AMS (Verilog Analog and
Mixed-Signal Extensions) with the subset corresponding to those VMS
keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009
languages.
keywords with near-equivalents in Verilog 2005 or SystemVerilog 2017.
AMS parsing is enabled with :vlopt:`--language VAMS <--language>` or
:vlopt:`--language 1800+VAMS <--language>`.
At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt,
string, and wreal.
Verilator implements ceil, exp, floor, ln, log, pow, sqrt, string, and
wreal.
Synthesis Directive Assertion Support
@ -87,12 +86,12 @@ directives. The same applies to any :code:`//ambit synthesis`,
:code:`//cadence` or :code:`//pragma` directives of the same form.
When these synthesis directives are discovered, Verilator will either
formally prove the directive to be true, or failing that, will insert the
formally prove the directive to be true, or, failing that, will insert the
appropriate code to detect failing cases at simulation runtime and print an
"Assertion failed" error message.
Verilator likewise also asserts any "unique" or "priority" SystemVerilog
keywords on case statement, as well as "unique" on if statements. However,
keywords on case statements, as well as "unique" on if statements. However,
"priority if" is currently ignored.
@ -109,7 +108,7 @@ With :vlopt:`--timing`, all timing controls are supported:
as well as all flavors of :code:`fork`.
Compiling a verilated design that makes use of these features requires a
Compiling a Verilated design that uses these features requires a
compiler with C++20 coroutine support, e.g. Clang 5, GCC 10, or newer.
:code:`#0` delays cause Verilator to issue the :option:`ZERODLY` warning, as
@ -125,11 +124,11 @@ always the one chosen. Such expressions cause the :option:`MINTYPMAX` warning.
Another consequence of using :vlopt:`--timing` is that the :vlopt:`--main`
option generates a main file with a proper timing eval loop, eliminating the
need for writing any driving C++ code. You can then simply compile the
need for writing any driving C++ code. You can simply compile the
simulation (perhaps using :vlopt:`--build`) and run it.
With :vlopt:`--no-timing`, all timing controls cause the :option:`NOTIMING`
error, with the exception of:
error, except:
* delay statements – they are ignored (as they are in synthesis), though they
do issue a :option:`STMTDLY` warning,
@ -138,16 +137,15 @@ error, with the exception of:
* net delays – they are ignored,
* event controls at the top of the procedure,
Forks cause this error as well, with the exception of:
Forks cause this error as well, except:
* forks with no statements,
* :code:`fork..join` or :code:`fork..join_any` with one statement,
* forks with :vlopt:`--bbox-unsup`.
If neither :vlopt:`--timing` nor :vlopt:`--no-timing` is specified, all timing
controls cause the :option:`NEEDTIMINGOPT` error, with the exception of event
controls at the top of the process. Forks cause this error as well, with the
exception of:
If neither :vlopt:`--timing` nor :vlopt:`--no-timing` is specified, all
timing controls cause the :option:`NEEDTIMINGOPT` error, except event
controls at the top of the process. Forks cause this error as well, except:
* forks with no statements,
* :code:`fork..join` or :code:`fork..join_any` with one statement,
@ -175,15 +173,15 @@ Synthesis Subset
Verilator supports the Synthesis subset with other verification constructs
being added over time. Verilator also simulates events as Synopsys's Design
Compiler would; namely given a block of the form:
Compiler would, namely given a block of the form:
.. code-block:: sv
always @(x) y = x & z;
This will recompute y when there is even a potential for change in x or a
change in z, that is when the flops computing x or z evaluate (which is
what Design Compiler will synthesize.) A compliant simulator would only
This will recompute y when there is a potential for change in x or a change
in z; that is when the flops computing x or z evaluate (which is what
Design Compiler will synthesize.) A compliant simulator will only
calculate y if x changes. We recommend using always_comb to make the code
run the same everywhere. Also avoid putting $displays in combo blocks, as
they may print multiple times when not desired, even on compliant
@ -196,7 +194,7 @@ Signal Naming
To avoid conflicts with C symbol naming, any character in a signal name
that is not alphanumeric nor a single underscore will be replaced by __0hh
where hh is the hex code of the character. To avoid conflicts with
Verilator's internal symbols, any double underscore are replaced with
Verilator's internal symbols, any double underscore is replaced with
___05F (5F is the hex code of an underscore.)
@ -211,14 +209,13 @@ Class
-----
Verilator class support is limited but in active development. Verilator
supports members, and methods. Verilator does not support class static
members, class extend, or class parameters.
supports members, methods, class extend, and class parameters.
Dotted cross-hierarchy references
---------------------------------
Verilator supports dotted references to variables, functions and tasks in
Verilator supports dotted references to variables, functions, and tasks in
different modules. The portion before the dot must have a constant value;
for example a[2].b is acceptable, while a[x].b is generally not.
@ -232,7 +229,7 @@ code.
Latches
-------
Verilator is optimized for edge sensitive (flop based) designs. It will
Verilator is optimized for edge-sensitive (flop-based) designs. It will
attempt to do the correct thing for latches, but most performance
optimizations will be disabled around the latch.
@ -252,38 +249,38 @@ unsupported.
Unknown States
--------------
Verilator is mostly a two state simulator, not a four state simulator.
However, it has two features which uncover most initialization bugs
(including many that a four state simulator will miss.)
Verilator is mostly a two-state simulator, not a four-state simulator.
However, it has two features that uncover most initialization bugs
(including many that a four-state simulator will miss.)
Identity comparisons (=== or !==) are converted to standard ==/!= when
neither side is a constant. This may make the expression yield a different
result compared to a four state simulator. An === comparison to X will
result than a four-state simulator. An === comparison to X will
always be false, so that Verilog code which checks for uninitialized logic
will not fire.
Assigning X to a variable will actually assign a constant value as
determined by the :vlopt:`--x-assign` option. This allows runtime
randomization, thus if the value is actually used, the random value should
cause downstream errors. Integers also get randomized, even though the
Verilog 2001 specification says they initialize to zero. Note however that
randomization happens at initialization time and hence during a single
simulation run, the same constant (but random) value will be used every
time the assignment is executed.
Assigning X to a variable will assign a constant value as determined by the
:vlopt:`--x-assign` option. This allows runtime randomization; thus, if
the value is used, the random value should cause downstream errors.
Integers also get randomized, even though the Verilog 2001 specification
says they initialize to zero. However, randomization happens at
initialization time; hence, during a single simulation run, the same
constant (but random) value will be used every time the assignment is
executed.
All variables, depending on :vlopt:`--x-initial` setting, are typically
randomly initialized using a function. By running several random
simulation runs you can determine that reset is working correctly. On the
first run, have the function initialize variables to zero. On the second,
have it initialize variables to one. On the third and following runs have
it initialize them randomly. If the results match, reset works. (Note
this is what the hardware will really do.) In practice, just setting all
variables to one at startup finds most problems (since typically control
signals are active-high).
randomly initialized using a function. You can determine that reset is
working correctly by running several random simulation runs. On the first
run, have the function initialize variables to zero. On the second, have
it initialize variables to one. On the third and following runs, have it
initialize them randomly. If the results match, reset works. (Note that
this is what the hardware will do.) In practice, setting all variables to
one at startup finds the most problems (since control signals are typically
active-high).
:vlopt:`--x-assign` applies to variables explicitly initialized or assigned
an X. Uninitialized clocks are initialized to zero, while all other state
holding variables are initialized to a random value. Event driven
holding variables are initialized to a random value. Event-driven
simulators will generally trigger an edge on a transition from X to 1
(posedge) or X to 0 (negedge). However, by default, since clocks are
initialized to zero, Verilator will not trigger an initial negedge. Some
@ -319,19 +316,19 @@ External logic will be needed to combine these signals with any external
drivers.
Tristate drivers are not supported inside functions and tasks; an inout
there will be considered a two state variable that is read and written
instead of a four state variable.
there will be considered a two-state variable that is read and written
instead of a four-state variable.
Functions & Tasks
-----------------
All functions and tasks will be inlined (will not become functions in C.)
The only support provided is for simple statements in tasks (which may
The only support provided is simple statements in tasks (which may
affect global variables).
Recursive functions and tasks are not supported. All inputs and outputs
are automatic, as if they had the Verilog 2001 "automatic" keyword
are automatic as if they had the Verilog 2001 "automatic" keyword
prepended. (If you don't know what this means, Verilator will do what you
probably expect, what C does. The default behavior of Verilog is
different.)
@ -363,13 +360,13 @@ error for more information.
Array Out of Bounds
-------------------
Writing a memory element that is outside the bounds specified for the array
may cause a different memory element inside the array to be written
instead. For power-of-2 sized arrays, Verilator will give a width warning
and the address. For non-power-of-2-sizes arrays, index 0 will be written.
Writing a memory element outside the bounds specified for the array may
cause a different memory element inside the array to be written instead.
For power-of-2 sized arrays, Verilator will give a width warning and the
address. For non-power-of-2-sizes arrays, index 0 will be written.
Reading a memory element that is outside the bounds specified for the array
will give a width warning and wrap around the power-of-2 size. For
Reading a memory element outside the bounds specified for the array will
give a width warning and wrap around the power-of-2 size. For
non-power-of-2 sizes, it will return an unspecified constant of the
appropriate width.
@ -390,14 +387,14 @@ Force statement
---------------
Verilator supports the procedural `force` (and corresponding `release`)
statement. The behavior of the `force` statement however does not entirely
comply with the IEEE 1800 SystemVerilog standard. According to the standard,
statement. However, the behavior of the `force` statement does not entirely
comply with IEEE 1800. According to the standard,
when a procedural statement of the form `force a = b;` is executed, the
simulation should behave as if from that point forwards, a continuous
assignment `assign a = b;` have been added to override the drivers of `a`.
More specifically: the value of `a` should be updated, whenever the value of
`b` changes, all the way until a `release a;` statement is executed.
Verilator instead evaluates the current value of `b` at the time the `force`
simulation should behave as if, from that point forwards, a continuous
assignment `assign a = b;` has been added to override the drivers of `a`.
More specifically: the value of `a` should be updated whenever the value of
`b` changes, until a `release a;` statement is executed.
Verilator instead evaluates the current value of `b` when the `force`
statement is executed, and forces `a` to that value, without updating it
until a new `force` or `release` statement is encountered that applies to
`a`. This non-standard behavior is nevertheless consistent with some other
@ -407,7 +404,7 @@ simulators.
Encrypted Verilog
-----------------
Open source simulators like Verilator are unable to use encrypted RTL
Open-source simulators like Verilator cannot use encrypted RTL
(i.e. IEEE P1735). Talk to your IP vendor about delivering IP blocks via
Verilator's :vlopt:`--protect-lib` feature.
@ -448,12 +445,12 @@ This section describes specific limitations for each language keyword.
certain limited cases.
'{} operator
Assignment patterns with order based, default, constant integer (array)
Assignment patterns with an order based, default, constant integer (array)
or member identifier (struct/union) keys are supported. Data type keys
and keys which are computed from a constant expression are not supported.
and keys computed from a constant expression are not supported.
\`uselib
Uselib, a vendor specific library specification method, is ignored along
Uselib, a vendor-specific library specification method, is ignored along
with anything following it until the end of that line.
cast operator
@ -461,8 +458,8 @@ cast operator
unsigned, not arrays nor structs.
chandle
Treated as a "longint"; does not yet warn about operations that are
specified as illegal on chandles.
Treated as a "longint"; does not yet warn about operations specified as
illegal on chandles.
disable
Disable statements may be used only if the block being disabled is a
@ -475,7 +472,7 @@ inside
upper bound. Case inside and case matches are also unsupported.
interface
Interfaces and modports, including with generated data types are
Interfaces and modports, including generated data types are
supported. Generate blocks around modports are not supported, nor are
virtual interfaces nor unnamed interfaces.
@ -487,25 +484,25 @@ specify specparam
All specify blocks and timing checks are ignored.
uwire
Verilator does not perform warning checking on uwires, it treats the
Verilator does not perform warning checking on uwires; it treats the
uwire keyword as if it were the normal wire keyword.
$bits, $countbits, $countones, $finish, $isunknown, $onehot, $onehot0, $signed, $stime, $stop, $time, $unsigned,
Generally supported.
$dump/$dumpports and related
$dumpfile or $dumpports will create a VCD or FST file (which is based on
$dumpfile or $dumpports will create a VCD or FST file (based on
the :vlopt:`--trace` option given when the model was Verilated). This
will take effect starting at the next eval() call. If you have multiple
Verilated designs under the same C model, then this will dump signals
Verilated designs under the same C model, this will dump signals
only from the design containing the $dumpvars.
$dumpvars and $dumpports module identifier is ignored; the traced
instances will always start at the top of the design. The levels argument
is also ignored, use tracing_on/tracing_off pragmas instead.
is also ignored; use tracing_on/tracing_off pragmas instead.
$dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename
argument is ignored, only a single trace file may be active at once.
argument is ignored; only a single trace file may be active at once.
$dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and
$dumplimit/$dumpportlimit are currently ignored.
@ -514,7 +511,7 @@ $error, $fatal, $info, $warning.
Generally supported.
$exit, $finish, $stop
The rarely used optional parameter to $finish and $stop is ignored. $exit
The rarely used optional parameter to $finish and $stop is ignored; $exit
is aliased to $finish.
$fopen, $fclose, $fdisplay, $ferror, $feof, $fflush, $fgetc, $fgets, $fscanf, $fwrite, $fscanf, $sscanf
@ -530,8 +527,8 @@ $random, $urandom, $urandom_range
per object for random stability of $urandom/$urandom_range.
$readmemb, $readmemh
Read memory commands are supported. Note Verilator and the Verilog
specification does not include support for readmem to multi-dimensional
Read memory commands are supported. Verilator and the Verilog
specification do not include support for readmem to multi-dimensional
arrays.
$test$plusargs, $value$plusargs

12
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@ -9,13 +9,13 @@ Welcome to Verilator!
The Verilator package converts Verilog [#]_ and SystemVerilog [#]_ hardware
description language (HDL) designs into a C++ or SystemC model that, after
compiling, can be executed. Verilator is not a traditional simulator, but a
compiling, can be executed. Verilator is not a traditional simulator but a
compiler.
Verilator is typically used as follows:
1. The :command:`verilator` executable is invoked with parameters similar
to GCC, or other simulators such as Cadence Verilog-XL/NC-Verilog, or
to GCC or other simulators such as Cadence Verilog-XL/NC-Verilog, or
Synopsys VCS. Verilator reads the specified SystemVerilog code, lints it,
optionally adds coverage and waveform tracing support, and compiles the
design into a source-level multithreaded C++ or SystemC "model". The
@ -28,10 +28,10 @@ output is a "Verilated" model.
instantiates the Verilated model as a C++/SystemC object.
3. The user C++ wrapper, the files created by Verilator, a "runtime
library" provided by Verilator, and if applicable SystemC libraries are
library" provided by Verilator, and, if applicable SystemC libraries are
then compiled using a C++ compiler to create a simulation executable.
4. The resulting executable will perform the actual simulation, during
4. The resulting executable will perform the actual simulation during
"simulation runtime".
5. If appropriately enabled, the executable may also generate waveform
@ -45,11 +45,11 @@ The best place to get started is to try the :ref:`Examples`.
Engineers (IEEE) Standard for Verilog Hardware Description
Language`, Std. 1364, released in 1995, 2001, and 2005. The
Verilator documentation uses the shorthand, e.g., "IEEE 1394-2005",
to refer to the e.g. 2005 version of this standard.
to refer to the, e.g., 2005 version of this standard.
.. [#] SystemVerilog is defined by the `Institute of Electrical and
Electronics Engineers (IEEE) Standard for SystemVerilog - Unified
Hardware Design, Specification, and Verification Language`, Standard
1800, released in 2005, 2009, 2012, and 2017. The Verilator
documentation uses the shorthand e.g., "IEEE 1800-2017", to refer to
the e.g. 2017 version of this standard.
the, e.g., 2017 version of this standard.

231
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@ -7,7 +7,7 @@
Simulating (Verilated-Model Runtime)
************************************
This section describes items related to simulating, that is, the use of a
This section describes items related to simulating, that is, using a
Verilated model's executable. For the runtime arguments to a simulated
model, see :ref:`Simulation Runtime Arguments`.
@ -21,29 +21,29 @@ For best performance, run Verilator with the :vlopt:`-O3`
:vlopt:`--x-assign fast <--x-assign>`
:vlopt:`--x-initial fast <--x-initial>`
:vlopt:`--noassert <--assert>` options. The :vlopt:`-O3`
option will require longer time to run Verilator, and
option will require a longer time to run Verilator, and
:vlopt:`--x-assign fast <--x-assign>`
:vlopt:`--x-initial fast <--x-assign>`
may increase the risk of reset bugs in trade for performance; see the above
documentation for these options.
If using Verilated multithreaded, use ``numactl`` to ensure you are using
non-conflicting hardware resources. See :ref:`Multithreading`. Also
consider using profile-guided optimization, see :ref:`Thread PGO`.
If using Verilated multithreaded, use ``numactl`` to ensure you use
non-conflicting hardware resources. See :ref:`Multithreading`. Also,
consider using profile-guided optimization; see :ref:`Thread PGO`.
Minor Verilog code changes can also give big wins. You should not have any
UNOPTFLAT warnings from Verilator. Fixing these warnings can result in
huge improvements; one user fixed their one UNOPTFLAT warning by making a
simple change to a clock latch used to gate clocks and gained a 60%
performance improvement.
:option:`UNOPTFLAT` warnings from Verilator. Fixing these warnings can
result in huge improvements; one user fixed their one UNOPTFLAT warning by
making a simple change to a clocked latch used to gate clocks and gained a
60% performance improvement.
Beyond that, the performance of a Verilated model depends mostly on your
C++ compiler and size of your CPU's caches. Experience shows that large
models are often limited by the size of the instruction cache, and as such
reducing code size if possible can be beneficial.
Beyond that, the performance of a Verilated model depends primarily on your
C++ compiler and the size of your CPU's caches. Experience shows that the
instruction cache size often limits large models, and reducing code size,
if possible, can be beneficial.
The supplied $VERILATOR_ROOT/include/verilated.mk file uses the OPT,
OPT_FAST, OPT_SLOW and OPT_GLOBAL variables to control optimization. You
OPT_FAST, OPT_SLOW, and OPT_GLOBAL variables to control optimization. You
can set these when compiling the output of Verilator with Make, for
example:
@ -51,17 +51,17 @@ example:
make OPT_FAST="-Os -march=native" -f Vour.mk Vour__ALL.a
OPT_FAST specifies optimization options for those parts of the model that
are on the fast path. This is mostly code that is executed every
cycle. OPT_SLOW applies to slow-path code, which executes rarely, often
only once at the beginning or end of simulation. Note that OPT_SLOW is
OPT_FAST specifies optimization options for those parts of the model
on the fast path. This is mostly code that is executed every
cycle. OPT_SLOW applies to slow-path code, which rarely executes, often
only once at the beginning or end of the simulation. OPT_SLOW is
ignored if VM_PARALLEL_BUILDS is not 1, in which case all generated code
will be compiled in a single compilation unit using OPT_FAST. See also the
Verilator :vlopt:`--output-split` option. The OPT_GLOBAL variable applies
to common code in the runtime library used by Verilated models (shipped in
$VERILATOR_ROOT/include). Additional C++ files passed on the verilator
command line use OPT_FAST. The OPT variable applies to all compilation
units in addition to the specific "OPT" variables described above.
units and the specific "OPT" variables described above.
You can also use the :vlopt:`-CFLAGS` and/or :vlopt:`-LDFLAGS` options on
the verilator command line to pass arguments directly to the compiler or
@ -70,53 +70,53 @@ linker.
The default values of the "OPT" variables are chosen to yield good
simulation speed with reasonable C++ compilation times. To this end,
OPT_FAST is set to "-Os" by default. Higher optimization such as "-O2" or
"-O3" may help (though often they provide only a very small performance
benefit), but compile times may be excessively large even with medium sized
"-O3" may help (though often they provide only a minimal performance
benefit), but compile times may be excessively large even with medium-sized
designs. Compilation times can be improved at the expense of simulation
speed by reducing optimization, for example with OPT_FAST="-O0". Often good
simulation speed can be achieved with OPT_FAST="-O1 -fstrict-aliasing" but
with improved compilation times. Files controlled by OPT_SLOW have little
effect on performance and therefore OPT_SLOW is empty by default
(equivalent to "-O0") for improved compilation speed. In common use-cases
speed by reducing optimization, for example, with OPT_FAST="-O0". Often
good simulation speed can be achieved with OPT_FAST="-O1 -fstrict-aliasing"
but with improved compilation times. Files controlled by OPT_SLOW have
little effect on performance, and therefore OPT_SLOW is empty by default
(equivalent to "-O0") for improved compilation speed. In common use cases,
there should be little benefit in changing OPT_SLOW. OPT_GLOBAL is set to
"-Os" by default and there should rarely be a need to change it. As the
runtime library is small in comparison to a lot of Verilated models,
disabling optimization on the runtime library should not have a serious
effect on overall compilation time, but may have detrimental effect on
simulation speed, especially with tracing. In addition to the above, for
best results use OPT="-march=native", the latest Clang compiler (about 10%
faster than GCC), and link statically.
"-Os" by default, and there should rarely be a need to change it. As the
runtime library is small compared to many Verilated models, disabling
optimization on the runtime library should not seriously affect overall
compilation time but may have a detrimental effect on simulation speed,
especially with tracing. In addition to the above, for best results, use
OPT="-march=native", the latest Clang compiler (about 10% faster than GCC),
and link statically.
Generally the answer to which optimization level gives the best user
experience depends on the use case and some experimentation can pay
Generally, the answer to which optimization level gives the best user
experience depends on the use case, and some experimentation can pay
dividends. For a speedy debug cycle during development, especially on large
designs where C++ compilation speed can dominate, consider using lower
optimization to get to an executable faster. For throughput oriented use
cases, for example regressions, it is usually worth spending extra
optimization to get to an executable faster. For throughput-oriented use
cases, for example, regressions, it is usually worth spending extra
compilation time to reduce total CPU time.
If you will be running many simulations on a single model, you can
investigate profile guided optimization. See :ref:`Compiler PGO`.
investigate profile-guided optimization. See :ref:`Compiler PGO`.
Modern compilers also support link-time optimization (LTO), which can help
Modern compilers also support link-time optimization (LTO), which can help,
especially if you link in DPI code. To enable LTO on GCC, pass "-flto" in
both compilation and link. Note LTO may cause excessive compile times on
large designs.
both compilation and link. Note that LTO may cause excessive compile times
on large designs.
Unfortunately, using the optimizer with SystemC files can result in
compilation taking several minutes. (The SystemC libraries have many little
inlined functions that drive the compiler nuts.)
If you are using your own makefiles, you may want to compile the Verilated
If using your own makefiles, you may want to compile the Verilated
code with ``--MAKEFLAGS -DVL_INLINE_OPT=inline``. This will inline
functions, however this requires that all cpp files be compiled in a single
functions; however, this requires that all cpp files be compiled in a single
compiler run.
You may uncover further tuning possibilities by profiling the Verilog code.
See :ref:`profiling`.
When done optimizing, please let the author know the results. We like to
keep tabs on how Verilator compares, and may be able to suggest additional
keep tabs on how Verilator compares and may be able to suggest additional
improvements.
@ -143,14 +143,14 @@ Functional Coverage
-------------------
With :vlopt:`--coverage` or :vlopt:`--coverage-user`, Verilator will
translate functional coverage points which the user has inserted manually
into the SystemVerilog design, into the Verilated model.
translate functional coverage points the user has inserted manually win
SystemVerilog code through into the Verilated model.
Currently, all functional coverage points are specified using SystemVerilog
assertion syntax which must be separately enabled with :vlopt:`--assert`.
assertion syntax, which must be separately enabled with :vlopt:`--assert`.
For example, the following SystemVerilog statement will add a coverage
point, under the coverage name "DefaultClock":
point under the coverage name "DefaultClock":
.. code-block:: sv
@ -163,13 +163,13 @@ Line Coverage
-------------
With :vlopt:`--coverage` or :vlopt:`--coverage-line`, Verilator will
automatically add coverage analysis at each code flow change point (e.g. at
branches). At each such branch an unique counter is incremented. At the
end of a test, the counters along with the filename and line number
corresponding to each counter are written into the coverage file.
automatically add coverage analysis at each code flow change point (e.g.,
at branches). At each such branch, a counter is incremented. At the end
of a test, the counters, filename, and line number corresponding to each
counter are written into the coverage file.
Verilator automatically disables coverage of branches that have a $stop in
them, as it is assumed $stop branches contain an error check that should
Verilator automatically disables coverage of branches with a $stop in
them, as it is assumed that $stop branches contain an error check that should
not occur. A :option:`/*verilator&32;coverage_block_off*/` metacomment
will perform a similar function on any code in that block or below, or
:option:`/*verilator&32;coverage_off*/` and
@ -177,8 +177,9 @@ will perform a similar function on any code in that block or below, or
respectively around a block of code.
Verilator may over-count combinatorial (non-clocked) blocks when those
blocks receive signals which have had the UNOPTFLAT warning disabled; for
most accurate results do not disable this warning when using coverage.
blocks receive signals which have had the :option:`UNOPTFLAT` warning
disabled; for the most accurate results, do not disable this warning when
using coverage.
.. _Toggle Coverage:
@ -189,8 +190,8 @@ Toggle Coverage
With :vlopt:`--coverage` or :vlopt:`--coverage-toggle`, Verilator will
automatically add toggle coverage analysis into the Verilated model.
Every bit of every signal in a module has a counter inserted. The counter
will increment on every edge change of the corresponding bit.
Every bit of every signal in a module has a counter inserted, and the
counter will increment on every edge change of the corresponding bit.
Signals that are part of tasks or begin/end blocks are considered local
variables and are not covered. Signals that begin with underscores (see
@ -198,17 +199,17 @@ variables and are not covered. Signals that begin with underscores (see
total storage across all dimensions, see :vlopt:`--coverage-max-width`) are
also not covered.
Hierarchy is compressed, such that if a module is instantiated multiple
times, coverage will be summed for that bit across **all** instantiations
of that module with the same parameter set. A module instantiated with
different parameter values is considered a different module, and will get
counted separately.
Hierarchy is compressed, so if a module is instantiated multiple times,
coverage will be summed for that bit across **all** instantiations of that
module with the same parameter set. A module instantiated with different
parameter values is considered a different module and will get counted
separately.
Verilator makes a minimally-intelligent decision about what clock domain
the signal goes to, and only looks for edges in that clock domain. This
means that edges may be ignored if it is known that the edge could never be
seen by the receiving logic. This algorithm may improve in the future.
The net result is coverage may be lower than what would be seen by looking
means that edges may be ignored if it is known that the receiving logic
could never see the edge. This algorithm may improve in the future. The
net result is that coverage may be lower than what would be seen by looking
at traces, but the coverage is a more accurate representation of the
quality of stimulus into the design.
@ -226,7 +227,7 @@ signals that do not need toggle analysis, such as RAMs and register files.
Coverage Collection
-------------------
When any coverage flag was used to Verilate, Verilator will add appropriate
When any coverage flag is used to Verilate, Verilator will add appropriate
coverage point insertions into the model and collect the coverage data.
To get the coverage data from the model, in the user wrapper code,
@ -239,23 +240,23 @@ Run each of your tests in different directories, potentially in parallel.
Each test will create a :file:`logs/coverage.dat` file.
After running all of the tests, execute the :command:`verilator_coverage`
command, passing arguments pointing to the filenames of all of the
individual coverage files. :command:`verilator_coverage` will reads the
command, passing arguments pointing to the filenames of all the
individual coverage files. :command:`verilator_coverage` will read the
:file:`logs/coverage.dat` file(s), and create an annotated source code
listing showing code coverage details.
:command:`verilator_coverage` may also be used for test grading, that is
computing which tests are important to fully cover the design.
:command:`verilator_coverage` may also be used for test grading, computing
which tests are important to give full verification coverage on the design.
For an example, see the :file:`examples/make_tracing_c/logs` directory.
Grep for lines starting with '%' to see what lines Verilator believes need
more coverage.
Additional options of :command:`verilator_coverage` allow for merging of
coverage data files or other transformations.
Additional options of :command:`verilator_coverage` allow for the merging
of coverage data files or other transformations.
Info files can be written by verilator_coverage for import to
:command:`lcov`. This enables use of :command:`genhtml` for HTML reports
:command:`lcov`. This enables using :command:`genhtml` for HTML reports
and importing reports to sites such as `https://codecov.io
<https://codecov.io>`_.
@ -276,7 +277,7 @@ To use profiling:
#. Build and run the simulation model.
#. The model will create gmon.out.
#. Run :command:`gprof` to see where in the C++ code the time is spent.
#. Run the gprof output through the :command:`verilator_profcfunc` program
#. Run the gprof output through the :command:`verilator_profcfunc` program,
and it will tell you what Verilog line numbers on which most of the time
is being spent.
@ -286,7 +287,7 @@ To use profiling:
Execution Profiling
===================
For performance optimization, it is useful to see statistics and visualize how
For performance optimization, it is helpful to see statistics and visualize how
execution time is distributed in a verilated model.
With the :vlopt:`--prof-exec` option, Verilator will:
@ -296,14 +297,13 @@ With the :vlopt:`--prof-exec` option, Verilator will:
* Add code to save profiling data in non-human-friendly form to the file
specified with :vlopt:`+verilator+prof+exec+file+\<filename\>`.
* In multi-threaded models, add code to record the start and end time of each
macro-task across a number of calls to eval. (What is a macro-task? See the
* In multithreaded models, add code to record each macro-task's start and
end time across several calls to eval. (What is a macro-task? See the
Verilator internals document (:file:`docs/internals.rst` in the
distribution.)
The :command:`verilator_gantt` program may then be run to transform the
saved profiling file into a nicer visual format and produce some related
statistics.
saved profiling file into a visual format and produce related statistics.
.. figure:: figures/fig_gantt_min.png
@ -311,11 +311,11 @@ statistics.
The measured_parallelism shows the number of CPUs being used at a given moment.
The cpu_thread section shows which thread is executing on each of the physical CPUs.
The cpu_thread section shows which thread is executing on each physical CPU.
The thread_mtask section shows which macro-task is running on a given thread.
For more information see :command:`verilator_gantt`.
For more information, see :command:`verilator_gantt`.
.. _Profiling ccache efficiency:
@ -323,12 +323,11 @@ For more information see :command:`verilator_gantt`.
Profiling ccache efficiency
===========================
The Verilator generated Makefile provides support for basic profiling of
ccache behavior during the build. This can be used to track down files that
might be unnecessarily rebuilt, though as of today even small code changes
will usually require rebuilding a large number of files. Improving ccache
efficiency during the edit/compile/test loop is an active area of
development.
The Verilator-generated Makefile supports basic profiling of ccache
behavior during the build. This can be used to track down files that might
be unnecessarily rebuilt, though as of today, even minor code changes will
usually require rebuilding a large number of files. Improving ccache
efficiency during the edit/compile/test loop is an active development area.
To get a basic report of how well ccache is doing, add the `ccache-report`
target when invoking the generated Makefile:
@ -352,17 +351,17 @@ releases.
Save/Restore
============
The intermediate state of a Verilated model may be saved, so that it may
The intermediate state of a Verilated model may be saved so that it may
later be restored.
To enable this feature, use :vlopt:`--savable`. There are limitations in
what language features are supported along with :vlopt:`--savable`; if you
attempt to use an unsupported feature Verilator will throw an error.
attempt to use an unsupported feature, Verilator will throw an error.
To use save/restore, the user wrapper code must create a VerilatedSerialize
or VerilatedDeserialze object then calling the :code:`<<` or :code:`>>`
operators on the generated model and any other data the process needs
saved/restored. These functions are not thread safe, and are typically
or VerilatedDeserialze object and then call the :code:`<<` or :code:`>>`
operators on the generated model and any other data the process needs to be
saved/restored. These functions are not thread-safe and are typically
called only by a main thread.
For example:
@ -372,7 +371,7 @@ For example:
void save_model(const char* filenamep) {
VerilatedSave os;
os.open(filenamep);
os << main_time; // user code must save the timestamp, etc
os << main_time; // user code must save the timestamp
os << *topp;
}
void restore_model(const char* filenamep) {
@ -387,11 +386,11 @@ Profile-Guided Optimization
===========================
Profile-guided optimization is the technique where profiling data is
collected by running your simulation executable, then this information is
collected by running your simulation executable; then this information is
used to guide the next Verilation or compilation.
There are two forms of profile-guided optimizations. Unfortunately for
best results they must each be performed from the highest level code to the
There are two forms of profile-guided optimizations. Unfortunately, for
best results, they must each be performed from the highest level code to the
lowest, which means performing them separately and in this order:
* :ref:`Thread PGO`
@ -399,7 +398,7 @@ lowest, which means performing them separately and in this order:
Other forms of PGO may be supported in the future, such as clock and reset
toggle rate PGO, branch prediction PGO, statement execution time PGO, or
others as they prove beneficial.
others, as they prove beneficial.
.. _Thread PGO:
@ -407,7 +406,7 @@ others as they prove beneficial.
Thread Profile-Guided Optimization
----------------------------------
Verilator supports profile-guided optimization (Verilation) of multi-threaded
Verilator supports profile-guided optimization (Verilation) of multithreaded
models (Thread PGO) to improve performance.
When using multithreading, Verilator computes how long macro tasks take and
@ -425,24 +424,24 @@ optimization.
Run the model executable. When the executable exits, it will create a
profile.vlt file.
Rerun Verilator, optionally omitting the :vlopt:`--prof-pgo` option,
and adding the profile.vlt generated earlier to the command line.
Rerun Verilator, optionally omitting the :vlopt:`--prof-pgo` option and
adding the :file:`profile.vlt` generated earlier to the command line.
Note there is no Verilator equivalent to GCC's --fprofile-use. Verilator's
profile data file (profile.vlt) can be placed on the verilator command line
directly without any prefix.
Note there is no Verilator equivalent to GCC's --fprofile-use. Verilator's
profile data file (:file:`profile.vlt`) can be placed directly on the
verilator command line without any option prefix.
If results from multiple simulations are to be used in generating the
optimization, multiple simulation's profile.vlt may be concatenated
externally, or each of the files may be fed as separate command line
options into Verilator. Verilator will sum the profile results, so a
longer running test will have proportionally more weight for optimization
than a shorter running test.
externally, or each file may be fed as separate command line options into
Verilator. Verilator will sum the profile results, so a long-running test
will have more weight for optimization proportionally than a
shorter-running test.
If you provide any profile feedback data to Verilator, and it cannot use
If you provide any profile feedback data to Verilator and it cannot use
it, it will issue the :option:`PROFOUTOFDATE` warning that threads were
scheduled using estimated costs. This usually indicates that the profile
data was generated from different Verilog source code than Verilator is
data was generated from a different Verilog source code than Verilator is
currently running against. Therefore, repeat the data collection phase to
create new profiling data, then rerun Verilator with the same input source
files and that new profiling data.
@ -454,12 +453,12 @@ Compiler Profile-Guided Optimization
------------------------------------
GCC and Clang support compiler profile-guided optimization (PGO). This
optimizes any C/C++ program including Verilated code. Using compiler PGO
optimizes any C/C++ program, including Verilated code. Using compiler PGO
typically yields improvements of 5-15% on both single-threaded and
multi-threaded models.
multithreaded models.
To use compiler PGO with GCC or Clang, please see the appropriate compiler
documentation. The process in GCC 10 was as follows:
Please see the appropriate compiler documentation to use PGO with GCC or
Clang. The process in GCC 10 was as follows:
1. Compile the Verilated model with the compiler's "-fprofile-generate"
flag:
@ -469,7 +468,7 @@ documentation. The process in GCC 10 was as follows:
verilator [whatever_flags] --make \
-CFLAGS -fprofile-generate -LDFLAGS -fprofile-generate
or, if calling make yourself, add -fprofile-generate appropriately to your
Or, if calling make yourself, add -fprofile-generate appropriately to your
Makefile.
2. Run your simulation. This will create \*.gcda file(s) in the same
@ -496,6 +495,6 @@ documentation. The process in GCC 10 was as follows:
or, if calling make yourself, add these CFLAGS switches appropriately to
your Makefile.
Clang and GCC also support -fauto-profile which uses sample-based
Clang and GCC also support -fauto-profile, which uses sample-based
feedback-directed optimization. See the appropriate compiler
documentation.

164
docs/guide/verilating.rst
View File

@ -8,7 +8,7 @@ Verilating
Verilator may be used in five major ways:
* With the :vlopt:`--cc` or :vlopt:`--sc` options, Verilator will translate
the design into C++ or SystemC code respectively. See :ref:`C++ and
the design into C++ or SystemC code, respectively. See :ref:`C++ and
SystemC Generation`.
* With the :vlopt:`--lint-only` option, Verilator will lint the design to
@ -19,8 +19,8 @@ Verilator may be used in five major ways:
:file:`docs/xml.rst` in the distribution.
* With the :vlopt:`-E` option, Verilator will preprocess the code according
to IEEE preprocessing rules, and write the output to standard out. This
is useful to feed other tools, and to debug how "\`define" statements are
to IEEE preprocessing rules and write the output to standard out. This
is useful to feed other tools and to debug how "\`define" statements are
expanded.
@ -34,10 +34,10 @@ Verilator will translate a SystemVerilog design into C++ with the
When using these options:
#. Verilator reads the input Verilog code, determines all "top modules" that
is modules or programs that are not used as instances under other cells.
If :vlopt:`--top-module` is used, then that determines the top module and
all other top modules are removed, otherwise a :vlopt:`MULTITOP` warning
#. Verilator reads the input Verilog code and determines all "top modules", that
is, modules or programs that are not used as instances under other cells.
If :vlopt:`--top-module` is used, then that determines the top module, and
all other top modules are removed; otherwise a :vlopt:`MULTITOP` warning
is given.
#. Verilator writes the C++/SystemC code to output files into the
@ -46,13 +46,13 @@ When using these options:
top module.
#. If :vlopt:`--exe` is used, Verilator creates makefiles to generate a
simulation executable, otherwise it creates makefiles to generate an
simulation executable, otherwise, it creates makefiles to generate an
archive (.a) containing the objects.
#. If :vlopt:`--build` option was used, it calls :ref:`GNU Make` or
:ref:`CMake` to build the model.
Once a model is built it is then typically run, see :ref:`Simulating`.
Once a model is built, it is then typically run, see :ref:`Simulating`.
.. _Hierarchical Verilation:
@ -60,14 +60,14 @@ Once a model is built it is then typically run, see :ref:`Simulating`.
Hierarchical Verilation
=======================
Large designs may take long (e.g. 10+ minutes) and huge memory (e.g. 100+
Large designs may take long (e.g., 10+ minutes) and huge memory (e.g., 100+
GB) to Verilate. In hierarchical mode, the user manually selects some
large lower-level hierarchy blocks to separate from the larger design. For
example a core may be the hierarchy block, and separated out of a
multi-core SoC.
example, a core may be the hierarchy block separated out of a multi-core
SoC design.
Verilator is run in hierarchical mode on the whole SoC. Verilator will
make two models, one for the CPU hierarchy block, and one for the SoC. The
make two models, one for the CPU hierarchy block and one for the SoC. The
Verilated code for the SoC will automatically call the CPU Verilated model.
The current hierarchical Verilation is based on :vlopt:`--lib-create`. Each
@ -78,16 +78,16 @@ blocks will see a tiny wrapper generated by :vlopt:`--lib-create`.
Usage
-----
Users need to mark one or more moderate size module as hierarchy block(s).
Users need to mark one or more moderate-size modules as hierarchy block(s).
There are two ways to mark a module:
* Write :option:`/*verilator&32;hier_block*/` metacomment in HDL code.
* Add a :option:`hier_block` line in a the :ref:`Configuration Files`.
* Add a :option:`hier_block` line in the :ref:`Configuration Files`.
Then pass the :vlopt:`--hierarchical` option to Verilator
Then pass the :vlopt:`--hierarchical` option to Verilator.
Compilation is the same as when not using hierarchical mode.
The compilation is the same as when not using hierarchical mode.
.. code-block:: bash
@ -97,21 +97,20 @@ Compilation is the same as when not using hierarchical mode.
Limitations
-----------
Hierarchy blocks have some limitations including:
Hierarchy blocks have some limitations, including:
* The hierarchy block cannot be accessed using dot (.) from upper module(s)
or other hierarchy blocks.
* The hierarchy block cannot be accessed using dot (.) from the upper
module(s) or other hierarchy blocks.
* Signals in the block cannot be traced.
* Modport cannot be used at the hierarchical block boundary.
* The simulation speed is likely to not be as fast as flat Verilation, in
which all modules are globally scheduled.
* The simulation speed is likely not as fast as flat Verilation, in which
all modules are globally scheduled.
* Generated clocks may not work correctly if they are generated in the
hierarchical model and pass up into another hierarchical model or the top
module.
* Generated clocks may not work correctly if generated in the hierarchical
model and passed into another hierarchical model or the top module.
* Delays are not allowed in hierarchy blocks.
@ -130,8 +129,8 @@ Overlapping Verilation and Compilation
--------------------------------------
Verilator needs to run 2 + *N* times in hierarchical Verilation, where *N*
is the number of hierarchy blocks. One of the two is for the top module
which refers wrappers of all other hierarchy blocks. The second one of the
is the number of hierarchy blocks. One of the two is for the top module,
which refers to the wrappers of all other hierarchy blocks. The second of the
two is the initial run that searches modules marked with
:option:`/*verilator&32;hier_block*/` metacomment and creates a plan and
write in :file:`{prefix}_hier.mk`. This initial run internally invokes
@ -153,19 +152,19 @@ Verilator supports cross-compiling Verilated code. This is generally used
to run Verilator on a Linux system and produce C++ code that is then compiled
on Windows.
Cross compilation involves up to three different OSes. The build system is
where you configured and compiled Verilator, the host system where you run
Verilator, and the target system where you compile the Verilated code and
run the simulation.
Cross-compilation involves up to three different OSes. The build system is
where you configure and compile Verilator, the host system is where you run
Verilator, and the target system is where you compile the Verilated code
and run the simulation.
Currently, Verilator requires the build and host system type to be the
Verilator requires the build and host system types to be the
same, though the target system type may be different. To support this,
:command:`./configure` and make Verilator on the build system. Then, run
Verilator on the host system. Finally, the output of Verilator may be
compiled on the different target system.
To support this, none of the files that Verilator produces will reference
any configure generated build-system specific files, such as
any configure-generated build-system-specific files, such as
:file:`config.h` (which is renamed in Verilator to :file:`config_build.h`
to reduce confusion.) The disadvantage of this approach is that
:file:`include/verilatedos.h` must self-detect the requirements of the
@ -183,29 +182,29 @@ Multithreading
Verilator supports multithreaded simulation models.
With :vlopt:`--threads 1 <--threads>`, the generated model is single
threaded, however the support libraries are multithread safe. This allows
different instantiations of model(s) to potentially each be run under a
different thread. All threading is the responsibility of the user's C++
testbench.
With :vlopt:`--threads 1 <--threads>`, the generated model is
single-threaded; however, the support libraries are multithread safe. This
allows different instantiations of the model(s) to potentially each be run
under a different thread. All threading is the responsibility of the user's
C++ testbench.
With :vlopt:`--threads {N} <--threads>`, where N is at least 2, the
generated model will be designed to run in parallel on N threads. The
thread calling eval() provides one of those threads, and the generated
model will create and manage the other N-1 threads. It's the client's
responsibility not to oversubscribe the available CPU cores. Under CPU
oversubscription, the Verilated model should not livelock nor deadlock,
oversubscription, the Verilated model should not livelock nor deadlock;
however, you can expect performance to be far worse than it would be with
proper ratio of threads and CPU cores.
the proper ratio of threads and CPU cores.
The thread used for constructing a model must be the same thread that calls
:code:`eval()` into the model, this is called the "eval thread". The thread
used to perform certain global operations such as saving and tracing must
be done by a "main thread". In most cases the eval thread and main thread
:code:`eval()` into the model; this is called the "eval thread". The thread
used to perform certain global operations, such as saving and tracing, must
be done by a "main thread". In most cases, the eval thread and main thread
are the same thread (i.e. the user's top C++ testbench runs on a single
thread), but this is not required.
When making frequent use of DPI imported functions in a multi-threaded
When making frequent use of DPI imported functions in a multithreaded
model, it may be beneficial to performance to adjust the
:vlopt:`--instr-count-dpi` option based on some experimentation. This
influences the partitioning of the model by adjusting the assumed execution
@ -218,24 +217,24 @@ with :vlopt:`--threads`, and is executed on the same thread pool as the model.
The :vlopt:`--trace-threads` options can be used with :vlopt:`--trace-fst`
to offload FST tracing using multiple threads. If :vlopt:`--trace-threads` is
given without :vlopt:`--threads`, then :vlopt:`--trace-threads` will imply
:vlopt:`--threads 1 <--threads>`, i.e.: the support libraries will be
:vlopt:`--threads 1 <--threads>`, i.e., the support libraries will be
thread safe.
With :vlopt:`--trace-threads 0 <--trace-threads>`, trace dumps are produced
on the main thread. This again gives the highest single thread performance.
on the main thread. This again gives the highest single-thread performance.
With :vlopt:`--trace-threads {N} <--trace-threads>`, where N is at least 1,
up to N additional threads will be created and managed by the trace files
(e.g.: VerilatedFstC), to offload construction of the trace dump. The main
(e.g., VerilatedFstC), to offload construction of the trace dump. The main
thread will be released to proceed with execution as soon as possible, though
some blocking of the main thread is still necessary while capturing the
some main thread blocking is still necessary while capturing the
trace. FST tracing can utilize up to 2 offload threads, so there is no use
of setting :vlopt:`--trace-threads` higher than 2 at the moment.
When running a multithreaded model, the default Linux task scheduler often
works against the model, by assuming threads are short lived, and thus
often schedules threads using multiple hyperthreads within the same
physical core. For best performance use the :command:`numactl` program to
works against the model by assuming short-lived threads and thus
it often schedules threads using multiple hyperthreads within the same
physical core. For best performance, use the :command:`numactl` program to
(when the threading count fits) select unique physical cores on the same
socket. The same applies for :vlopt:`--trace-threads` as well.
@ -247,8 +246,8 @@ As an example, if a model was Verilated with
egrep 'processor|physical id|core id' /proc/cpuinfo
To select cores 0, 1, 2, and 3 that are all located on the same socket (0)
but different physical cores. (Also useful is
:command:`numactl --hardware`, or :command:`lscpu` but those doesn't show
but have different physical cores. (Also useful is
:command:`numactl --hardware`, or :command:`lscpu`, but those don't show
hyperthreading cores.) Then we execute:
.. code-block:: bash
@ -256,8 +255,8 @@ hyperthreading cores.) Then we execute:
numactl -m 0 -C 0,1,2,3 -- verilated_executable_name
This will limit memory to socket 0, and threads to cores 0, 1, 2, 3,
(presumably on socket 0) optimizing performance. Of course this must be
adjusted if you want another simulator using e.g. socket 1, or if you
(presumably on socket 0), optimizing performance. Of course, this must be
adjusted if you want another simulator to use, e.g., socket 1, or if you
Verilated with a different number of threads. To see what CPUs are
actually used, use :vlopt:`--prof-exec`.
@ -265,19 +264,19 @@ actually used, use :vlopt:`--prof-exec`.
Multithreaded Verilog and Library Support
-----------------------------------------
$display/$stop/$finish are delayed until the end of an eval() call in order
$display/$stop/$finish are delayed until the end of an eval() call
to maintain ordering between threads. This may result in additional tasks
completing after the $stop or $finish.
If using :vlopt:`--coverage`, the coverage routines are fully thread safe.
If using :vlopt:`--coverage`, the coverage routines are fully thread-safe.
If using the DPI, Verilator assumes pure DPI imports are thread safe,
If using the DPI, Verilator assumes pure DPI imports are thread-safe,
balancing performance versus safety. See :vlopt:`--threads-dpi`.
If using :vlopt:`--savable`, the save/restore classes are not multithreaded
and must be called only by the eval thread.
If using :vlopt:`--sc`, the SystemC kernel is not thread safe, therefore
If using :vlopt:`--sc`, the SystemC kernel is not thread-safe; therefore,
the eval thread and main thread must be the same.
If using :vlopt:`--trace`, the tracing classes must be constructed and
@ -297,8 +296,8 @@ Verilator defaults to creating GNU Make makefiles for the model. Verilator
will call make automatically when the :vlopt:'--build' option is used.
If calling Verilator from a makefile, the :vlopt:'-MMD' option will create
a dependency file which will allow Make to only run Verilator if input
Verilog files change.
a dependency file, allowing Make to only run Verilator if input Verilog
files change.
.. _CMake:
@ -307,8 +306,8 @@ CMake
Verilator can be run using CMake, which takes care of both running
Verilator and compiling the output. There is a CMake example in the
examples/ directory. The following is a minimal CMakeLists.txt that would
build the code listed in :ref:`Example C++ Execution`
:file:`examples/` directory. The following is a minimal CMakeLists.txt that
would build the code listed in :ref:`Example C++ Execution`
.. code-block:: CMake
@ -320,8 +319,8 @@ build the code listed in :ref:`Example C++ Execution`
:code:`find_package` will automatically find an installed copy of
Verilator, or use a local build if VERILATOR_ROOT is set.
It is recommended to use CMake >= 3.12 and the Ninja generator, though
other combinations should work. To build with CMake, change to the folder
Using CMake >= 3.12 and the Ninja generator is recommended, though other
combinations should work. To build with CMake, change to the folder
containing CMakeLists.txt and run:
.. code-block:: bash
@ -340,14 +339,14 @@ Or to build with your system default generator:
cmake ..
cmake --build .
If you're building the example you should have an executable to run:
If you're building the example, you should have an executable to run:
.. code-block:: bash
./Vour
The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT and
VERILATOR_BIN to the appropriate values, and also creates a verilate()
The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT,
and VERILATOR_BIN to the appropriate values and creates a verilate()
function. verilate() will automatically create custom commands to run
Verilator and add the generated C++ sources to the target specified.
@ -362,14 +361,14 @@ Verilate in CMake
[OPT_GLOBAL ..] [DIRECTORY dir] [THREADS num]
[TRACE_THREADS num] [VERILATOR_ARGS ...])
Lowercase and ... should be replaced with arguments, the uppercase parts
delimit the arguments and can be passed in any order, or left out entirely
Lowercase and ... should be replaced with arguments; the uppercase parts
delimit the arguments and can be passed in any order or left out entirely
if optional.
verilate(target ...) can be called multiple times to add other Verilog
modules to an executable or library target.
When generating Verilated SystemC sources, you should also include the
When generating Verilated SystemC sources, you should list the
SystemC include directories and link to the SystemC libraries.
.. describe:: target
@ -379,7 +378,7 @@ SystemC include directories and link to the SystemC libraries.
.. describe:: COVERAGE
Optional. Enables coverage if present, equivalent to "VERILATOR_ARGS
--coverage"
--coverage".
.. describe:: DIRECTORY
@ -407,22 +406,22 @@ SystemC include directories and link to the SystemC libraries.
.. describe:: PREFIX
Optional. Sets the Verilator output prefix. Defaults to the name of the
first source file with a "V" prepended. Must be unique in each call to
verilate(), so this is necessary if you build a module multiple times
with different parameters. Must be a valid C++ identifier, i.e. contains
no white space and only characters A-Z, a-z, 0-9 or _.
first source file with a "V" prepended. It must be unique in each call
to verilate(), so this is necessary if you build a module multiple times
with different parameters. It must be a valid C++ identifier, i.e., it
contains no white space and only characters A-Z, a-z, 0-9 or _.
.. describe:: SOURCES
List of Verilog files to Verilate. Must have at least one file.
List of Verilog files to Verilate. You must provide at least one file.
.. describe:: SYSTEMC
Optional. Enables SystemC mode, defaults to C++ if not specified.
When using Accellera's SystemC with CMake support, a CMake target is
available that simplifies the SystemC steps. This will only work if the
SystemC installation can be found by CMake. This can be configured by
available that simplifies the SystemC steps. This will only work if
CMake can find the SystemC installation, and this can be configured by
setting the CMAKE_PREFIX_PATH variable during CMake configuration.
Don't forget to set the same C++ standard for the Verilated sources as
@ -431,12 +430,11 @@ SystemC include directories and link to the SystemC libraries.
.. describe:: THREADS
Optional. Generated a multi-threaded model, same as "--threads".
Optional. Enable a multithreaded model; see :vlopt:`--threads`.
.. describe:: TRACE_THREADS
Optional. Generated multi-threaded FST trace dumping, same as
"--trace-threads".
Optional. Enable multithreaded FST trace; see :vlopt:`--trace-threads`.
.. describe:: TOP_MODULE
@ -456,7 +454,7 @@ SystemC include directories and link to the SystemC libraries.
.. describe:: VERILATOR_ARGS
Optional. Extra arguments to Verilator. Do not specify :vlopt:`--Mdir`
or :vlopt:`--prefix` here, use DIRECTORY or PREFIX.
or :vlopt:`--prefix` here; use DIRECTORY or PREFIX.
SystemC Link in CMake

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@ -45,6 +45,7 @@ Cochrane
Cuan
Cygwin
DErrico
DFG
Da
Danilo
Dannoritzer
@ -606,6 +607,7 @@ ifndef
impot
incdir
includer
incrementing
inferfaces
inhibitSim
initarray
@ -646,6 +648,7 @@ localparams
localtime
logicals
longint
lossy
lsb
lvalue
lxt