When using --lib-create, disable tracing hash/internals. Partial (#3200).
This commit is contained in:
Wilson Snyder
parent
899de9a282
commit
c0892dd11c
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@ -197,15 +197,21 @@ private:
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+ "_protectlib_final(chandle handle__V);\n\n");
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// Local variables
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txtp->addText(fl, "chandle handle__V;\n\n");
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// Avoid tracing handle, as it is not a stable value, so breaks vcddiff
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// Likewise other internals aren't interesting to the user
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txtp->addText(fl, "// verilator tracing_off\n");
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txtp->addText(fl, "chandle handle__V;\n");
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txtp->addText(fl, "time last_combo_seqnum__V;\n");
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if (m_hasClk) txtp->addText(fl, "time last_seq_seqnum__V;\n");
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txtp->addText(fl, "\n");
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m_comboDeclsp = new AstTextBlock(fl);
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txtp->addNodep(m_comboDeclsp);
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m_seqDeclsp = new AstTextBlock(fl);
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txtp->addNodep(m_seqDeclsp);
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m_tmpDeclsp = new AstTextBlock(fl);
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txtp->addNodep(m_tmpDeclsp);
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txtp->addText(fl, "\ntime last_combo_seqnum__V;\n");
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if (m_hasClk) txtp->addText(fl, "time last_seq_seqnum__V;\n\n");
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// CPP hash value
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addComment(txtp, fl, "Hash value to make sure this file and the corresponding");
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@ -0,0 +1,251 @@
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$version Generated by VerilatedVcd $end
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$date Sun Nov 14 10:12:01 2021 $end
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$timescale 1ps $end
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$scope module top $end
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$var wire 1 ) clk $end
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$scope module t $end
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$var wire 1 ) clk $end
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$var wire 32 + count [31:0] $end
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$var wire 8 # out0 [7:0] $end
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$var wire 8 $ out1 [7:0] $end
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$var wire 8 % out2 [7:0] $end
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$var wire 8 & out3 [7:0] $end
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$var wire 8 * out3_2 [7:0] $end
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$var wire 8 ' out5 [7:0] $end
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$var wire 8 ( out6 [7:0] $end
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$scope module i_delay0 $end
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$var wire 1 ) clk $end
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$var wire 8 & in [7:0] $end
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$var wire 8 ' out [7:0] $end
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$upscope $end
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$scope module i_delay1 $end
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$var wire 1 ) clk $end
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$var wire 8 ' in [7:0] $end
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$var wire 8 ( out [7:0] $end
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$upscope $end
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$scope module i_sub0 $end
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$var wire 1 ) clk $end
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$var wire 8 & in [7:0] $end
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$var wire 8 # out [7:0] $end
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$scope module i_sub0 $end
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$var wire 1 ) clk $end
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$var wire 8 & in [7:0] $end
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$var wire 8 # out [7:0] $end
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$upscope $end
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$upscope $end
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$scope module i_sub1 $end
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$var wire 1 ) clk $end
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$var wire 8 # in [7:0] $end
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$var wire 8 $ out [7:0] $end
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$upscope $end
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$scope module i_sub2 $end
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$var wire 1 ) clk $end
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$var wire 8 $ in [7:0] $end
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$var wire 8 % out [7:0] $end
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$upscope $end
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$scope module i_sub3 $end
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$var wire 1 ) clk $end
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$var wire 8 % in [7:0] $end
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$var wire 8 & out [7:0] $end
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$upscope $end
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$scope module i_sub3_2 $end
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$var wire 1 ) clk $end
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$var wire 8 % in [7:0] $end
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$var wire 8 * out [7:0] $end
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$upscope $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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b00000000 #
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b00000000 $
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b00000000 %
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b00000000 &
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b00000000 '
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b00000000 (
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0)
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b00000000 *
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b00000000000000000000000000000000 +
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#10
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b00000001 $
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b00000010 %
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b00000010 &
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1)
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b00000010 *
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b00000000000000000000000000000001 +
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#15
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0)
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#20
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b00000010 #
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b00000101 %
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b00000011 &
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1)
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b00000011 *
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b00000000000000000000000000000010 +
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#25
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0)
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#30
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b00000011 #
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b00000011 $
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b00000111 %
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b00000101 &
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b00000010 '
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1)
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b00000101 *
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b00000000000000000000000000000011 +
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#35
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0)
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#40
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b00000101 #
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b00000100 $
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b00001000 %
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b00001000 &
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b00000011 '
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1)
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b00001000 *
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b00000000000000000000000000000100 +
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#45
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0)
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#50
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b00001000 #
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b00000110 $
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b00001010 &
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b00000101 '
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1)
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b00001010 *
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b00000000000000000000000000000101 +
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#55
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0)
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#60
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b00001010 #
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b00001001 $
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b00001010 %
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b00001011 &
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b00001000 '
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b00000010 (
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1)
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b00001011 *
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b00000000000000000000000000000110 +
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#65
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0)
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#70
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b00001011 #
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b00001011 $
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b00001011 %
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b00001010 '
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b00000011 (
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1)
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b00000000000000000000000000000111 +
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#75
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0)
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#80
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b00001100 $
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b00001101 %
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b00001101 &
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b00001011 '
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b00000101 (
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1)
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b00001101 *
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b00000000000000000000000000001000 +
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#85
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0)
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#90
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b00001101 #
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b00010000 %
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b00001110 &
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b00001000 (
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1)
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b00001110 *
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b00000000000000000000000000001001 +
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#95
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0)
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#100
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b00001110 #
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b00001110 $
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b00010010 %
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b00010000 &
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b00001101 '
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b00001010 (
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1)
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b00010000 *
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b00000000000000000000000000001010 +
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#105
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0)
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#110
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b00010000 #
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b00001111 $
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b00010011 %
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b00010011 &
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b00001110 '
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b00001011 (
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1)
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b00010011 *
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b00000000000000000000000000001011 +
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#115
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0)
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#120
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b00010011 #
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b00010001 $
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b00010101 &
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b00010000 '
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1)
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b00010101 *
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b00000000000000000000000000001100 +
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#125
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0)
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#130
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b00010101 #
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b00010100 $
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b00010101 %
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b00010110 &
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b00010011 '
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b00001101 (
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1)
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b00010110 *
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b00000000000000000000000000001101 +
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#135
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0)
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#140
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b00010110 #
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b00010110 $
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b00010110 %
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b00010101 '
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b00001110 (
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1)
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b00000000000000000000000000001110 +
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#145
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0)
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#150
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b00010111 $
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b00011000 %
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b00011000 &
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b00010110 '
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b00010000 (
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1)
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b00011000 *
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b00000000000000000000000000001111 +
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#155
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0)
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#160
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b00011000 #
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b00011011 %
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b00011001 &
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b00010011 (
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1)
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b00011001 *
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b00000000000000000000000000010000 +
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#165
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0)
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#170
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b00011001 #
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b00011001 $
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b00011101 %
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b00011011 &
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b00011000 '
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b00010101 (
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1)
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b00011011 *
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b00000000000000000000000000010001 +
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@ -0,0 +1,35 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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scenarios(vlt_all => 1);
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top_filename("t/t_hier_block.v");
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# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
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# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
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# So use 6 threads here though it's not optimal in performace wise, but ok.
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compile(
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v_flags2 => ['t/t_hier_block.cpp'],
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verilator_flags2 => [($Self->{vltmt} ? ' --threads 6' : ''),
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'--hierarchical',
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'--Wno-TIMESCALEMOD',
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'--trace',
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'--no-trace-underscore', # To avoid handle mismatches
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],
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);
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execute(
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check_finished => 1,
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);
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vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename});
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ok(1);
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1;
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