Fix tracing parameters overridden with -G (#3723).

Changes

@@ -18,6 +18,7 @@ Verilator 5.003 devel
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd]
 * Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon]
+* Fix tracing parameters overridden with -G (#3723). [Iztok Jeras]
 
 
 Verilator 5.002 2022-10-29

src/V3LinkDot.cpp

@@ -1220,20 +1220,15 @@ class LinkDotFindVisitor final : public VNVisitor {
                     && (m_statep->rootEntp()->nodep() == m_modSymp->parentp()->nodep())) {
                     // This is the toplevel module. Check for command line overwrites of parameters
                     // We first search if the parameter is overwritten and then replace it with a
-                    // new value. It will keep the same FileLine information.
+                    // new value.
                     if (v3Global.opt.hasParameter(nodep->name())) {
-                        AstVar* const newp = new AstVar{
-                            nodep->fileline(), VVarType{VVarType::GPARAM}, nodep->name(), nodep};
-                        newp->combineType(nodep);
                         const string svalue = v3Global.opt.parameter(nodep->name());
                         if (AstNode* const valuep
                             = AstConst::parseParamLiteral(nodep->fileline(), svalue)) {
-                            newp->valuep(valuep);
                             UINFO(9, "       replace parameter " << nodep << endl);
-                            UINFO(9, "       with " << newp << endl);
-                            nodep->replaceWith(newp);
-                            VL_DO_DANGLING(pushDeletep(nodep), nodep);
-                            nodep = newp;
+                            UINFO(9, "       with " << valuep << endl);
+                            if (nodep->valuep()) pushDeletep(nodep->valuep()->unlinkFrBack());
+                            nodep->valuep(valuep);
                         }
                     }
                 }

test_regress/t/t_trace_param_override.out

@@ -0,0 +1,16 @@
+$version Generated by VerilatedVcd $end
+$date Thu Nov 10 19:19:51 2022 $end
+$timescale 1ps $end
+
+ $scope module TOP $end
+  $scope module t $end
+   $var wire 32 $ PORIG [31:0] $end
+   $var wire 32 # POVERRODE [31:0] $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000011111 #
+b00000000000000000000000000010000 $

test_regress/t/t_trace_param_override.pl

@@ -0,0 +1,25 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["--exe --main --trace -GPOVERRODE=31"],
+    make_main => 0,
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+vcd_identical($Self->trace_filename, $Self->{golden_filename});
+
+ok(1);
+1;

test_regress/t/t_trace_param_override.v

@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define STRINGIFY(x) `"x`"
+
+module t #(
+           parameter int POVERRODE = 16,
+           parameter int PORIG = 16
+           ) (/*AUTOARG*/);
+
+   initial begin
+      $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+      $dumpvars;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule