Tests: Add unsupported t_class_static_member tests.

This commit is contained in:
Wilson Snyder 2022-01-02 09:43:26 -05:00
parent bf972963f4
commit 028737cde8
6 changed files with 168 additions and 0 deletions

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%Error-UNSUPPORTED: t/t_class_static_member.v:12:15: Unsupported: 'static' class members
: ... In instance t
12 | static int c_st = 22;
| ^~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error: Exiting due to

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#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
fails => $Self->{vlt_all}, # Verilator unsupported, bug546
expect_filename => $Self->{golden_filename},
);
execute(
check_finished => 1,
) if !$Self->{vlt_all};
ok(1);
1;

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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
class Cls;
int c_no = 2;
//automatic int c_au = 2; // automatic not a legal keyword here
static int c_st = 22;
function int f_c_no ();
++c_no; return c_no;
endfunction
function int f_c_st ();
++c_st; return c_st;
endfunction
static function int f_cs_st ();
++c_st; return c_st;
endfunction
endclass
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
Cls a = new;
Cls b = new;
int v;
initial begin
v = a.f_c_no(); `checkh(v, 3);
v = a.f_c_no(); `checkh(v, 4);
v = b.f_c_no(); `checkh(v, 3);
v = b.f_c_no(); `checkh(v, 4);
v = a.f_c_st(); `checkh(v, 23);
v = a.f_c_st(); `checkh(v, 24);
v = b.f_c_st(); `checkh(v, 25);
v = b.f_c_st(); `checkh(v, 26);
//
v = Cls::f_cs_st(); `checkh(v, 27);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

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%Error: t/t_class_static_member_pkg.v:51:16: Syntax Error: Not expecting CLASSORPACKAGEREF under a DOT in dotted expression
51 | v = Pkg::Cls::f_cs_st(); do if ((v) !== (27)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_class_static_member_pkg.v",51, (v), (27)); $stop; end while(0);;
| ^~~
%Error: Exiting due to

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#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
fails => $Self->{vlt_all}, # Verilator unsupported, bug546
expect_filename => $Self->{golden_filename},
);
execute(
check_finished => 1,
) if !$Self->{vlt_all};
ok(1);
1;

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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
package Pkg;
class Cls;
int c_no = 2;
//automatic int c_au = 2; // automatic not a legal keyword here
static int c_st = 22;
function int f_c_no ();
++c_no; return c_no;
endfunction
function int f_c_st ();
++c_st; return c_st;
endfunction
static function int f_cs_st ();
++c_st; return c_st;
endfunction
endclass
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
Pkg::Cls a = new;
Pkg::Cls b = new;
int v;
initial begin
v = a.f_c_no(); `checkh(v, 3);
v = a.f_c_no(); `checkh(v, 4);
v = b.f_c_no(); `checkh(v, 3);
v = b.f_c_no(); `checkh(v, 4);
v = a.f_c_st(); `checkh(v, 23);
v = a.f_c_st(); `checkh(v, 24);
v = b.f_c_st(); `checkh(v, 25);
v = b.f_c_st(); `checkh(v, 26);
//
v = Pkg::Cls::f_cs_st(); `checkh(v, 27);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule