Tests: Add unsupported t_class_static_member tests.
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%Error-UNSUPPORTED: t/t_class_static_member.v:12:15: Unsupported: 'static' class members
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: ... In instance t
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12 | static int c_st = 22;
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| ^~~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error: Exiting due to
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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fails => $Self->{vlt_all}, # Verilator unsupported, bug546
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expect_filename => $Self->{golden_filename},
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);
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execute(
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check_finished => 1,
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) if !$Self->{vlt_all};
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ok(1);
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1;
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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class Cls;
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int c_no = 2;
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//automatic int c_au = 2; // automatic not a legal keyword here
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static int c_st = 22;
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function int f_c_no ();
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++c_no; return c_no;
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endfunction
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function int f_c_st ();
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++c_st; return c_st;
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endfunction
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static function int f_cs_st ();
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++c_st; return c_st;
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endfunction
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endclass
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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Cls a = new;
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Cls b = new;
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int v;
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initial begin
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v = a.f_c_no(); `checkh(v, 3);
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v = a.f_c_no(); `checkh(v, 4);
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v = b.f_c_no(); `checkh(v, 3);
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v = b.f_c_no(); `checkh(v, 4);
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v = a.f_c_st(); `checkh(v, 23);
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v = a.f_c_st(); `checkh(v, 24);
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v = b.f_c_st(); `checkh(v, 25);
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v = b.f_c_st(); `checkh(v, 26);
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//
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v = Cls::f_cs_st(); `checkh(v, 27);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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%Error: t/t_class_static_member_pkg.v:51:16: Syntax Error: Not expecting CLASSORPACKAGEREF under a DOT in dotted expression
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51 | v = Pkg::Cls::f_cs_st(); do if ((v) !== (27)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_class_static_member_pkg.v",51, (v), (27)); $stop; end while(0);;
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| ^~~
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%Error: Exiting due to
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@ -0,0 +1,23 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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fails => $Self->{vlt_all}, # Verilator unsupported, bug546
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expect_filename => $Self->{golden_filename},
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);
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execute(
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check_finished => 1,
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) if !$Self->{vlt_all};
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ok(1);
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1;
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@ -0,0 +1,57 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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package Pkg;
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class Cls;
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int c_no = 2;
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//automatic int c_au = 2; // automatic not a legal keyword here
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static int c_st = 22;
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function int f_c_no ();
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++c_no; return c_no;
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endfunction
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function int f_c_st ();
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++c_st; return c_st;
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endfunction
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static function int f_cs_st ();
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++c_st; return c_st;
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endfunction
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endclass
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endpackage
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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Pkg::Cls a = new;
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Pkg::Cls b = new;
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int v;
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initial begin
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v = a.f_c_no(); `checkh(v, 3);
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v = a.f_c_no(); `checkh(v, 4);
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v = b.f_c_no(); `checkh(v, 3);
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v = b.f_c_no(); `checkh(v, 4);
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v = a.f_c_st(); `checkh(v, 23);
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v = a.f_c_st(); `checkh(v, 24);
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v = b.f_c_st(); `checkh(v, 25);
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v = b.f_c_st(); `checkh(v, 26);
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//
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v = Pkg::Cls::f_cs_st(); `checkh(v, 27);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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