Tests: Add t_class_param_mod.pl

This commit is contained in:
Wilson Snyder 2021-12-12 19:49:06 -05:00
parent d753f36ebc
commit aa8423ba46
4 changed files with 104 additions and 13 deletions

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@ -1,14 +1,5 @@
%Error-UNSUPPORTED: t/t_class_param.v:22:11: Unsupported: parameterized classes
: ... In instance t
22 | Cls #(.P(4)) c4;
| ^
%Error-UNSUPPORTED: t/t_class_param.v:18:30: Unsupported: class parameters
18 | localparam P = PMINUS1 + 1;
| ^
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_class_param.v:7:23: Unsupported: class parameters
: ... In instance t
7 | class Cls #(parameter P = 12);
| ^
%Error-UNSUPPORTED: t/t_class_param.v:17:14: Unsupported: parameterized classes
: ... In instance t
17 | typedef Cls#(5) Cls5_t;
| ^
%Error: Exiting due to

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@ -14,26 +14,41 @@ class Cls #(parameter P = 12);
endfunction
endclass
class Wrap #(parameter PMINUS1 = 3);
localparam P = PMINUS1 + 1;
Cls#(P) c1;
function int get_p;
return c1.get_p();
endfunction
endclass
typedef Cls#(5) Cls5_t;
// See also t_class_param_mod.v
module t (/*AUTOARG*/);
Cls c12;
Cls #(.P(4)) c4;
Cls5_t c5;
Wrap #(.PMINUS1(15)) w16;
initial begin
c12 = new;
c4 = new;
c5 = new;
w16 = new;
if (c12.P != 12) $stop;
if (c4.P != 4) $stop;
if (c5.P != 5) $stop;
if (c12.get_p() != 12) $stop;
if (c4.get_p() != 4) $stop;
if (c5.get_p() != 5) $stop;
if (w16.get_p() != 16) $stop;
// verilator lint_off WIDTH
c12.member = 32'haaaaaaaa;
c4.member = 32'haaaaaaaa;
c5.member = 32'haaaaaaaa;
// verilator lint_on WIDTH
if (c12.member != 12'haaa) $stop;
if (c4.member != 4'ha) $stop;

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@ -0,0 +1,22 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2020 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
fails => $Self->{vlt_all},
);
execute(
check_finished => 1,
) if !$Self->{vlt_all};
ok(1);
1;

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@ -0,0 +1,63 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// See also t_class_param.v
module t (/*AUTOARG*/);
class Cls #(parameter P = 12);
bit [P-1:0] member;
function bit [P-1:0] get_member;
return member;
endfunction
function int get_p;
return P;
endfunction
endclass
class Wrap #(parameter PMINUS1 = 3);
localparam P = PMINUS1 + 1;
Cls#(P) c1;
function int get_p;
return c1.get_p();
endfunction
endclass
typedef Cls#(5) Cls5_t;
Cls c12;
Cls #(.P(4)) c4;
Cls5_t c5;
Wrap #(.PMINUS1(15)) w16;
initial begin
c12 = new;
c4 = new;
c5 = new;
w16 = new;
if (c12.P != 12) $stop;
if (c4.P != 4) $stop;
if (c5.P != 5) $stop;
if (c12.get_p() != 12) $stop;
if (c4.get_p() != 4) $stop;
if (c5.get_p() != 5) $stop;
if (w16.get_p() != 16) $stop;
// verilator lint_off WIDTH
c12.member = 32'haaaaaaaa;
c4.member = 32'haaaaaaaa;
c5.member = 32'haaaaaaaa;
// verilator lint_on WIDTH
if (c12.member != 12'haaa) $stop;
if (c4.member != 4'ha) $stop;
if (c12.get_member() != 12'haaa) $stop;
if (c4.get_member() != 4'ha) $stop;
if ($sformatf("%p", c12) != "'{member:'haaa}") $stop;
if ($sformatf("%p", c4) != "'{member:'ha}") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule