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Tests: rename

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This commit is contained in:
Wilson Snyder
2022-12-08 07:23:53 -05:00
parent 4b6e15d0eb
commit 2dc0053ea4
2 changed files with 1 additions and 0 deletions
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test_regress/t/t_timing_bug3781.pl → test_regress/t/t_timing_dlyassign.pl
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test_regress/t/t_timing_bug3781.v → test_regress/t/t_timing_dlyassign.v
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@@ -4,6 +4,7 @@
// any use, without warranty, 2022 by Antmicro Ltd.
// SPDX-License-Identifier: CC0-1.0
// bug3781
module t;
logic clk;
logic [7:0] data;