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Fix linker errors in user-facing timing functions (#3657)
Before this change, a design verilated with `--timing` that does not actually use timing features would be emitted with `eventsPending` and `nextTimeSlot` declared in the top class. However, their definitions would be missing, leading to linker errors during design compilation. This patch makes Verilator always emit the definitions, which prevents linker errors. Trying to use `nextTimeSlot` without delays in the design will result in an error at runtime.
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+14
-16
@@ -439,22 +439,20 @@ class EmitCModel final : public EmitCFunc {
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puts("}\n");
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}
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if (v3Global.usesTiming()) {
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putSectionDelimiter("Events and timing");
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if (auto* const delaySchedp = v3Global.rootp()->delaySchedulerp()) {
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puts("bool " + topClassName() + "::eventsPending() { return !vlSymsp->TOP.");
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puts(delaySchedp->nameProtect());
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puts(".empty(); }\n\n");
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puts("uint64_t " + topClassName() + "::nextTimeSlot() { return vlSymsp->TOP.");
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puts(delaySchedp->nameProtect());
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puts(".nextTimeSlot(); }\n");
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} else {
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puts("bool " + topClassName() + "::eventsPending() { return false; }\n\n");
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puts("uint64_t " + topClassName() + "::nextTimeSlot() {\n");
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puts("VL_FATAL_MT(__FILE__, __LINE__, \"\", \"%Error: No delays in the "
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"design\");\n");
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puts("return 0;\n}\n");
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}
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putSectionDelimiter("Events and timing");
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if (auto* const delaySchedp = v3Global.rootp()->delaySchedulerp()) {
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puts("bool " + topClassName() + "::eventsPending() { return !vlSymsp->TOP.");
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puts(delaySchedp->nameProtect());
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puts(".empty(); }\n\n");
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puts("uint64_t " + topClassName() + "::nextTimeSlot() { return vlSymsp->TOP.");
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puts(delaySchedp->nameProtect());
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puts(".nextTimeSlot(); }\n");
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} else {
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puts("bool " + topClassName() + "::eventsPending() { return false; }\n\n");
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puts("uint64_t " + topClassName() + "::nextTimeSlot() {\n");
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puts("VL_FATAL_MT(__FILE__, __LINE__, \"\", \"%Error: No delays in the "
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"design\");\n");
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puts("return 0;\n}\n");
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}
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putSectionDelimiter("Utilities");
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