Fix incorrect return in DFG decomposition

Fixes #3676

src/V3DfgDecomposition.cpp

@@ -405,14 +405,14 @@ class ExtractCyclicComponents final {
                 if (!varp->hasSinks() && varp->arity() == 0) {
                     VL_DO_DANGLING(varp->unlinkDelete(dfg), varp);
                 }
-                return;
+                continue;
             }
             if (DfgVarArray* const varp = vtxp->cast<DfgVarArray>()) {
                 varp->packSources();
                 if (!varp->hasSinks() && varp->arity() == 0) {
                     VL_DO_DANGLING(varp->unlinkDelete(dfg), varp);
                 }
-                return;
+                continue;
             }
         }
     }

test_regress/t/t_dfg_3676.pl

@@ -0,0 +1,16 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Geza Lore. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile();
+
+ok(1);
+1;

test_regress/t/t_dfg_3676.v

@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Geza Lore.
+// SPDX-License-Identifier: CC0-1.0
+
+// verilator lint_off UNOPTFLAT
+
+module t(
+  input  wire [3:0]      i,
+  output wire [2:0][3:0] o
+);
+
+   wire [2:0][3:0] v;
+
+   // This circular logic used to trip up DFG decomposition
+
+   assign v[0]    = i;
+   assign v[1][0] = v[0][1] | v[0][0];
+
+   assign o[1][2] = v[0][2];
+   assign o[2][1:0] = {v[1][0] , o[1][0]};
+
+endmodule