Fischer Moseley
|
958ccadbd0
|
refactored logic analyzer working in sim
|
2024-01-05 21:43:53 -08:00 |
|
Fischer Moseley
|
a11605b2b7
|
refactor logic analyzer
|
2024-01-05 16:50:25 -08:00 |
|
Fischer Moseley
|
ee18e10ae1
|
add immediate capture mode to logic analyzer
|
2024-01-03 13:35:09 -07:00 |
|
Fischer Moseley
|
bc616fd3bf
|
inital source, imported from splat
|
2023-12-28 14:22:29 -08:00 |
|
Fischer Moseley
|
060583d8fc
|
add working io_core autogeneration
|
2023-09-04 23:03:49 -04:00 |
|
Fischer Moseley
|
49021411ea
|
add beginnings of working io_core with CDC/large inputs
|
2023-09-04 23:03:49 -04:00 |
|
Fischer Moseley
|
23418066f9
|
remove uart_rx formal
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
f902d07b1d
|
update read responses to use D as preamble
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
4abc2e2cae
|
update template naming for consistency
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
7ed4a9e6b8
|
polish uart testbenches
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
56b2442df7
|
move uart code for verification to test/
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
d580419a5b
|
remove lut_mem, clean up examples
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
112bd43963
|
remove mention of wdata/rdata
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
da4920d89d
|
fetch lab-bc on the fly, archive build outputs
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
ac23e8a599
|
make functional sim run again
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
d95ca04dd5
|
move macro functions to tasks, update to
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
6e9ca36559
|
add test case for back to back messages
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
0c942fcb59
|
finish cleaning up bridge_rx_tb
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
25b2ff0dd0
|
add first round of tweaks to bridge_rx_tb
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
1a536080f1
|
rewrite bridge_rx and add basic formal
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
38f7ee86fa
|
add uart_rx and refactor uart_tx and bridge_tx
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
df2dbf4ec6
|
update makefile to reflect new paths
|
2023-04-28 14:57:36 -04:00 |
|
Fischer Moseley
|
15aa5f469f
|
add ethernet_tx_tb
|
2023-04-28 14:57:36 -04:00 |
|
Fischer Moseley
|
2c461ed08d
|
add working ethernet_tx testbench
|
2023-04-28 14:57:36 -04:00 |
|
Fischer Moseley
|
9c5ea31d14
|
enforce consistent naming of lut_mem module
|
2023-04-28 14:57:36 -04:00 |
|
Fischer Moseley
|
b3d402c1f5
|
refactor python/hdl structure
|
2023-04-28 14:57:36 -04:00 |
|
Fischer Moseley
|
7cd8a2cfa5
|
tidy up mac stack
|
2023-04-28 14:57:36 -04:00 |
|
Fischer Moseley
|
c507f795f1
|
add ethernet_tx/rx, semi-working in hardware
|
2023-04-28 14:57:36 -04:00 |
|
Fischer Moseley
|
357b7eed94
|
refactor logic analyzer a little, add ps2_decoder example, and implement trigger_loc
|
2023-04-18 01:06:39 -04:00 |
|
Fischer Moseley
|
07624d83ee
|
move back to iverilog 13 compatability
|
2023-04-17 18:14:31 -04:00 |
|
Fischer Moseley
|
925fd915be
|
update simulation syntax for iverilog 11 compat
|
2023-04-17 18:14:31 -04:00 |
|
Fischer Moseley
|
1aa067b435
|
update logic_analyzer_tb to use only generated HDL
|
2023-04-17 18:14:31 -04:00 |
|
Fischer Moseley
|
a2ad90a66a
|
modify sim and generator, seems to work in simulation
|
2023-04-17 18:14:31 -04:00 |
|
Fischer Moseley
|
bdca8e01e7
|
add boilerplate for new modules - just gotta rewrite the fsm
|
2023-04-17 18:14:31 -04:00 |
|
Fischer Moseley
|
153ae7e3df
|
video sprite example working! kinda frankensteined tho
|
2023-04-13 17:02:55 -04:00 |
|
Fischer Moseley
|
5ceefc8da9
|
this bram core has taken my soul
|
2023-04-12 18:15:50 -04:00 |
|
Fischer Moseley
|
ba6100ce30
|
import tutorial from yesterday, add mostly working bram core
|
2023-04-12 11:47:50 -04:00 |
|
Fischer Moseley
|
3731305f63
|
keep tidying bram core
|
2023-04-10 18:03:02 -04:00 |
|
Fischer Moseley
|
db76ce3579
|
reasonably tidy BRAM core - might be dependent on icarus 13
|
2023-04-10 17:51:43 -04:00 |
|
Fischer Moseley
|
4837b2787a
|
add (half) working BRAM core example
|
2023-04-10 17:02:48 -04:00 |
|
Fischer Moseley
|
12f498dc9a
|
add cursed BRAM core implementation
|
2023-04-10 14:38:29 -04:00 |
|
Fischer Moseley
|
1710da6f87
|
update makefile to represent new functional sim locations
|
2023-04-09 22:33:58 -04:00 |
|
Fischer Moseley
|
353be7551e
|
remove all narly verilog from python! 🤠
|
2023-04-08 16:23:02 -04:00 |
|
Fischer Moseley
|
c604614428
|
autogenerate logic_analyzer and sample_mem
|
2023-04-03 23:15:09 -04:00 |
|
Fischer Moseley
|
0a4a1519c4
|
clean up inferred BRAM, trim whitespace
|
2023-04-03 21:20:58 -04:00 |
|
Fischer Moseley
|
8f08dffc70
|
consolidate logic analyzer testbench
|
2023-04-03 12:20:24 -04:00 |
|
Fischer Moseley
|
aea5a77258
|
blacken autogen test runner
|
2023-04-02 20:38:34 -04:00 |
|
Fischer Moseley
|
df4d243b9a
|
refactor test structure
|
2023-04-02 20:33:50 -04:00 |
|
Fischer Moseley
|
af295ead51
|
logic analyzer appears to kinda work in simulation. buggy, but working!
|
2023-04-02 13:54:34 -04:00 |
|
Fischer Moseley
|
edf94c9cf7
|
add api generation tests
|
2023-03-24 10:34:15 -04:00 |