update simulation syntax for iverilog 11 compat

2023-04-16 15:54:25 -04:00 · 2023-04-16 15:54:25 -04:00 · 925fd915be
parent 1aa067b435
commit 925fd915be
1 changed files with 4 additions and 2 deletions
--- a/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv
+++ b/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv
@ -50,8 +50,10 @@ task write_and_verify(
    assert(read_data == write_data) else $error("data read does not match data written!");
 endtask

-task read_all_reg();
-    string desc;
+task read_all_reg(
+    string desc
+    );
+
    for(int i = 0; i < (logic_analyzer_tb.la.block_mem.MAX_ADDR); i++) begin

        if(i == logic_analyzer_tb.la.fsm_registers.BASE_ADDR) desc = "FSM";