move back to iverilog 13 compatability

2023-04-16 15:59:18 -04:00 · 2023-04-16 15:59:18 -04:00 · 07624d83ee
parent ca814df63e
commit 07624d83ee
1 changed files with 2 additions and 4 deletions
--- a/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv
+++ b/test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv
@ -50,10 +50,8 @@ task write_and_verify(
    assert(read_data == write_data) else $error("data read does not match data written!");
 endtask

-task read_all_reg(
-    string desc
-    );
-
+task read_all_reg();
+    string desc;
    for(int i = 0; i < (logic_analyzer_tb.la.block_mem.MAX_ADDR); i++) begin

        if(i == logic_analyzer_tb.la.fsm_registers.BASE_ADDR) desc = "FSM";