fetch lab-bc on the fly, archive build outputs

.github/workflows/build_examples.yml

@@ -36,4 +36,10 @@ jobs:
         run: make nexys_a7
 
       - name: Build Icestick examples
-        run: make icestick
+        run: make icestick
+
+      - name: Upload examples folder as build artifact
+        uses: actions/upload-artifact@v3
+        with:
+          name: examples
+          path: examples/

.gitignore

@@ -25,8 +25,8 @@ dist/
 *.egg-info
 __pycache__/
 
-# Verilator outputs
-obj_dir/
+# Any stray lab-bc's
+lab-bc.py
 
 # Formal outputs
 test/formal_verification/*_basic

Makefile

@@ -3,7 +3,8 @@ test: auto_gen sim formal
 examples: icestick nexys_a7
 
 clean:
-	rm -f *.out *.vcd
+	rm *.out *.vcd
+	rm **/lab-bc.py
 	rm -rf dist/
 	rm -rf src/mantaray.egg-info
 
@@ -103,39 +104,45 @@ nexys_a7: nexys_a7_video_sprite_uart nexys_a7_io_core nexys_a7_ps2_logic_analyze
 nexys_a7_io_core_ether:
 	cd examples/nexys_a7/io_core_ether/;\
 	manta gen manta.yaml manta.v;		\
-	build
+	wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
+	python3 lab-bc.py
 
 nexys_a7_io_core_uart:
 	cd examples/nexys_a7/io_core_uart/; \
 	manta gen manta.yaml manta.v;		\
-	build
+	wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
+	python3 lab-bc.py
 
 nexys_a7_lut_mem_ether:
 	cd examples/nexys_a7/lut_mem_ether/;\
 	manta gen manta.yaml manta.v;		\
-	build
+	wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
+	python3 lab-bc.py
 
 nexys_a7_lut_mem_uart:
 	cd examples/nexys_a7/lut_mem_uart/;\
 	manta gen manta.yaml manta.v;		\
-	build
+	wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
+	python3 lab-bc.py
 
 nexys_a7_ps2_logic_analyzer:
 	cd examples/nexys_a7/ps2_logic_analyzer/;  					\
 	manta gen manta.yaml src/manta.v;							\
 	manta playback manta.yaml my_logic_analyzer sim/playback.v;	\
-	build
+	wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
+	python3 lab-bc.py
 
 nexys_a7_video_sprite_ether:
 	cd examples/nexys_a7/video_sprite_ether;\
 	manta gen manta.yaml src/manta.v;		\
-	build
+	wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
+	python3 lab-bc.py
 
 nexys_a7_video_sprite_uart:
 	cd examples/nexys_a7/video_sprite_uart;	\
 	manta gen manta.yaml src/manta.v;		\
-	build
-
+	wget https://fpga.mit.edu/6205/_static/F22/documentation/vivado/lab-bc.py; \
+	python3 lab-bc.py
 
 icestick: icestick_io_core icestick_lut_mem
 

test/virtual_uart/manta.yaml

@@ -1,11 +0,0 @@
----
-cores:
-  mem:
-    type: block_mem
-    width: 18
-    depth: 256
-
-uart:
-  port: "auto"
-  baudrate: 115200
-  clock_freq: 100000000

test/virtual_uart/tb_manta.cpp

@@ -1,78 +0,0 @@
-#include <stdlib.h>
-#include <iostream>
-#include <string>
-#include <verilated.h>
-#include <verilated_vcd_c.h>
-#include "Vmanta.h"
-
-vluint64_t sim_time = 0;
-
-int main(int argc, char** argv, char** env) {
-    Vmanta *dut = new Vmanta;
-
-    Verilated::traceEverOn(true);
-    VerilatedVcdC *m_trace = new VerilatedVcdC;
-    dut->trace(m_trace, 5);
-    m_trace->open("waveform.vcd");
-
-    while(true) {
-
-    // get line from stdin
-    std::string line;
-    std::getline(std::cin, line);
-
-    for (int i=0; i < line.length(); i++) {
-         // advance simulation
-        dut->clk ^= 1;
-        dut->mem_clk ^= 1;
-        dut->eval();
-        m_trace->dump(sim_time);
-        sim_time++;
-
-        // feed it to the serial port
-        dut->urx_brx_axiv = 1;
-        dut->urx_brx_axid = line[i];
-
-        if (line[i] == 'C')
-            dut->urx_brx_axid = '\r';
-
-        if (line[i] == 'L')
-            dut->urx_brx_axid = '\n';
-
-        // advance simulation
-        dut->clk ^= 1;
-        dut->mem_clk ^= 1;
-        dut->eval();
-        m_trace->dump(sim_time);
-        sim_time++;
-    }
-
-    for (int i=0; i < 30; i++) {
-
-         // advance simulation
-        dut->clk ^= 1;
-        dut->mem_clk ^= 1;
-        dut->eval();
-        m_trace->dump(sim_time);
-        sim_time++;
-
-
-        // print whatever's on the port
-        if(dut->btx_utx_start)
-            std::cout << dut->btx_utx_data;
-
-         // advance simulation
-        dut->clk ^= 1;
-        dut->mem_clk ^= 1;
-        dut->eval();
-        m_trace->dump(sim_time);
-        sim_time++;
-    }
-
-
-    }
-
-    m_trace->close();
-    delete dut;
-    exit(EXIT_SUCCESS);
-}