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update makefile to reflect new paths

This commit is contained in:
Fischer Moseley 2023-04-28 14:54:20 -04:00
parent f5caca613a
commit df2dbf4ec6
2 changed files with 5 additions and 12 deletions
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13
Makefile
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@ -32,7 +32,7 @@ auto_gen:
python3 test/auto_gen/run_tests.py
# Functional Simulation
functional_sim: io_core_tb logic_analyzer_tb bit_fifo_tb bridge_rx_tb bridge_tx_tb lut_mem_tb
functional_sim: io_core_tb logic_analyzer_tb bridge_rx_tb bridge_tx_tb lut_mem_tb
ethernet_tx_tb:
iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/ethernet_tx_tb.sv
@ -68,20 +68,13 @@ logic_analyzer_tb:
vvp sim.out; \
rm sim.out
bit_fifo_tb:
iverilog -g2012 -o sim.out -y src/manta \
test/functional_sim/bit_fifo_tb/bit_fifo_tb.sv \
test/functional_sim/bit_fifo_tb/bit_fifo.v
vvp sim.out
rm sim.out
bridge_rx_tb:
iverilog -g2012 -o sim.out -y src/manta test/functional_sim/bridge_rx_tb.sv
iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/bridge_rx_tb.sv
vvp sim.out
rm sim.out
bridge_tx_tb:
iverilog -g2012 -o sim.out -y src/manta test/functional_sim/bridge_tx_tb.sv
iverilog -g2012 -o sim.out -y src/manta/uart_iface test/functional_sim/bridge_tx_tb.sv
vvp sim.out
rm sim.out

4
test/functional_sim/logic_analyzer_tb/logic_analyzer_tb.sv
View File

@ -195,8 +195,8 @@ module logic_analyzer_tb;
write_reg(la.trig_blk.BASE_ADDR + 1, 1, "larry_arg");
$display(" -> requesting start");
write_reg(2, 1, "request_start");
write_reg(2, 0, "request_start");
write_reg(3, 1, "request_start");
write_reg(3, 0, "request_start");
#`CP
$display(" -> set larry = 1");