Fischer Moseley
|
6d3a32a988
|
update lots of docs
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
c37a6e5e90
|
move icestick build steps to makefile
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
179b3a8283
|
update makefile
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
30f6e43916
|
update makefile to reset build agent
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
17c91ffc34
|
update makefile
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
0044ae5884
|
merge nexys makefile targets
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
7e707e1fc1
|
manually specify vivado path in makefile
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
b9318e9bf0
|
make examples not require python scripts directory on path
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
6aa27e431e
|
build examples on self-hosted runner
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
7ed4a9e6b8
|
polish uart testbenches
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
56b2442df7
|
move uart code for verification to test/
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
d580419a5b
|
remove lut_mem, clean up examples
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
0840786914
|
enforce consistent folder naming
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
c591c9c6ea
|
update makefile targets
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
54022fff8d
|
make obj/ if does not exist
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
da4920d89d
|
fetch lab-bc on the fly, archive build outputs
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
2b483b1beb
|
add bridge_rx formal to makefile
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
adf355c633
|
make examples build
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
788c616b37
|
update makefile and CI
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
ac23e8a599
|
make functional sim run again
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
1a536080f1
|
rewrite bridge_rx and add basic formal
|
2023-09-02 11:39:16 -04:00 |
|
Fischer Moseley
|
df2dbf4ec6
|
update makefile to reflect new paths
|
2023-04-28 14:57:36 -04:00 |
|
Fischer Moseley
|
cef5e9318b
|
flip i and j, and see the light
|
2023-04-28 14:57:36 -04:00 |
|
Fischer Moseley
|
15aa5f469f
|
add ethernet_tx_tb
|
2023-04-28 14:57:36 -04:00 |
|
Fischer Moseley
|
2c461ed08d
|
add working ethernet_tx testbench
|
2023-04-28 14:57:36 -04:00 |
|
Fischer Moseley
|
9c5ea31d14
|
enforce consistent naming of lut_mem module
|
2023-04-28 14:57:36 -04:00 |
|
Fischer Moseley
|
b3d402c1f5
|
refactor python/hdl structure
|
2023-04-28 14:57:36 -04:00 |
|
Fischer Moseley
|
c507f795f1
|
add ethernet_tx/rx, semi-working in hardware
|
2023-04-28 14:57:36 -04:00 |
|
Fischer Moseley
|
ca814df63e
|
forgot a semicolon in the makefile
|
2023-04-17 18:14:31 -04:00 |
|
Fischer Moseley
|
1aa067b435
|
update logic_analyzer_tb to use only generated HDL
|
2023-04-17 18:14:31 -04:00 |
|
Fischer Moseley
|
102bdee410
|
update makefile to match positional args from PATH'd binaries
|
2023-04-17 18:14:31 -04:00 |
|
Fischer Moseley
|
a2ad90a66a
|
modify sim and generator, seems to work in simulation
|
2023-04-17 18:14:31 -04:00 |
|
Fischer Moseley
|
bdca8e01e7
|
add boilerplate for new modules - just gotta rewrite the fsm
|
2023-04-17 18:14:31 -04:00 |
|
Fischer Moseley
|
d8eeb65b8f
|
fix pipelining in video_sprite exmaple
|
2023-04-13 18:00:22 -04:00 |
|
Fischer Moseley
|
ba6100ce30
|
import tutorial from yesterday, add mostly working bram core
|
2023-04-12 11:47:50 -04:00 |
|
Fischer Moseley
|
12f498dc9a
|
add cursed BRAM core implementation
|
2023-04-10 14:38:29 -04:00 |
|
Fischer Moseley
|
1710da6f87
|
update makefile to represent new functional sim locations
|
2023-04-09 22:33:58 -04:00 |
|
Fischer Moseley
|
1d5245b999
|
fix tests for CI
|
2023-04-08 14:12:24 -04:00 |
|
Fischer Moseley
|
ab8582a570
|
move building examples into makefile, add working logic analyzer test
|
2023-04-03 23:47:36 -04:00 |
|
Fischer Moseley
|
0a4a1519c4
|
clean up inferred BRAM, trim whitespace
|
2023-04-03 21:20:58 -04:00 |
|
Fischer Moseley
|
df4d243b9a
|
refactor test structure
|
2023-04-02 20:33:50 -04:00 |
|
Fischer Moseley
|
839bd4f8e4
|
update arg order for iverilog - seems to throw errors across versions/OSs
|
2023-04-01 16:38:45 -07:00 |
|
Fischer Moseley
|
d5dfd3bbf3
|
add boilerplate for API generation tests
|
2023-03-23 23:50:09 -04:00 |
|
Fischer Moseley
|
a57b5908f2
|
add verbose output to serial
|
2023-03-23 18:10:52 -04:00 |
|
Fischer Moseley
|
500267798f
|
add example instantiation to top of autogenerated output
|
2023-03-19 10:57:32 -06:00 |
|
Fischer Moseley
|
2c51aa9a9a
|
paritally imnplement io core autogeneration
|
2023-03-16 09:38:17 -04:00 |
|
Fischer Moseley
|
11495fca61
|
refactor logic analyzer into submodules
|
2023-03-15 22:43:21 -04:00 |
|
Fischer Moseley
|
fade794333
|
add initialls logic_analyzer core
|
2023-03-15 15:57:42 -04:00 |
|
Fischer Moseley
|
aa2ba43e8f
|
rename lut mem to lut ram, add to manta generator
|
2023-03-14 16:24:56 -04:00 |
|
Fischer Moseley
|
3fda03ec90
|
break up hdl definition into multiple member functinos
|
2023-03-14 16:24:56 -04:00 |