update makefile to match positional args from PATH'd binaries

Makefile

@@ -92,9 +92,10 @@ nexys_a7_io_core:
 	python3 lab-bc.py
 
 nexys_a7_logic_analyzer:
-	cd examples/nexys_a7/logic_analyzer/;   \
-	manta gen manta.yaml src/manta.v;		\
-	mkdir -p obj/; 							\
+	cd examples/nexys_a7/logic_analyzer/;  						\
+	manta gen manta.yaml src/manta.v;							\
+	manta playback manta.yaml my_logic_analyzer sim/playback.v 	\
+	mkdir -p obj/; 												\
 	python3 lab-bc.py
 
 nexys_a7_lut_ram:

examples/nexys_a7/logic_analyzer/run_logic_analyzer.py

@@ -1,15 +0,0 @@
-from manta import Manta
-import pickle
-
-m = Manta('manta.yaml')
-# capture = m.my_logic_analyzer.capture()
-
-# with open("capture.pkl", "wb") as f:
-#     pickle.dump(capture, f)
-
-with open("capture.pkl", "rb") as f:
-    capture = pickle.load(f)
-
-m.my_logic_analyzer.export_vcd(capture, "capture.vcd")
-m.my_logic_analyzer.export_mem(capture, "capture.mem")
-m.my_logic_analyzer.export_playback_module("sim/playback.v")

examples/nexys_a7/logic_analyzer/sim/playback.v

@@ -1,57 +0,0 @@
-/*
-This playback module was generated with Manta v0.0.0 on 16 Apr 2023 at 14:13:24 by fischerm
-
-If this breaks or if you've got dank formal verification memes, contact fischerm [at] mit.edu
-
-Provided under a GNU GPLv3 license. Go wild.
-
-Here's an example instantiation of the Manta module you configured, feel free to copy-paste
-this into your source!
-
-my_logic_analyzer_playback #(.MEM_FILE("capture.mem")) my_logic_analyzer_playback_inst (
-    .clk(clk),
-    .enable(1'b1),
-
-    .larry(larry),
-    .curly(curly),
-    .moe(moe),
-    .shemp(shemp));
-
-*/
-
-
-module my_logic_analyzer_playback (
-    input wire clk,
-
-    input wire enable,
-    output reg done,
-
-    output reg larry,
-    output reg curly,
-    output reg moe,
-    output reg [3:0] shemp);
-
-    parameter MEM_FILE = "";
-    localparam SAMPLE_DEPTH = 4096;
-    localparam TOTAL_PROBE_WIDTH = 7;
-
-    reg [TOTAL_PROBE_WIDTH-1:0] capture [SAMPLE_DEPTH-1:0];
-    reg [$clog2(SAMPLE_DEPTH)-1:0] addr;
-    reg [TOTAL_PROBE_WIDTH-1:0] sample;
-
-    assign done = (addr >= SAMPLE_DEPTH);
-
-    initial begin
-        $display("Loading capture from %s", MEM_FILE);
-        $readmemb(MEM_FILE, capture, 0, SAMPLE_DEPTH-1);
-        addr = 0;
-    end
-
-    always @(posedge clk) begin
-        if (enable && !done) begin
-            addr = addr + 1;
-            sample = capture[addr];
-            {shemp, moe, curly, larry} = sample;
-        end
-    end
-endmodule