Commit Graph

257 Commits

Author SHA1 Message Date
Fischer Moseley 7340ccbbcb more docs 2023-09-02 11:39:16 -04:00
Fischer Moseley 6d3a32a988 update lots of docs 2023-09-02 11:39:16 -04:00
Fischer Moseley 4abc2e2cae update template naming for consistency 2023-09-02 11:39:16 -04:00
Fischer Moseley c37a6e5e90 move icestick build steps to makefile 2023-09-02 11:39:16 -04:00
Fischer Moseley 179b3a8283 update makefile 2023-09-02 11:39:16 -04:00
Fischer Moseley 30f6e43916 update makefile to reset build agent 2023-09-02 11:39:16 -04:00
Fischer Moseley 17c91ffc34 update makefile 2023-09-02 11:39:16 -04:00
Fischer Moseley 0044ae5884 merge nexys makefile targets 2023-09-02 11:39:16 -04:00
Fischer Moseley 7e707e1fc1 manually specify vivado path in makefile 2023-09-02 11:39:16 -04:00
Fischer Moseley b9318e9bf0 make examples not require python scripts directory on path 2023-09-02 11:39:16 -04:00
Fischer Moseley d80adebe22 remove lab-bc setup and tool installation 2023-09-02 11:39:16 -04:00
Fischer Moseley 6aa27e431e build examples on self-hosted runner 2023-09-02 11:39:16 -04:00
Fischer Moseley c76a6de585 fix broken link in io core tutorial 2023-09-02 11:39:16 -04:00
Fischer Moseley 86e491b432 update io core example 2023-09-02 11:39:16 -04:00
Fischer Moseley 7ed4a9e6b8 polish uart testbenches 2023-09-02 11:39:16 -04:00
Fischer Moseley 0132d8fab0 update roadmap 2023-09-02 11:39:16 -04:00
Fischer Moseley 56b2442df7 move uart code for verification to test/ 2023-09-02 11:39:16 -04:00
Fischer Moseley d580419a5b remove lut_mem, clean up examples 2023-09-02 11:39:16 -04:00
Fischer Moseley 8b9abd1b0b update examples, which appear to build :cowboy: 2023-09-02 11:39:16 -04:00
Fischer Moseley 0840786914 enforce consistent folder naming 2023-09-02 11:39:16 -04:00
Fischer Moseley 112bd43963 remove mention of wdata/rdata 2023-09-02 11:39:16 -04:00
Fischer Moseley c591c9c6ea update makefile targets 2023-09-02 11:39:16 -04:00
Fischer Moseley 54022fff8d make obj/ if does not exist 2023-09-02 11:39:16 -04:00
Fischer Moseley da4920d89d fetch lab-bc on the fly, archive build outputs 2023-09-02 11:39:16 -04:00
Fischer Moseley 2b483b1beb add bridge_rx formal to makefile 2023-09-02 11:39:16 -04:00
Fischer Moseley adf355c633 make examples build 2023-09-02 11:39:16 -04:00
Fischer Moseley 051d9800c4 add separate CI pipeline for formal 2023-09-02 11:39:16 -04:00
Fischer Moseley e604db48d8 fix yaml syntax 2023-09-02 11:39:16 -04:00
Fischer Moseley 788c616b37 update makefile and CI 2023-09-02 11:39:16 -04:00
Fischer Moseley ac23e8a599 make functional sim run again 2023-09-02 11:39:16 -04:00
Fischer Moseley d95ca04dd5 move macro functions to tasks, update to 2023-09-02 11:39:16 -04:00
Fischer Moseley 6e9ca36559 add test case for back to back messages 2023-09-02 11:39:16 -04:00
Fischer Moseley 0c942fcb59 finish cleaning up bridge_rx_tb 2023-09-02 11:39:16 -04:00
Fischer Moseley 25b2ff0dd0 add first round of tweaks to bridge_rx_tb 2023-09-02 11:39:16 -04:00
Fischer Moseley 1a536080f1 rewrite bridge_rx and add basic formal 2023-09-02 11:39:16 -04:00
Fischer Moseley 9771d80fd1 replace logic nettype with reg 2023-09-02 11:39:16 -04:00
Fischer Moseley 38f7ee86fa add uart_rx and refactor uart_tx and bridge_tx 2023-09-02 11:39:16 -04:00
Fischer Moseley d67ac9c799 add thesis pdf 2023-07-06 22:28:49 -07:00
Fischer Moseley df2dbf4ec6 update makefile to reflect new paths 2023-04-28 14:57:36 -04:00
Fischer Moseley f5caca613a simplify uart/ether APIs, improve lazy loading 2023-04-28 14:57:36 -04:00
Fischer Moseley ab58af0bfc add video_sprite_ether example 2023-04-28 14:57:36 -04:00
Fischer Moseley cef5e9318b flip i and j, and see the light 2023-04-28 14:57:36 -04:00
Fischer Moseley 15aa5f469f add ethernet_tx_tb 2023-04-28 14:57:36 -04:00
Fischer Moseley 2c461ed08d add working ethernet_tx testbench 2023-04-28 14:57:36 -04:00
Fischer Moseley 9c5ea31d14 enforce consistent naming of lut_mem module 2023-04-28 14:57:36 -04:00
Fischer Moseley 54b97fd120 add working ethernet verilog autogeneration woot woot :) 2023-04-28 14:57:36 -04:00
Fischer Moseley 1d2171faad update pyproject.toml to get verilog files from all subdirs 2023-04-28 14:57:36 -04:00
Fischer Moseley 2013e74f0f update help message with consistent version number 2023-04-28 14:57:36 -04:00
Fischer Moseley b3d402c1f5 refactor python/hdl structure 2023-04-28 14:57:36 -04:00
Fischer Moseley 7f9012b542 tidy examples 2023-04-28 14:57:36 -04:00