luke
/
manta
mirror of https://github.com/fischermoseley/manta.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

update makefile and CI

This commit is contained in:
Fischer Moseley 2023-07-17 07:10:20 -07:00
parent ac23e8a599
commit 788c616b37
3 changed files with 56 additions and 78 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

43
.github/workflows/build_examples.yml vendored
View File

@ -1,11 +1,11 @@
name: build_examples
on: [push]
jobs:
nexys_a7_examples:
examples:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- name: Add SSH Keys
- name: Add SSH Keys for lab-bc
run: |
mkdir ~/.ssh
touch ~/.ssh/id_rsa
@ -26,41 +26,14 @@ jobs:
python3 -m pip install .
- name: Build io_core
run: make nexys_a7_io_core
- name: Build logic_analyzer
run: make nexys_a7_logic_analyzer
- name: Build lut_mem
run: make nexys_a7_lut_mem
icestick_examples:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- name: Install Manta from Source
run: |
pip install setuptools --upgrade
# omitting the following commmand causes the version of setuptools
# used by python to get confused, and it doesn't detect the name
# or version of the package from pyproject.toml - so the following
# workaround is used:
# https://github.com/pypa/setuptools/issues/3269#issuecomment-1254507377
export DEB_PYTHON_INSTALL_LAYOUT=deb_system
python3 -m pip install .
- name: Install Icestorm Tools
run: |
- name: Install oss-cad-suite
run: |
wget --no-verbose https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2023-02-23/oss-cad-suite-linux-x64-20230223.tgz
tar -xzf oss-cad-suite-linux-x64-20230223.tgz
echo "$(pwd)/oss-cad-suite/bin" >> $GITHUB_PATH
- name: Build io_core
run: make icestick_io_core
- name: Build Nexys A7 examples
run: make nexys_a7
- name: Build lut_mem
run: make icestick_lut_mem
- name: Build Icestick examples
run: make icestick

13
.github/workflows/functional_sim.yml vendored
View File

@ -19,5 +19,14 @@ jobs:
python3 -m pip install .
- run: sudo apt install iverilog
- run: make functional_sim
- name: Install oss-cad-suite
run: |
wget --no-verbose https://github.com/YosysHQ/oss-cad-suite-build/releases/download/2023-02-23/oss-cad-suite-linux-x64-20230223.tgz
tar -xzf oss-cad-suite-linux-x64-20230223.tgz
echo "$(pwd)/oss-cad-suite/bin" >> $GITHUB_PATH
- name: Run functional simulations
run: make sim
- name: Run formal verification
run: make formal

78
Makefile
View File

@ -1,41 +1,56 @@
build:
python3 -m build
test: auto_gen sim formal
pypi_upload: build
python3 -m twine upload --repository testpypi dist/*
examples: icestick nexys_a7
lint:
python3 -m black src/manta/__init__.py
python3 -m black src/manta/__main__.py
clean:
rm -f *.out *.vcd
rm -rf dist/
rm -rf src/mantaray.egg-info
rm -rf test/formal_verification/*_basic
rm -rf test/formal_verification/*_cover
rm -f examples/nexys_a7/io_core/obj/*
rm -f examples/nexys_a7/io_core/src/manta.v
rm -f examples/nexys_a7/logic_analyzer/obj/*
rm -f examples/nexys_a7/logic_analyzer/src/manta.v
rm -f examples/nexys_a7/lut_mem/obj/*
rm -f examples/nexys_a7/lut_mem/src/manta.v
rm -f examples/icestick/io_core/*.bin
rm -f examples/icestick/io_core/manta.v
rm -f examples/icestick/lut_mem/*.bin
rm -f examples/icestick/lut_mem/manta.v
serve_docs:
mkdocs serve
src_loc:
find src -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l
total_loc:
find . -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.yml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l
real_loc:
find src test -type f \( -iname \*.sv -o -iname \*.v -o -iname \*.py -o -iname \*.yaml -o -iname \*.md \) | sed 's/.*/"&"/' | xargs wc -l
test: auto_gen functional_sim
# Python Operations
python_build:
python3 -m build
clean:
rm -f *.out *.vcd
rm -rf dist/
rm -rf src/mantaray.egg-info
rm -rf test/formal_verification/*_basic
rm -rf test/formal_verification/*_cover
pypi_upload: build
python3 -m twine upload --repository testpypi dist/*
python_lint:
python3 -m black src/manta/__init__.py
python3 -m black src/manta/__main__.py
# API Generation Tests
auto_gen:
python3 test/auto_gen/run_tests.py
# Functional Simulation
functional_sim: io_core_tb logic_analyzer_tb bridge_rx_tb bridge_tx_tb lut_mem_tb
sim: ethernet_tx_tb ethernet_rx_tb mac_tb block_memory_tb io_core_tb logic_analyzer_tb bridge_rx_tb bridge_tx_tb lut_mem_tb block_memory_tb
ethernet_tx_tb:
iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/ethernet_tx_tb.sv
@ -48,12 +63,12 @@ ethernet_rx_tb:
rm sim.out
mac_tb:
iverilog -g2012 -o sim.out -y src/manta test/functional_sim/mac_tb.sv
iverilog -g2012 -o sim.out -y src/manta/ether_iface test/functional_sim/mac_tb.sv
vvp sim.out
rm sim.out
block_memory_tb:
iverilog -g2012 -o sim.out -y src/manta test/functional_sim/block_memory_tb.sv
iverilog -g2012 -o sim.out -y src/manta/block_mem_core test/functional_sim/block_memory_tb.sv
vvp sim.out
rm sim.out
@ -88,12 +103,9 @@ lut_mem_tb:
# Formal Verification
formal:
sby test/formal_verification/uart_rx.sby
sby -f test/formal_verification/uart_rx.sby
# Build Examples
examples: icestick nexys_a7
nexys_a7: nexys_a7_video_sprite nexys_a7_io_core nexys_a7_ps2_logic_analyzer nexys_a7_lut_mem
nexys_a7_video_sprite:
@ -127,20 +139,4 @@ icestick_io_core:
icestick_lut_mem:
cd examples/icestick/lut_mem/; \
manta gen manta.yaml manta.v; \
./build.sh
clean_examples:
rm -f examples/nexys_a7/io_core/obj/*
rm -f examples/nexys_a7/io_core/src/manta.v
rm -f examples/nexys_a7/logic_analyzer/obj/*
rm -f examples/nexys_a7/logic_analyzer/src/manta.v
rm -f examples/nexys_a7/lut_mem/obj/*
rm -f examples/nexys_a7/lut_mem/src/manta.v
rm -f examples/icestick/io_core/*.bin
rm -f examples/icestick/io_core/manta.v
rm -f examples/icestick/lut_mem/*.bin
rm -f examples/icestick/lut_mem/manta.v
./build.sh