luke
/
abc
mirror of https://github.com/YosysHQ/abc.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
2,451 Commits 27 Branches 57 Tags 58 MiB
Commit Graph

1236 Commits

Author SHA1 Message Date
Alan Mishchenko 853222ee7b Fixed a corner-case when 'sim3 -a' does not work for costant POs. 2013-01-25 06:49:49 +07:00
Alan Mishchenko edd4b2a29c Added switch &trim -V <num> to remove const POs with specific value <num>. 2013-01-25 06:19:51 +07:00
Alan Mishchenko aa9c87cf8d Extending verification status file format to allow for SAT status without CEX. 2013-01-25 05:59:56 +07:00
Alan Mishchenko 6863688789 Enabled detecting CEXes in multiple POs without stopping (sim3 -a). 2013-01-23 12:37:44 +07:00
Alan Mishchenko ac1207abea Enabled detecting CEXes in multiple POs without stopping (sim3 -a). 2013-01-23 02:07:50 +07:00
Alan Mishchenko 1b6662ce4a Fixing C++ compilation issues. 2013-01-08 14:16:59 +08:00
Alan Mishchenko 562b612691 Fixing C++ compilation issues. 2013-01-08 14:15:39 +08:00
Alan Mishchenko a625caa17d Fixing C++ compilation issues. 2013-01-08 13:56:20 +08:00
Alan Mishchenko f26e760e9d Fixing C++ compilation issues. 2013-01-08 13:33:17 +08:00
Alan Mishchenko 81a1d97079 Fixing C++ compilation issues. 2013-01-08 13:14:45 +08:00
Alan Mishchenko a8dad4ed61 Fixing C++ compilation issues. 2013-01-08 13:12:28 +08:00
Alan Mishchenko a0819f62ab Adding support of flops to the conversion of MiniAIG into ABC network. 2013-01-08 06:42:25 +08:00
Alan Mishchenko 79f3ecb15f Technology mapper. 2013-01-08 05:50:37 +08:00
Alan Mishchenko e1a5556e8c New unrolling manager. 2012-12-24 08:16:19 +07:00
Alan Mishchenko bfad654205 Assembling timing/hierarchy manager from input data. 2012-12-15 17:39:34 -08:00
Alan Mishchenko 82050bbe11 Assembling timing/hierarchy manager from input data. 2012-12-13 15:18:53 -08:00
Alan Mishchenko 2575a5d683 Unifification of custom extensions. 2012-12-10 13:56:40 -08:00
Alan Mishchenko f7b7ab59cf Retiring old 'fpga' command and package. 2012-12-10 01:14:55 -08:00
Alan Mishchenko dc843b03c9 Renaming If_Lut_t into If_LibLut_t. 2012-12-10 01:07:41 -08:00
Alan Mishchenko 5eedc74a15 Adding box library. 2012-12-10 00:59:54 -08:00
Alan Mishchenko 8355eb1d41 Enabling multi-output solving in 'pdr'. 2012-12-09 17:52:34 -08:00
Alan Mishchenko ce63869fe7 Enabling multi-output solving in 'pdr'. 2012-12-09 17:33:44 -08:00
Alan Mishchenko 8761942258 Renaming multi-output mode enable switch 'bmc3 -s' to be 'bmc3 -a'. 2012-12-09 16:56:43 -08:00
Alan Mishchenko 9fc1cd0b3f Enabling multi-output solving in 'pdr'. 2012-12-09 15:12:40 -08:00
Alan Mishchenko 58d4012a55 Enabling multi-output solving in 'pdr'. 2012-12-09 14:46:16 -08:00
Alan Mishchenko 9f396a0d7e Enabling multi-output solving in 'pdr'. 2012-12-09 10:11:52 -08:00
Alan Mishchenko b65ae7349a Enabling multi-output solving in 'pdr'. 2012-12-09 09:47:48 -08:00
Alan Mishchenko 0058cefee3 Deriving CEX after phase/tempor/reparam. 2012-12-09 00:19:18 -08:00
Alan Mishchenko a68593c4f2 Deriving CEX after phase/tempor/reparam. 2012-12-08 12:44:08 -08:00
Alan Mishchenko 8e5d771feb Deriving CEX after phase/tempor/reparam. 2012-12-08 12:38:31 -08:00
Alan Mishchenko f1749fa594 Enabling additional stat printouts. 2012-12-02 01:44:17 -08:00
Alan Mishchenko 4d67a04b19 Enabling additional stat printouts. 2012-12-02 01:25:53 -08:00
Alan Mishchenko a797ea0cc7 Enabling additional stat printouts. 2012-12-02 00:00:29 -08:00
Alan Mishchenko 86fcba60c2 Enabling command &append for combiming multiple AIGs. 2012-12-01 23:13:24 -08:00
Alan Mishchenko 01bea8ef3a Enabling additional stat printouts. 2012-12-01 22:16:22 -08:00
Alan Mishchenko cd32ae50c4 Counter-example analysis and optimization. 2012-11-30 17:22:44 -08:00
Alan Mishchenko f1a5288904 Counter-example analysis and optimization. 2012-11-30 11:38:05 -08:00
Alan Mishchenko 661265984c Counter-example analysis and optimization. 2012-11-28 16:18:39 -08:00
Alan Mishchenko b2fd119933 DSD manager. 2012-11-20 21:34:40 -08:00
Alan Mishchenko ffbe3bc576 DSD manager. 2012-11-19 23:42:05 -08:00
Alan Mishchenko a0052e22b4 Added switch 'cexcut -m' to generate bad states for all frames after G. 2012-11-15 16:00:29 -08:00
Alan Mishchenko c2e467d55b Added switch 'cexcut -n' to generate only one bad state. 2012-11-15 10:59:57 -08:00
Alan Mishchenko 2eb2402b01 Added command 'cexcut' and 'cexmerge'. 2012-11-14 20:50:18 -08:00
Alan Mishchenko 9173799c96 Added command 'cexcut' and 'cexmerge'. 2012-11-14 18:22:13 -08:00
Alan Mishchenko be29f37baa Added command 'cexcut' and 'cexmerge'. 2012-11-14 18:20:35 -08:00
Alan Mishchenko 9d5d804610 Added command 'cexcut' and 'cexmerge'. 2012-11-14 16:09:49 -08:00
Alan Mishchenko d8e0403296 Added command 'cexsave' and 'cexload'. 2012-11-14 14:33:27 -08:00
Alan Mishchenko be7a4e4259 Isolating BMC code into a separate package. 2012-11-14 13:55:24 -08:00
Alan Mishchenko aba8ff4ba0 Modifying parameter limits to allow mapping into 2-LUTs. 2012-11-14 12:56:45 -08:00
Alan Mishchenko 30b8c3d422 Made print-out of frontier cut an option ('-c') in '&ps'. 2012-11-12 14:08:10 -08:00
Alan Mishchenko 566c7d7152 Extending GIA to represent pintypes and pins. 2012-11-12 13:57:51 -08:00
Alan Mishchenko 21e6a59ed8 Improved DSD. 2012-11-11 13:26:36 -08:00
Alan Mishchenko ee789ba902 Improved DSD. 2012-11-10 19:37:53 -08:00
Alan Mishchenko e0f27f5ac3 Improved DSD. 2012-11-10 17:26:01 -08:00
Alan Mishchenko fdcbb2cf37 Performance bug fix in choice generation. 2012-11-09 12:43:03 -08:00
Alan Mishchenko db7852bba7 Improvements to LMS code. 2012-11-06 18:04:23 -08:00
Alan Mishchenko 7ba37f4901 Improved DSD. 2012-11-03 00:38:17 -07:00
Alan Mishchenko c899645b10 Adding dumping truth tables from LMS manager. 2012-11-02 18:59:14 -07:00
Alan Mishchenko 96d3348d8f Fixing out-of-bound problem when collecting GIA nodes. 2012-11-02 12:02:16 -07:00
Alan Mishchenko 7a7173c80e Improvements to LMS code. 2012-11-02 00:27:34 -07:00
Alan Mishchenko bd7b55115f Improvements to LMS code. 2012-11-02 00:06:56 -07:00
Alan Mishchenko a20e32f9e3 Improvements to LMS code. 2012-11-01 22:03:37 -07:00
Alan Mishchenko f23a17e0c6 Improvements to LMS code. 2012-11-01 16:24:36 -07:00
Alan Mishchenko 35c8d6a2fd Improvements to the truth table computations. 2012-11-01 14:58:31 -07:00
Alan Mishchenko d56570f235 Improvements to the truth table computations. 2012-11-01 14:23:05 -07:00
Alan Mishchenko ce3f8cb1d1 Improvements to the truth table computations. 2012-11-01 02:53:09 -07:00
Alan Mishchenko ce1ea73238 Removed 'send_cex'. 2012-10-31 01:36:14 -07:00
Alan Mishchenko 0fafe786ae Improvements to the truth table computations. 2012-10-30 22:25:45 -07:00
Niklas Een 77fde55b1b Added switch for netlist type to 'send_aig'. Changed defautl to &-space. Fixed printf -> Abc_Print in some places. 2012-10-30 19:09:40 -07:00
Niklas Een 7da6ef1c02 Removed CEX communication through bridge in Abc_FrameReplaceCex 2012-10-30 13:02:11 -07:00
Alan Mishchenko 9b8d362854 Added new bridge commands. 2012-10-29 23:50:47 -07:00
Alan Mishchenko 90529df059 Tentatively integrated new DSD. 2012-10-29 13:39:05 -07:00
Alan Mishchenko 68d360c2d0 Move truth table code into a separte file. 2012-10-28 19:42:20 -07:00
Alan Mishchenko f5a8cf99c0 Improvements to LMS code. 2012-10-28 18:58:43 -07:00
Alan Mishchenko d8d820052e Improvements to LMS code. 2012-10-28 18:50:10 -07:00
Alan Mishchenko 12dda47081 Improvements to LMS code. 2012-10-28 18:22:17 -07:00
Alan Mishchenko 15895cd2e3 Improvements to LMS code. 2012-10-28 18:17:28 -07:00
Alan Mishchenko c73c37a99d Improvements to LMS code. 2012-10-28 16:16:34 -07:00
Alan Mishchenko 4e52703b8a Improvements to LMS code. 2012-10-27 18:03:57 -07:00
Alan Mishchenko 94d722c58e Improvements to LMS code. 2012-10-27 17:33:13 -07:00
Alan Mishchenko b733b813d6 Added switch '-q' to 'scorr' and '&scorr' to quit when PO is not a candidate constant. 2012-10-25 22:50:29 -07:00
Alan Mishchenko fac3976621 Adding binary file dumping for truth tables. 2012-10-25 13:55:04 -07:00
Alan Mishchenko 059da57476 Adding binary file dumping for truth tables. 2012-10-25 11:45:19 -07:00
Alan Mishchenko 785ae9e4db Changing the defaults of command 'collapse'. 2012-10-25 11:16:11 -07:00
Alan Mishchenko 7ecea8d40d Added hierarchical BLIF output for mapping with LUT structures (write_blif -a -S <XYZ>). 2012-10-24 21:12:50 -07:00
Alan Mishchenko e9e8f17942 Integrating GIA with LUT mapping. 2012-10-24 20:00:20 -07:00
Alan Mishchenko 6b96d9a84e Integrating GIA with LUT mapping. 2012-10-24 17:39:38 -07:00
Alan Mishchenko e9783622a2 Disabling SAT sweeping in 'map' by default. 2012-10-23 12:08:15 -07:00
Alan Mishchenko 7235d74010 Bug fix in hierarchical BLIF reader. 2012-10-11 23:25:40 -07:00
Alan Mishchenko d261e617fc Added command to transform GIA into the file with truth tables for each output. 2012-10-10 01:11:24 -07:00
Alan Mishchenko 1e7ea2ca45 Improvements to gate sizing. 2012-10-09 21:14:32 -07:00
Alan Mishchenko 4ed89d00fe Making explicit cast to 64-bit unsigned in a few places. 2012-10-09 09:23:08 -07:00
Alan Mishchenko a5d07fa44a Bug fix in LMS code. 2012-10-08 22:41:19 -07:00
Alan Mishchenko cad47254a0 Updating readme. 2012-10-06 19:27:19 -07:00
Alan Mishchenko f66fd3f3a3 Updating readme. 2012-10-06 18:28:25 -07:00
Alan Mishchenko 3d23bc8c57 New AIG optimization package. 2012-10-06 16:02:36 -07:00
Alan Mishchenko ad8a3f5159 New AIG optimization package. 2012-10-06 15:09:00 -07:00
Alan Mishchenko 6de48109f3 Allow for binary input file in 'testdec' and 'testnpn'. 2012-10-05 21:43:11 -07:00
Alan Mishchenko 369b5f479a Allow for binary input file in 'testdec' and 'testnpn'. 2012-10-05 21:02:46 -07:00
Alan Mishchenko b852db94fb Allow for binary input file in 'testdec' and 'testnpn'. 2012-10-05 20:38:46 -07:00
Alan Mishchenko e01e49369f Changed 'readline' declaration rules. 2012-10-04 13:03:04 -07:00
Alan Mishchenko bbd170e8a3 Minor bug fix. 2012-10-04 09:17:13 -07:00
Alan Mishchenko 56d3d7cd22 C++ portability changes. 2012-10-03 21:49:18 -07:00
Alan Mishchenko d1ffd8d703 Added command 'starter' to call ABC concurrently. 2012-10-02 22:40:18 -07:00
Alan Mishchenko e6196fb462 Added command 'starter' to call ABC concurrently. 2012-10-02 22:35:45 -07:00
Alan Mishchenko 6c1c45b90f Added command 'starter' to call ABC concurrently. 2012-10-02 21:41:24 -07:00
Alan Mishchenko aa705a9af6 Renamed reference counting APIs in GIA package. 2012-10-02 20:20:46 -07:00
Alan Mishchenko 49267fd379 Structural reparametrization. 2012-10-02 20:11:38 -07:00
Alan Mishchenko aeb7f7ea11 Combined old reparametrization command with the new one. 2012-10-02 17:27:36 -07:00
Alan Mishchenko 9d6f7fa4e6 Added detection of 'readline' library at compile-time. 2012-10-02 17:00:03 -07:00
Alan Mishchenko 65cf119c2b Added detection of 'readline' library at compile-time. 2012-10-02 16:46:55 -07:00
Alan Mishchenko 4aa33e7d0f Structural reparametrization. 2012-10-02 16:30:14 -07:00
Alan Mishchenko a595fa85ef Structural reparametrization. 2012-09-30 22:46:21 -07:00
Alan Mishchenko 7fab7fd176 Added serialization of Mini AIG. 2012-09-29 20:21:27 -04:00
Alan Mishchenko 8a91a9afe8 Experiments with mini AIG manager. 2012-09-29 19:44:45 -04:00
Alan Mishchenko 781c66cbf3 Experiments with mini AIG manager. 2012-09-29 19:00:36 -04:00
Alan Mishchenko 73d68a08c1 Compiler warnings. 2012-09-29 17:56:00 -04:00
Alan Mishchenko 13dc7bacf1 Added detection of 'readline' library at compile-time. 2012-09-29 17:50:50 -04:00
Alan Mishchenko 71bdfae941 Replacing 'st_table' by 'st__table' to resolve linker problems. 2012-09-29 17:11:03 -04:00
Alan Mishchenko 5cf9d6ddd7 Experiments with mini AIG manager. 2012-09-29 16:17:19 -04:00
Alan Mishchenko ae1dddbcc3 Experiments with mini AIG manager. 2012-09-29 15:37:31 -04:00
Alan Mishchenko 62a6152b6c Experiments with mini AIG manager. 2012-09-29 15:29:07 -04:00
Alan Mishchenko 74c9a068eb Updated version of LMS code. 2012-09-26 08:50:15 -07:00
Alan Mishchenko 27383e8be2 Updated version of LMS code. 2012-09-26 08:36:05 -07:00
Alan Mishchenko 794b4cd8ce Updated version of LMS code. 2012-09-26 08:23:40 -07:00
Alan Mishchenko 8c369788b3 Improvements to the NPN semi-canonical form computation package. 2012-09-25 13:20:18 -07:00
Alan Mishchenko 0a9236add5 Improvements to the NPN semi-canonical form computation package. 2012-09-25 13:10:52 -07:00
Alan Mishchenko aed3b3a13a Cleaned up interfaces of genlib/liberty/supergate reading/writing. 2012-09-25 01:34:26 -07:00
Alan Mishchenko d0197d8378 Changed printouts in a few places in supergate computation. 2012-09-24 22:57:01 -07:00
Alan Mishchenko 6f03813557 Testing GIA with time manager. 2012-09-24 01:13:51 -07:00
Alan Mishchenko 40d9b5853b Testing GIA with time manager. 2012-09-23 18:34:10 -07:00
Alan Mishchenko f7caf84f21 Modified structural constraint extraction (unfold -s) to work for multi-output testcases. 2012-09-23 14:30:17 -07:00
Alan Mishchenko c8ed816714 Migrating to array-based traversal ID. 2012-09-23 12:29:16 -07:00
Alan Mishchenko 6e774ef541 Cleaing AIG manager by removing pointers to HAIG. 2012-09-23 12:01:59 -07:00
Alan Mishchenko a50a38155c Integrating time manager into choice computation. 2012-09-22 17:57:06 -07:00
Alan Mishchenko b5306c1566 Added simplification before the concurrent call to PDR. 2012-09-20 20:13:40 -07:00
Alan Mishchenko 5f09917c22 Added simplification before the concurrent call to PDR. 2012-09-20 19:51:39 -07:00
Alan Mishchenko d21c0be44a Added slack computation to 'stime'. 2012-09-20 14:13:59 -07:00
Alan Mishchenko 266af49386 Modified 'read' to read all types of libraries (genlib, liberty, scl). 2012-09-20 13:12:51 -07:00
Alan Mishchenko bc44087bac Modified 'read' to read all types of libraries (genlib, liberty, scl). 2012-09-20 12:41:59 -07:00
Alan Mishchenko f59de3decc Fixes to Verilog parser. 2012-09-20 11:29:37 -07:00
Alan Mishchenko 723f85ef1b Extending Liberty parser to handle multi-output cells. 2012-09-19 20:21:27 -07:00
Alan Mishchenko 5dc50744f0 Extending Liberty parser to handle multi-output cells. 2012-09-19 18:42:00 -07:00
Alan Mishchenko 480ca14c75 Extending Liberty parser to handle multi-output cells. 2012-09-19 17:35:04 -07:00
Alan Mishchenko 3af0f719af Extending BLIF parser/write to hangle multi-output cells. 2012-09-19 16:28:06 -07:00
Alan Mishchenko e0eb270324 Changes to command 'upsize'. 2012-09-18 13:23:58 -07:00
Alan Mishchenko 508b6f1b13 Fixing mismatch between declaration of the output value of Extra_CpuTime. 2012-09-18 09:58:06 -07:00
Alan Mishchenko 7e843d64a9 Added delay multipliers to 'map'. 2012-09-16 23:34:56 -07:00
Alan Mishchenko 6d05fde2dc Added delay multipliers to 'map'. 2012-09-16 22:05:15 -07:00
Alan Mishchenko ee436f9377 Changed a few things in the refinement package of &gla. 2012-09-16 13:56:10 -07:00
Alan Mishchenko 5953beb2da Restructured the code to post-process object used during refinement in &gla. 2012-09-16 09:54:19 -07:00
Alan Mishchenko fdf5ad3433 Cleaned 'abc.c' by removing useless procedures. 2012-09-15 23:52:36 -07:00
Alan Mishchenko 69bbfa9856 Created new abstraction package from the code that was all over the place. 2012-09-15 23:27:46 -07:00
Alan Mishchenko 117bc0dbcd Prepared &gla to try abstracting and proving concurrently. 2012-09-14 21:20:37 -07:00
Alan Mishchenko 3b14c7b490 Prepared &gla to try abstracting and proving concurrently. 2012-09-14 13:31:29 -07:00
Alan Mishchenko 19c28cae94 Prepared &gla to try abstracting and proving concurrently. 2012-09-14 10:27:48 -07:00
Alan Mishchenko a246882a5b Scalable gate-level abstraction. 2012-09-11 19:11:51 -07:00
Niklas Een 1c865bf229 Added -C to command line for running commands, then staying in interactive mode 2012-09-11 18:48:43 -07:00
Alan Mishchenko 784a3579e5 Fixing Verilog writer's way of writing module names. 2012-09-11 18:44:07 -07:00
Alan Mishchenko d40af538e2 Unified print-out of property failures produced by all engines. 2012-09-09 20:46:34 -07:00
Alan Mishchenko 56117d56e8 Added switch '-p' to '&gla -n' to use full proof for UNSAT core computation (for experiments). 2012-09-09 15:28:31 -07:00
Alan Mishchenko 4333fd24d2 Started CEX minimization procedure. 2012-09-08 18:28:13 -07:00
Alan Mishchenko 5ca4f3cf9f Updating &gla_refine to perform suffic refinement. 2012-09-07 23:26:23 -07:00
Alan Mishchenko 548e04192b Updating &gla_refine to perform suffic refinement. 2012-09-07 20:44:12 -07:00
Alan Mishchenko 39fe23f079 Integrated new fast semi-canonical form for Boolean functions up to 16 inputs. 2012-09-06 15:52:54 -07:00
Alan Mishchenko 9c8be56ccd Integrated new fast semi-canonical form for Boolean functions up to 16 inputs. 2012-09-06 15:32:07 -07:00
Alan Mishchenko cd2bd70865 Added switch 'dch -r' to skip choices with structural support redundancy. 2012-09-05 19:39:25 -07:00
Alan Mishchenko c1f4545e07 Added error message when the user is trying 'dsat' for multi-output comb miters. 2012-09-05 18:53:21 -07:00
Alan Mishchenko f6b67d7846 Added new command &gla_shrink. 2012-09-04 23:57:58 -07:00
Alan Mishchenko 8e12b60b66 Better batch mode printout. 2012-09-04 14:39:14 -07:00
Alan Mishchenko 05f51cbb2a Enabled recording the name of the file GIA is coming from. 2012-09-04 13:52:42 -07:00
Alan Mishchenko 9621ae946e Added switch &srm -A <file> for dumping SRM into a user-specified file. 2012-09-02 20:12:03 -07:00
Alan Mishchenko a49ba2d280 Fixing the way constants are written into mapped Verilog files. 2012-08-31 00:05:10 -07:00
Alan Mishchenko 3400670839 Handling constant nodes in gate sizing. 2012-08-30 13:58:26 -07:00
Alan Mishchenko 83bfe0b1fe New package to read/write a subset of Liberty for STA. 2012-08-29 16:20:39 -07:00
Alan Mishchenko 6814c48bb4 Added an API to convert a multi-output PLA into a shared AIG. 2012-08-29 12:43:55 -07:00
Alan Mishchenko 5ff49be993 Ensured that SC mapped network is always in a topo order. 2012-08-28 19:42:53 -07:00
Alan Mishchenko 9b02fe59bd Added buffering based on combinational merging. 2012-08-28 19:24:13 -07:00
Alan Mishchenko 329831bdac Bug fix: abstraction commands not properly updating status when dumping intermediate abstraction. 2012-08-28 12:12:24 -07:00
Alan Mishchenko 8a1d439cb1 Added precomputation of TFO ordering for incremental network updates. 2012-08-27 22:11:29 -07:00
Alan Mishchenko a6bfd49591 Improved printout of command history. 2012-08-27 19:57:44 -07:00
Alan Mishchenko da6838463f Added features 'map -M <float>' to control the use of large gates. 2012-08-27 14:29:32 -07:00
Alan Mishchenko 889ed19c1c Compiler warnings. 2012-08-26 09:31:43 -07:00
Alan Mishchenko 137f0347f0 Added switch '&gla -m' to dump original miter with the abstraction map. 2012-08-26 09:21:45 -07:00
Alan Mishchenko fba0552f87 Added recording history of used commands into file 'abc.history' (Windows only). 2012-08-25 14:57:06 -07:00
Alan Mishchenko bffbd05a2f Added recording history of used commands into file 'abc.history' (Windows only). 2012-08-25 13:43:44 -07:00
Alan Mishchenko 2a7a06b653 Added recording history of used commands into file 'abc.history' (Windows only). 2012-08-25 12:32:44 -07:00
Alan Mishchenko 49c5799934 Several improvements to command 'testnpn'. 2012-08-25 10:30:53 -07:00
Alan Mishchenko f85db9dd1f Compiler warnings. 2012-08-24 21:36:09 -07:00
Alan Mishchenko 13bd7b334c New package to read/write a subset of Liberty for STA. 2012-08-24 21:31:46 -07:00
Alan Mishchenko 22d21a5c44 Added recording history of used commands into file 'abc.history' (Windows only). 2012-08-24 15:44:33 -07:00
Alan Mishchenko 7e2b007762 Added recording history of used commands into file 'abc.history' (Windows only). 2012-08-24 12:25:53 -07:00
Alan Mishchenko 4a9152d0e1 Changed command 'sim' to work with a miter by default (replace 'sim -m' by 'sim' in verification applications). 2012-08-24 11:14:40 -07:00
Alan Mishchenko 942600414d Added simulation of comb circuits with user-specified patterns in command 'sim'. 2012-08-24 11:12:51 -07:00
Alan Mishchenko 12c776ed6e Added new algorithm for NPN semi-canonical form computation. 2012-08-23 22:20:27 -07:00
Alan Mishchenko 20518f59d1 Compiler warnings. 2012-08-09 18:45:53 -07:00
Alan Mishchenko 8ad4a10fae Compiler warnings. 2012-08-09 18:07:00 -07:00
Alan Mishchenko 41fa9a1016 New command 'testnpn' to compare semi-canonical forms. 2012-08-08 01:42:14 -07:00
Alan Mishchenko 6a9eaec3b5 Changing the default value '&gla -n' to the opposite. 2012-08-06 07:44:55 -07:00
Alan Mishchenko 30ae05f0a5 Scalable gate-level abstraction. 2012-08-03 18:25:47 -07:00
Alan Mishchenko e9af6c3cec Scalable gate-level abstraction. 2012-08-02 23:44:48 -07:00
Alan Mishchenko cb66aa429d Scalable gate-level abstraction. 2012-08-02 10:54:21 -07:00
Alan Mishchenko 352060122b Scalable gate-level abstraction. 2012-08-02 09:40:19 -07:00
Alan Mishchenko 216fc33a47 Fixed compiler warnings. 2012-07-29 22:36:21 -07:00
Alan Mishchenko 5838789ee7 Scalable gate-level abstraction. 2012-07-29 12:34:59 -07:00
Alan Mishchenko e8d690f2a4 Adding command 'testdec'. 2012-07-28 18:30:21 -07:00
Alan Mishchenko 1e159a826e Started implementing command 'testdec'. 2012-07-28 12:42:17 -07:00
Alan Mishchenko 950777ed50 Fixing interpolation to run without resource limits by default. 2012-07-25 20:42:55 -07:00
Alan Mishchenko b2ad079a2a Allow for skipping structural hashing when reading GIA from file. 2012-07-25 12:37:19 -07:00
Alan Mishchenko 160b196a70 Updated code for lazy man's synthesis. 2012-07-25 12:37:07 -07:00
Alan Mishchenko 7dc8c81ff6 Allow for skipping structural hashing when reading GIA from file. 2012-07-25 08:59:24 -07:00
Alan Mishchenko 6df122bda6 Updated code for lazy man's synthesis (memory optimization). 2012-07-20 18:56:26 -07:00
Alan Mishchenko 6c9b59bfc0 Updated code for lazy man's synthesis. 2012-07-20 15:54:08 -07:00
Alan Mishchenko f09afdf24c Added switch &trim -c to additionally remove direct connections (POs fed by PIs). 2012-07-20 13:52:39 -07:00
Alan Mishchenko aa78ce56e7 Updated code for lazy man's synthesis. 2012-07-20 11:52:51 -07:00
Alan Mishchenko 2279a538b7 New procedures to generate NPN-classes for a library of 6-input functions. 2012-07-19 20:38:03 -07:00
Alan Mishchenko 1fe2ba9ac0 Enabling &gla for combinational miters. 2012-07-18 23:52:41 -07:00
Alan Mishchenko 6b2da3978f Adding new file to the build file. 2012-07-17 20:46:45 -07:00
Alan Mishchenko 226c24e49d Updated code for lazy man's synthesis. 2012-07-15 15:56:03 -07:00
Alan Mishchenko 96d7699698 Updated code for lazy man's synthesis. 2012-07-15 15:54:36 -07:00
Alan Mishchenko 94193472c8 Fixing assertion mismatch in bmc2. 2012-07-14 09:25:18 -07:00
Alan Mishchenko d3ad7fbaf3 Several small changes and fixes. 2012-07-13 15:02:46 -07:00
Alan Mishchenko b9ee5d8564 Improvements in the proof-logging SAT solver. 2012-07-11 12:45:46 -07:00
Alan Mishchenko 63dab64574 Replacing printf() by Abc_Print(). 2012-07-10 18:04:08 -07:00
Alan Mishchenko 908d5e696c Replacing Mb/Gb to be MB/GB. 2012-07-09 22:57:03 -07:00
Alan Mishchenko a92c41f767 Removing print-out message in bridge mode. 2012-07-09 22:16:52 -07:00
Alan Mishchenko 637736827a Adding several command-line arguments to 'dsat'. 2012-07-09 19:24:39 -07:00
Alan Mishchenko 685faae8e2 Added command &gla_purify. 2012-07-08 17:56:49 -07:00
Alan Mishchenko ff0ec52d4d Updating memory print-out of &vta and &gla. 2012-07-08 14:01:28 -07:00
Alan Mishchenko d533f18219 Adding printout to report command line executed in batch mode. 2012-07-08 13:23:29 -07:00
Alan Mishchenko 6c3363f777 Adding restart to rarity simulation in sim3 and &sim3. 2012-07-08 13:23:05 -07:00
Alan Mishchenko 1c33107cbb Updating project settings to have simpler include paths. 2012-07-07 20:14:12 -07:00
Alan Mishchenko ea98a2497e Fixing time primtouts throughout the code. 2012-07-07 18:41:02 -07:00
Alan Mishchenko 4760983a46 Fixing time primtouts throughout the code. 2012-07-07 18:15:08 -07:00
Alan Mishchenko 3aab724573 Fixing time primtouts throughout the code. 2012-07-07 17:46:54 -07:00
Alan Mishchenko 5fb7c676c2 Procedure to compute truth tables for POs of GIA. 2012-07-07 13:13:32 -07:00
Alan Mishchenko bea33c0584 Diabling compact AIGER writing by default. 2012-07-07 12:23:03 -07:00
Alan Mishchenko 8b881d235a Making 'pdr', &gla, &vta print correctly in batch mode. 2012-07-07 10:44:34 -07:00
Alan Mishchenko 5008b1a4f3 Commands &fla_gla/&gla_fla to convert between flop-level and gate-level abstraction. 2012-07-06 20:41:11 -07:00
Alan Mishchenko e879f0f6d1 Tentatively retiring command &abs_start, &abs_cba, &abs_pba, &gla_cba, &gla_pba. 2012-07-06 18:50:50 -07:00
Alan Mishchenko 23467b83b6 Setting infinite default conflict limits in 'bmc', 'int', 'pdr'. 2012-07-06 18:48:35 -07:00
Alan Mishchenko 8b0302cdab Changing default conflict limits in bmc2 and bmc3 to be 0 (no limit). 2012-07-05 13:32:52 -07:00
Alan Mishchenko 3c43fbba1a Other improvements to &vta and &gla. 2012-07-05 13:09:41 -07:00
Alan Mishchenko ce6e6551c3 Other improvements to &vta and &gla. 2012-07-04 18:23:33 -07:00
Alan Mishchenko d3c018cd23 Reducing memory usage in bmc2 and bmc3. 2012-07-01 02:19:19 -07:00
Alan Mishchenko a4908534f1 Bug fix in &vta. 2012-06-29 15:17:03 -07:00
Alan Mishchenko 051cc64ee2 Gate level abstraction (command &gla). 2012-06-28 23:06:07 -07:00
Alan Mishchenko 520c436d28 Gate level abstraction (command &gla). 2012-06-28 16:44:03 -07:00
Alan Mishchenko 7629fd6aea Added min-cut-based refinement of gate-level abstraction (command &gla_refine). 2012-06-24 18:45:42 -07:00
Alan Mishchenko 3c0a9e0862 Switch -A <file_name> to specify file name for dumping abstrated model with &vta -d. 2012-06-21 20:20:26 -07:00
Alan Mishchenko 98d9d5a61f Added warning when a command is missing 2012-06-15 08:37:56 -07:00
Alan Mishchenko c6af9094c0 Changing 'if' to allow for delay optimization on sequential paths only. 2012-05-20 17:27:53 +07:00
Alan Mishchenko 37a3e07d91 Prevent network from being unmapped after equivalence checking. 2012-05-15 15:36:51 +07:00
Alan Mishchenko 54670783e0 Better resolution of CO drivers. Should impact the QoR after 'if'. 2012-05-15 15:28:42 +07:00
Alan Mishchenko 76539c1956 Added generation of multipliers in 'gen'. 2012-05-15 09:34:24 +07:00
Alan Mishchenko 675437b214 Preventing 'show' from unmapping the network. 2012-05-14 19:55:40 +07:00
Alan Mishchenko e37fb952da Included copyright statement into 'main.c'. 2012-05-11 09:26:36 +07:00
Alan Mishchenko 7452455155 Changing the rules of assigning the names when AIG is converted into a logic network. 2012-05-11 08:35:54 +07:00
Alan Mishchenko aa087d2513 Making sure cec -n and dsec -n do not remove the I/O names in the current network. 2012-05-08 13:37:19 +08:00
Alan Mishchenko 50fac8a098 Bug fix in fraig_restore. 2012-05-06 22:52:56 +08:00
Alan Mishchenko 959ac60956 Misc changes. 2012-05-01 08:04:31 +08:00
Alan Mishchenko 2c6faa0607 Compilation problem caused by multiple declarations. 2012-04-28 16:04:17 +07:00
Alan Mishchenko 78855cc952 Added supporting dual-output seq miters in &trim. 2012-04-28 04:19:26 +07:00
Alan Mishchenko 2bf7454b41 Added supporting dual-output seq miters in &iso. 2012-04-28 02:21:06 +07:00
Alan Mishchenko a4baba2c83 Misc changes. 2012-04-27 16:26:41 +07:00
Alan Mishchenko 590202e327 Set the failed output index if ORing of outputs was done in 'int'. 2012-04-27 16:14:40 +07:00
Alan Mishchenko 5f5dda9030 Updating the counter of finished frames when dumping intermediate abstraction in &vta. 2012-04-27 07:46:02 +07:00
Alan Mishchenko 5c683fc164 Adding iterative refinement to 'addbuffs'. 2012-04-14 15:06:41 -07:00
Alan Mishchenko 92ad58ffa2 Adding iterative refinement to 'addbuffs'. 2012-04-13 18:20:44 -07:00
Alan Mishchenko 7e21f01269 Updated used message for 'back_reach'. 2012-04-13 15:41:31 -07:00
Alan Mishchenko b1a57b2ae9 Adding iterative refinement to 'addbuffs'. 2012-04-11 16:29:08 -07:00
Alan Mishchenko 0184dab4de Adding iterative refinement to 'addbuffs'. 2012-04-11 16:00:09 -07:00
Alan Mishchenko 0d802453e4 Adding reverse order to 'addbuffs'. 2012-04-11 08:09:31 -07:00
Alan Mishchenko f380bb5ac1 Improving printouts of critical path. 2012-04-09 20:01:40 -07:00
Alan Mishchenko b9913732c4 Improving printouts of critical path. 2012-04-09 18:59:36 -07:00
Alan Mishchenko 0509440a45 Improving printouts of critical path. 2012-04-09 15:06:33 -07:00
Alan Mishchenko e908ff1cb9 Improving printouts of critical path. 2012-04-09 11:46:42 -07:00
Alan Mishchenko 48b47300e3 Added dumping abstracted model in &vta. 2012-04-07 12:43:17 -07:00
Alan Mishchenko c3d3ccf349 Better interface with the new code. 2012-04-06 22:03:00 -07:00
Alan Mishchenko 2c21e2de0d Improving printouts of critical path. 2012-04-06 13:31:03 -07:00
Alan Mishchenko 5de8e60b9f Improving printouts of critical path. 2012-04-06 12:52:26 -07:00
Alan Mishchenko 8c1513dfbc Improving printouts of critical path. 2012-04-06 00:45:58 -07:00
Alan Mishchenko 9eb1be8e53 Bug fix in 'addbuffs'. 2012-03-29 15:48:45 -07:00
Alan Mishchenko 3992e344ea Logic sharing for multi-input gates (silencing a warning). 2012-03-27 21:59:13 -07:00
Alan Mishchenko a21f2986aa Enabling mapping into multi-input AND/OR gates. 2012-03-27 20:15:02 -07:00
Alan Mishchenko 08253a50eb Logic sharing for multi-input gates (bug fix). 2012-03-26 20:21:05 -07:00
Alan Mishchenko a4144cf0d1 Making demiter dump files in the current directory. 2012-03-26 12:55:58 -07:00
Alan Mishchenko 16cf6bf1ca Logic sharing for multi-input gates. 2012-03-26 12:55:20 -07:00
Alan Mishchenko 45f07795ef Logic sharing for multi-input gates. 2012-03-25 23:10:35 -07:00
Alan Mishchenko 8ed3e40a52 Logic sharing for multi-input gates. 2012-03-25 22:47:08 -07:00
Alan Mishchenko 5f075adc19 Logic sharing for multi-input gates. 2012-03-25 16:58:40 -07:00
Alan Mishchenko b4df114e4a Logic sharing for multi-input gates. 2012-03-25 16:49:29 -07:00
Alan Mishchenko 309bcf2dec Logic sharing for multi-input gates. 2012-03-25 01:24:26 -07:00
Alan Mishchenko abb889fe6e Improving printouts of gates and support. 2012-03-24 13:15:37 -07:00
Alan Mishchenko aede5026b3 Silencing a gcc warning. 2012-03-23 22:55:45 -07:00
Alan Mishchenko 3abd9773a4 Enabled demitering dual-output miters. 2012-03-23 22:52:30 -07:00
Alan Mishchenko 1c31dbe786 Added command 'addbuffs' to create balanced CI/CO paths. 2012-03-23 22:29:25 -07:00
Alan Mishchenko 0792ab0eb6 Additional features for delay optimization 2012-03-21 23:19:49 -07:00
Alan Mishchenko f50ce3dbd9 Switching to a variable-page-size memory manager for clauses and proofs. 2012-03-21 17:13:39 -07:00
Alan Mishchenko 8f91b30a67 Bug fix to prevent crashing when Abc_Print() is called while ABC is not initialized. 2012-03-20 09:35:33 -07:00
Alan Mishchenko c347f2b90b Alternative way of computing delay in SOP balancing. 2012-03-16 15:43:08 -07:00
Alan Mishchenko aeedc6ace5 Exploration of ISO and minor changes. 2012-03-13 16:12:16 -07:00
Alan Mishchenko 795b5a6ce7 Added command 'nodedup' to duplicate nodes with high fanout. 2012-03-11 23:06:14 -07:00
Alan Mishchenko fec988f619 Renamed Aig_ObjPioNum to be Aig_ObjCioId. 2012-03-09 19:59:35 -08:00
Alan Mishchenko c46c957a07 Renamed Aig_ObjIsPi/Po to be ...Ci/Co and Aig_Man(Pi/Po)Num to be ...(Ci/Co)... 2012-03-09 19:50:18 -08:00
Alan Mishchenko 2c8f1a67ec Renamed Aig_ManForEachPi/Po to be ...Ci/Co and Aig_ObjCreatePi/Po to be ...Ci/Co. 2012-03-09 19:32:44 -08:00
Alan Mishchenko f7c7cb5c65 Adding switch '-n' to 'permute' to derive random topological ordering of internal nodes. 2012-03-06 11:53:07 +01:00
Alan Mishchenko eb4aa42577 Enabling user-specified required times in 'map'. 2012-03-02 13:50:28 -08:00
Alan Mishchenko 7fa9de2da4 Redirecting printf messages. 2012-03-02 01:31:44 -08:00
Alan Mishchenko 7926d75ecb Adding features related to the communication bridge. 2012-03-02 00:57:48 -08:00
Alan Mishchenko 3e5e7a2544 Added skipping &iso when there is only one PO. 2012-02-29 10:51:05 -08:00
Alan Mishchenko 1bf2b0351a Added skipping &iso when there is only one PO. 2012-02-29 10:38:18 -08:00
Alan Mishchenko 0b1cfe886e Added switch -z to command 'removepo' to enable removing const1 outputs. 2012-02-27 17:50:48 -08:00
Alan Mishchenko b06908d1e8 Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default (bug fix). 2012-02-25 15:54:11 -08:00
Alan Mishchenko b4fe108d86 Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default. 2012-02-24 16:11:49 -08:00
Alan Mishchenko 3552d39b71 Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default. 2012-02-24 13:37:31 -08:00
Alan Mishchenko d80f43a185 Making BMC engines (bmc2, bmc3) to perform OR-decomposition by default. 2012-02-24 13:21:32 -08:00
Alan Mishchenko 8f4457772a Added a way to disable support for dynamic linking. 2012-02-24 09:44:16 -08:00
Alan Mishchenko c20d29e7e7 Silenced a gcc warning. 2012-02-23 13:49:49 -08:00
Baruch Sterin f42131935e pyabc: silnce more warnings 2012-02-23 13:45:51 -08:00
Alan Mishchenko 1d25ae3b1a Experiment with technology mapping. 2012-02-22 17:54:24 -08:00
Alan Mishchenko d2cab85976 Adding flag -s to &put to disable status clearing. 2012-02-22 08:06:22 -08:00
Alan Mishchenko 8ba2398138 Undoing a previuos change to not reset the status after &put. 2012-02-22 00:46:52 -08:00
Alan Mishchenko db3a005402 Experiment with technology mapping. 2012-02-20 21:34:50 -08:00
Alan Mishchenko e60d6c94a3 Experiment with technology mapping. 2012-02-20 21:33:51 -08:00
Alan Mishchenko 9f71a9f67b Isomorphism checking code. 2012-02-20 16:09:20 -08:00
Alan Mishchenko 2377ae60e9 Isomorphism checking code. 2012-02-19 14:52:43 -08:00
Alan Mishchenko ea13085fe3 Added printout of BMC tents in &ps. 2012-02-19 13:33:21 -08:00
Alan Mishchenko c9147d76cc Setting the default limit on the number of timeframe in bmc2/bmc3 to 0 (infinity). 2012-02-19 09:55:52 -08:00
Alan Mishchenko 7ca9c116df Isomorphism checking code. 2012-02-18 19:20:02 -08:00
Alan Mishchenko 5d7c568589 Changes to properly save current GIA after &miter -t and not erase the comb cex after &put. 2012-02-17 15:51:12 -08:00
Alan Mishchenko ee9f66e2c4 Isomorphism checking code. 2012-02-17 13:19:09 -08:00
Alan Mishchenko f2a413029c Silencing some of the gcc warnings. 2012-02-17 12:46:08 -08:00
Alan Mishchenko 97856d021a Silencing some of the gcc warnings. 2012-02-16 23:40:23 -08:00
Alan Mishchenko 791b107e7a Silencing some of the gcc warnings. 2012-02-16 21:53:16 -08:00
Alan Mishchenko 8587ebe797 Variable timeframe abstraction. 2012-02-16 00:11:09 -08:00
Alan Mishchenko a9980135a0 Isomorphism checking code. 2012-02-14 22:15:49 -08:00
Alan Mishchenko 77b5dc261e Added restarts to PDR. 2012-02-13 23:31:01 -08:00
Alan Mishchenko d0713831a0 Lazy man's logic synthesis. 2012-02-12 17:30:05 -08:00
Alan Mishchenko d9edb7e549 Variable timeframe abstraction. 2012-02-12 02:16:36 -08:00
Alan Mishchenko 862ebb214d Variable timeframe abstraction. 2012-02-11 22:54:59 -08:00
Alan Mishchenko 49c5beefd4 Variable timeframe abstraction. 2012-02-11 22:30:04 -08:00
Alan Mishchenko 95d7b478fd Variable timeframe abstraction. 2012-02-11 21:56:05 -08:00
Alan Mishchenko 112f797c73 Added switch -f to 'print_io' to suppress printing flops. 2012-02-11 00:43:37 -08:00
Alan Mishchenko c5067f7d04 Graph isomorphism checking code. 2012-02-11 00:22:05 -08:00
Alan Mishchenko 71891354b4 Bug fixes in &cec command. 2012-02-10 00:07:31 -08:00
Alan Mishchenko 25859eefb6 Graph isomorphism checking code. 2012-02-02 15:45:48 -08:00
Alan Mishchenko 61211df4ff Lazy man's logic synthesis. 2012-02-01 12:24:04 -08:00
Alan Mishchenko 044149593d Graph isomorphism checking code. 2012-01-30 23:11:38 -08:00
Alan Mishchenko 7ea40494eb Graph isomorphism checking code. 2012-01-29 21:22:54 -08:00
Alan Mishchenko e511b87237 Moving Vec_IntPrint to where it belongs. 2012-01-29 21:22:26 -08:00
Alan Mishchenko 99b408fcb1 Generation of dual-rail miter. 2012-01-28 20:10:34 -08:00
Alan Mishchenko 5aeab257ed Generation of dual-rail miter. 2012-01-28 15:05:33 -08:00
Alan Mishchenko 7a87f20c18 Variable timeframe abstraction. 2012-01-27 00:57:42 -08:00
Alan Mishchenko ce0e8caf79 Variable timeframe abstraction. 2012-01-27 00:48:06 -08:00
Alan Mishchenko 94d35a2592 Variable timeframe abstraction. 2012-01-24 01:04:56 -08:00
Alan Mishchenko f8e933c718 Variable timeframe abstraction. 2012-01-23 13:45:46 -08:00
Alan Mishchenko c39fd3741a Added returning counter-example after BMC, which was recently added to 'dprove'. 2012-01-23 12:41:55 -08:00
Alan Mishchenko 8014f25f6d Major restructuring of the code. 2012-01-21 04:30:10 -08:00
Alan Mishchenko c44cc5de94 Deleting file added by mistake. 2012-01-20 20:30:24 -08:00
Alan Mishchenko 2c50c2c5c0 Preserving CI/CO varible names when moving between the main space and &-space. 2012-01-20 19:54:26 -08:00
Alan Mishchenko 7d4545126d Variable timeframe abstraction. 2012-01-20 19:04:01 -08:00
Alan Mishchenko b9163754b7 New hierarchy manager. 2012-01-20 09:52:38 -08:00
Alan Mishchenko ec1c45fb64 New hierarchy manager. 2012-01-19 21:09:49 -08:00
Alan Mishchenko 215d62f41f New hierarchy manager. 2012-01-19 17:18:11 -08:00
Alan Mishchenko fffd733f94 Replaced 'bmc' by 'bmc2' in 'dprove'. Added switches to 'dprove' to control BMC frames and conflicts. 2012-01-19 14:24:56 -08:00
Alan Mishchenko 0111d43b54 New hierarchy manager. 2012-01-19 12:02:07 -08:00
Alan Mishchenko 8c62c9db6c Added switch 'write_counter -f' to output flop values in each time frame. 2012-01-18 17:49:13 -08:00
Alan Mishchenko debe445063 New hierarchy manager. 2012-01-18 17:28:59 -08:00
Alan Mishchenko fe6d1ff7da New hierarchy manager. 2012-01-18 02:25:12 -08:00
Alan Mishchenko 2a236864ab Changes to the lazy man's synthesis code. 2012-01-17 23:38:11 -08:00
Alan Mishchenko d8d705c717 New hierarchy manager. 2012-01-17 23:19:47 -08:00
Alan Mishchenko 6bff2986a2 New hierarchy manager. 2012-01-17 15:02:25 -08:00
Alan Mishchenko be5256c926 New hierarchy manager. 2012-01-16 22:06:59 -08:00
Alan Mishchenko 0695ec5473 New hierarchy manager plus additional printout in the GIA package. 2012-01-16 13:07:51 -08:00
Alan Mishchenko ca28f77f3a Variable timeframe abstraction. 2012-01-16 12:21:53 -08:00
Alan Mishchenko 10478a9cbf Variable timeframe abstraction. 2012-01-15 20:47:58 -08:00
Alan Mishchenko bb4897aba6 Changes to the lazy man's synthesis code. 2012-01-15 12:35:04 -08:00
Alan Mishchenko 1f0e5533dc Several small bug fixes in the mapper. 2012-01-15 09:15:10 -08:00
Alan Mishchenko 60a84f7350 Changes to the lazy man's synthesis code. 2012-01-14 23:39:53 -08:00
Alan Mishchenko 868ed19469 Changes to the lazy man's synthesis code. 2012-01-14 22:37:25 -08:00
Alan Mishchenko ac7e665bf6 Bug fixes in the Verilog parser. 2012-01-14 22:21:23 -08:00
Alan Mishchenko c7e215ca31 New hierarchy manager. 2012-01-14 18:05:12 -08:00
Alan Mishchenko 9c409addca Support computation experiments with different network data-structures. 2012-01-14 18:04:47 -08:00
Alan Mishchenko 7a3c33e169 New hierarchy manager. 2012-01-13 22:49:08 -08:00
Alan Mishchenko 5fff8354ce New hierarchy manager. 2012-01-13 22:02:04 -08:00
Alan Mishchenko b7ba9aa8dc New hierarchy manager. 2012-01-13 20:58:28 -08:00
Alan Mishchenko 4bd7efa6cd Added counting hits and misses during structural hashing. 2012-01-13 19:31:13 -08:00
Alan Mishchenko edbff75fff New hierarchy manager. 2012-01-13 18:10:00 -08:00
Alan Mishchenko eecbbea24b New hierarchy manager. 2012-01-13 17:50:21 -08:00
Alan Mishchenko 095345fc4a Added new name manager and modified hierarchy manager to use it. 2012-01-13 15:43:09 -08:00
Alan Mishchenko cb2d12bb04 New hierarchy manager. 2012-01-13 00:34:13 -08:00
Alan Mishchenko 2e1dcdd239 Added model ID inside the design. 2012-01-12 23:29:47 -08:00
Alan Mishchenko fadde52dc6 Changes to the lazy man's synthesis code. 2012-01-11 22:08:35 -08:00
Alan Mishchenko 564a3553f0 Gate level abstraction. 2012-01-08 13:15:03 +07:00
Alan Mishchenko 376bf3a703 Bug fix: changing output number to 0 in the CEX after ORing POs. 2012-01-07 11:19:03 +07:00
Alan Mishchenko 26b87c8c55 Added warning when the network from file has no primary inputs. 2012-01-06 01:36:08 +07:00
Alan Mishchenko aec5d33889 Backward reachability using circuit cofactoring. 2012-01-01 15:58:17 +07:00
Alan Mishchenko 1e20e2ccbc Delay optimization using precomputed library. 2011-12-30 13:11:52 +07:00
Alan Mishchenko 655d452cbb Delay optimization using precomputed library. 2011-12-30 11:36:25 +07:00