mirror of https://github.com/YosysHQ/abc.git
Experiment with technology mapping.
This commit is contained in:
Alan Mishchenko
parent
18ea60a06b
commit
e60d6c94a3
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@ -279,6 +279,10 @@ SOURCE=.\src\base\abci\abcIf.c
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# End Source File
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# Begin Source File
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SOURCE=.\src\base\abci\abcIfif.c
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# End Source File
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# Begin Source File
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SOURCE=.\src\base\abci\abcIfMux.c
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# End Source File
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# Begin Source File
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@ -217,6 +217,7 @@ static int Abc_CommandSuperChoiceLut ( Abc_Frame_t * pAbc, int argc, cha
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static int Abc_CommandFpga ( Abc_Frame_t * pAbc, int argc, char ** argv );
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static int Abc_CommandFpgaFast ( Abc_Frame_t * pAbc, int argc, char ** argv );
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static int Abc_CommandIf ( Abc_Frame_t * pAbc, int argc, char ** argv );
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static int Abc_CommandIfif ( Abc_Frame_t * pAbc, int argc, char ** argv );
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static int Abc_CommandScut ( Abc_Frame_t * pAbc, int argc, char ** argv );
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static int Abc_CommandInit ( Abc_Frame_t * pAbc, int argc, char ** argv );
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@ -648,6 +649,7 @@ void Abc_Init( Abc_Frame_t * pAbc )
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Cmd_CommandAdd( pAbc, "FPGA mapping", "fpga", Abc_CommandFpga, 1 );
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Cmd_CommandAdd( pAbc, "FPGA mapping", "ffpga", Abc_CommandFpgaFast, 1 );
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Cmd_CommandAdd( pAbc, "FPGA mapping", "if", Abc_CommandIf, 1 );
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Cmd_CommandAdd( pAbc, "FPGA mapping", "ifif", Abc_CommandIfif, 1 );
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// Cmd_CommandAdd( pAbc, "Sequential", "scut", Abc_CommandScut, 0 );
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Cmd_CommandAdd( pAbc, "Sequential", "init", Abc_CommandInit, 1 );
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@ -13597,6 +13599,85 @@ usage:
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return 1;
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Abc_CommandIfif( Abc_Frame_t * pAbc, int argc, char ** argv )
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{
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extern void Abc_NtkPerformIfif( Abc_Ntk_t * pNtk, int nDelayLut, int nDegree, int fVerbose );
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Abc_Ntk_t * pNtk = Abc_FrameReadNtk(pAbc);
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int c;
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int nDelayLut = 5;
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int nDegree = 3;
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int fVerbose = 0;
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Extra_UtilGetoptReset();
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while ( ( c = Extra_UtilGetopt( argc, argv, "DNvh" ) ) != EOF )
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{
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switch ( c )
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{
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case 'D':
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if ( globalUtilOptind >= argc )
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{
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Abc_Print( -1, "Command line switch \"-D\" should be followed by a floating point number.\n" );
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goto usage;
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}
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nDelayLut = atoi(argv[globalUtilOptind]);
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globalUtilOptind++;
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if ( nDelayLut <= 0.0 )
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goto usage;
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break;
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case 'N':
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if ( globalUtilOptind >= argc )
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{
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Abc_Print( -1, "Command line switch \"-N\" should be followed by a floating point number.\n" );
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goto usage;
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}
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nDegree = atoi(argv[globalUtilOptind]);
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globalUtilOptind++;
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if ( nDegree < 0 )
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goto usage;
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break;
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case 'v':
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fVerbose ^= 1;
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break;
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case 'h':
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goto usage;
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default:
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goto usage;
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}
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}
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if ( pNtk == NULL )
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{
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Abc_Print( -1, "Empty network.\n" );
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return 1;
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}
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if ( !Abc_NtkIsLogic(pNtk) )
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{
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Abc_Print( -1, "Need mapped network.\n" );
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return 1;
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}
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Abc_NtkPerformIfif( pNtk, nDelayLut, nDegree, fVerbose );
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return 0;
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usage:
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Abc_Print( -2, "usage: ifif [-DNvh]\n" );
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Abc_Print( -2, "\t experimental technology mapper\n" );
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Abc_Print( -2, "\t-D num : the ratio of LUT delay to wire delay [default = %d]\n", nDelayLut );
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Abc_Print( -2, "\t-N num : degree of the combination of LUTs [default = %d]\n", nDegree );
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Abc_Print( -2, "\t-v : toggles verbose output [default = %s]\n", fVerbose? "yes": "no" );
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Abc_Print( -2, "\t-h : print the command usage\n");
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return 1;
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}
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/**Function*************************************************************
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@ -0,0 +1,266 @@
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/**CFile****************************************************************
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FileName [abcIfif.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Network and node package.]
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Synopsis [Experiment with technology mapping.]
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Author [Alan Mishchenko]
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Affiliation [UC Berkeley]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: abcIfif.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "src/base/abc/abc.h"
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ABC_NAMESPACE_IMPL_START
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////////////////////////////////////////////////////////////////////////
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/// DECLARATIONS ///
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////////////////////////////////////////////////////////////////////////
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typedef struct Abc_IffObj_t_ Abc_IffObj_t;
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struct Abc_IffObj_t_
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{
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int Delay0; // separate delay
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int Delay1; // combined delay
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int nLeaves;
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int pLeaves[6];
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};
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typedef struct Abc_IffMan_t_ Abc_IffMan_t;
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struct Abc_IffMan_t_
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{
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Abc_Ntk_t * pNtk;
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int nObjs;
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int nDelayLut;
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int nDegree;
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int fVerbose;
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// internal data
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Abc_IffObj_t * pObjs;
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};
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static inline Abc_IffObj_t * Abc_IffObj( Abc_IffMan_t * p, int i ) { assert( i >= 0 && i < p->nObjs ); return p->pObjs + i; }
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////////////////////////////////////////////////////////////////////////
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Abc_IffMan_t * Abc_NtkIfifStart( Abc_Ntk_t * pNtk, int nDelayLut, int nDegree, int fVerbose )
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{
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Abc_IffMan_t * p;
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p = ABC_CALLOC( Abc_IffMan_t, 1 );
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p->pNtk = pNtk;
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p->nObjs = Abc_NtkObjNumMax( pNtk );
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p->nDelayLut = nDelayLut;
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p->nDegree = nDegree;
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p->fVerbose = fVerbose;
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// internal data
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p->pObjs = ABC_CALLOC( Abc_IffObj_t, p->nObjs );
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return p;
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}
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void Abc_NtkIfifStop( Abc_IffMan_t * p )
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{
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// internal data
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ABC_FREE( p->pObjs );
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ABC_FREE( p );
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}
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/**Function*************************************************************
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Synopsis [Compare nodes by Delay1 stored in pObj->iTemp.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Abc_ObjIfifCompare( Abc_Obj_t ** pp1, Abc_Obj_t ** pp2 )
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{
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Abc_Obj_t * pObj1 = *pp1;
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Abc_Obj_t * pObj2 = *pp2;
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assert( Abc_ObjIsNode(pObj1) && Abc_ObjIsNode(pObj2) );
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return (int)pObj2->iTemp - (int)pObj1->iTemp;
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}
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/**Function*************************************************************
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Synopsis [This is the delay which object may have all by itself.]
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Description [This delay is stored in Delay0.]
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Abc_ObjDelay0( Abc_IffMan_t * p, Abc_Obj_t * pObj )
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{
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Abc_Obj_t * pFanin;
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int i, Delay0 = 0;
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Abc_ObjForEachFanin( pObj, pFanin, i )
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Delay0 = Abc_MaxInt( Delay0, Abc_IffObj(p, Abc_ObjId(pFanin))->Delay1 );
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return p->nDelayLut + Delay0;
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}
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/**Function*************************************************************
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Synopsis [This is the delay object may have in a group.]
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Description [This delay is stored in Delay1 and pObj->iTemp.]
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SideEffects []
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SeeAlso []
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***********************************************************************/
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int Abc_ObjDelay1( Abc_IffMan_t * p, Abc_Obj_t * pObj )
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{
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Abc_IffObj_t * pIfif;
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Abc_Obj_t * pNodes[6], * pFanin;
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int i, nNodes, Delay1, DelayWorst;
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// find the object structure
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pIfif = Abc_IffObj( p, Abc_ObjId(pObj) );
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// collect relevant nodes
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nNodes = 0;
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Abc_ObjForEachFanin( pObj, pFanin, i )
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if ( Abc_ObjIsNode(pFanin) )
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{
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assert( pFanin->iTemp >= p->nDelayLut );
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pNodes[nNodes++] = pFanin;
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}
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// process the result
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Delay1 = 0;
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pIfif->nLeaves = 0;
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if ( nNodes > 0 )
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{
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int fVerbose = 0;
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// sort fanins by delay
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qsort( (void *)pNodes, nNodes, sizeof(Abc_Obj_t *), (int (*)(const void *, const void *)) Abc_ObjIfifCompare );
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assert( pNodes[0]->iTemp >= pNodes[nNodes-1]->iTemp );
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if ( fVerbose )
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{
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for ( i = 0; i < nNodes; i++ )
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{
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printf( "Fanin %d : ", i );
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printf( "D0 %4d ", Abc_IffObj(p, Abc_ObjId(pNodes[i]))->Delay0 );
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printf( "D0* %4d ", Abc_IffObj(p, Abc_ObjId(pNodes[0]))->Delay0 - (p->nDelayLut-1) );
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printf( "D1 %4d ", Abc_IffObj(p, Abc_ObjId(pNodes[i]))->Delay1 );
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printf( "\n" );
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}
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printf( "\n" );
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}
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// get the worst-case fanin delay
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// DelayWorst = Abc_IffObj(p, Abc_ObjId(pNodes[0]))->Delay0 - (p->nDelayLut-1);
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DelayWorst = -1;
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// find the delay and remember fanins
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for ( i = 0; i < nNodes; i++ )
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{
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if ( pIfif->nLeaves < p->nDegree && Abc_IffObj(p, Abc_ObjId(pNodes[i]))->Delay1 > DelayWorst )
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{
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Delay1 = Abc_MaxInt( Delay1, Abc_IffObj(p, Abc_ObjId(pNodes[i]))->Delay0 - (p->nDelayLut-1) );
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pIfif->pLeaves[pIfif->nLeaves++] = Abc_ObjId(pNodes[i]);
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}
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else
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Delay1 = Abc_MaxInt( Delay1, Abc_IffObj(p, Abc_ObjId(pNodes[i]))->Delay1 );
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}
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// assert( pIfif->nLeaves > 0 );
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assert( Delay1 > 0 );
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}
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return p->nDelayLut + Delay1;
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Abc_NtkPerformIfif( Abc_Ntk_t * pNtk, int nDelayLut, int nDegree, int fVerbose )
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{
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Abc_IffMan_t * p;
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Abc_IffObj_t * pIffObj;
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Vec_Ptr_t * vNodes;
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Abc_Obj_t * pObj;
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int i, Delay, nLutSize = Abc_NtkGetFaninMax( pNtk );
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if ( nLutSize > 6 )
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{
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printf( "LUT size (%d) is more than 6.\n", nLutSize );
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return;
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}
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// convert to AIGs
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Abc_NtkToAig( pNtk );
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assert( nDegree >= 0 && nDegree <= 6 );
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// start manager
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p = Abc_NtkIfifStart( pNtk, nDelayLut, nDegree, fVerbose );
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// printf( "Running experiment with LUT delay %d and degree %d (LUT size is %d).\n", nDelayLut, nDegree, nLutSize );
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// compute the delay
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vNodes = Abc_NtkDfs( pNtk, 0 );
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Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
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{
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assert( Abc_ObjIsNode(pObj) );
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pIffObj = Abc_IffObj( p, Abc_ObjId(pObj) );
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pIffObj->Delay0 = Abc_ObjDelay0( p, pObj );
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pIffObj->Delay1 = Abc_ObjDelay1( p, pObj );
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pObj->iTemp = pIffObj->Delay1;
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// printf( "Node %3d : Lev =%3d Delay0 =%4d Delay1 =%4d Leaves =%3d.\n",
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// Abc_ObjId(pObj), Abc_ObjLevel(pObj), pIffObj->Delay0, pIffObj->Delay1, pIffObj->nLeaves );
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}
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Vec_PtrFree( vNodes );
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// consider delay at the outputs
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Delay = 0;
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Abc_NtkForEachCo( pNtk, pObj, i )
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Delay = Abc_MaxInt( Delay, Abc_IffObj(p, Abc_ObjId(Abc_ObjFanin0(pObj)))->Delay1 );
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printf( "Critical delay is %5d (%7.2f).\n", Delay, 1.0 * Delay / nDelayLut );
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// derive a new network
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// stop manager
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Abc_NtkIfifStop( p );
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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ABC_NAMESPACE_IMPL_END
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