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Fixes to Verilog parser.

This commit is contained in:
Alan Mishchenko 2012-09-20 11:29:37 -07:00
parent 723f85ef1b
commit f59de3decc
3 changed files with 9 additions and 3 deletions
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4
src/base/abc/abc.h
View File

@ -192,8 +192,8 @@ struct Abc_Ntk_t_
int iStep; // the generation number for the given network
// hierarchy
Abc_Lib_t * pDesign;
short fHieVisited; // flag to mark the visited network
short fHiePath; // flag to mark the network on the path
int fHieVisited; // flag to mark the visited network
int fHiePath; // flag to mark the network on the path
int Id; // model ID
double dTemp; // temporary value
// miscellaneous data members

6
src/base/io/io.c
View File

@ -197,6 +197,12 @@ int IoCommandRead( Abc_Frame_t * pAbc, int argc, char ** argv )
for ( pTemp = pFileName; *pTemp; pTemp++ )
if ( *pTemp == '>' )
*pTemp = '\\';
// check if the library is available
if ( glo_fMapped && Abc_FrameReadLibGen() == NULL )
{
Abc_Print( 1, "Cannot read mapped design when the library is not given.\n" );
return 0;
}
// read the file using the corresponding file reader
pNtk = Io_Read( pFileName, Io_ReadFileType(pFileName), fCheck );
if ( pNtk == NULL )

2
src/base/ver/verCore.c
View File

@ -2538,7 +2538,7 @@ int Ver_ParseDriveFormal( Ver_Man_t * pMan, Abc_Ntk_t * pNtk, Ver_Bundle_t * pBu
Vec_PtrForEachEntry( Abc_Obj_t *, pBundle->vNetsActual, pNetAct, m )
if ( Abc_ObjFaninNum(pNetAct) > 0 )
{
sprintf( pMan->sError, "Internal error while trying to connect undefined boxes. It is likely that the algorithm currently used has its limitations." );
sprintf( pMan->sError, "Missing specification of the I/Os of undefined box \"%s\".", Abc_NtkName(pNtk) );
Ver_ParsePrintErrorMessage( pMan );
return 0;
}