mirror of https://github.com/YosysHQ/abc.git
Enabling multi-output solving in 'pdr'.
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@ -2738,7 +2738,7 @@ int Abc_NtkDarPdr( Abc_Ntk_t * pNtk, Pdr_Par_t * pPars, Abc_Cex_t ** ppCex )
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if ( RetValue == 1 )
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Abc_Print( 1, "Property proved. " );
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else if ( RetValue == 0 )
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Abc_Print( 1, "Output %d of miter \"%s\" was asserted in frame %d. ", (*ppCex)->iPo, pNtk->pName, ppCex? (*ppCex)->iFrame : -1 );
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Abc_Print( 1, "Output %d of miter \"%s\" was asserted in frame %d. ", pMan->pSeqModel->iPo, pNtk->pName, pMan->pSeqModel->iFrame );
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else if ( RetValue == -1 )
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Abc_Print( 1, "Property UNDECIDED. " );
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else
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@ -2746,6 +2746,14 @@ int Abc_NtkDarPdr( Abc_Ntk_t * pNtk, Pdr_Par_t * pPars, Abc_Cex_t ** ppCex )
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ABC_PRT( "Time", clock() - clk );
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}
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// ABC_FREE( pNtk->pSeqModel );
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// pNtk->pSeqModel = pMan->pSeqModel; pMan->pSeqModel = NULL;
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if ( ppCex )
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*ppCex = pMan->pSeqModel;
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else
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ABC_FREE( pMan->pSeqModel );
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pMan->pSeqModel = NULL;
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if ( *ppCex && !Saig_ManVerifyCex( pMan, *ppCex ) )
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Abc_Print( 1, "Abc_NtkDarPdr(): Counter-example verification has FAILED.\n" );
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Aig_ManStop( pMan );
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