mirror of https://github.com/YosysHQ/abc.git
Enabling multi-output solving in 'pdr'.
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8761942258
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@ -2719,7 +2719,9 @@ int Abc_NtkDarPdr( Abc_Ntk_t * pNtk, Pdr_Par_t * pPars )
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RetValue = Pdr_ManSolve( pMan, pPars );
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if ( !pPars->fSilent )
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{
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if ( pPars->fSolveAll )
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if ( RetValue == 1 )
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Abc_Print( 1, "Property proved. " );
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else if ( pPars->fSolveAll )
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{
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int nOutputs = Saig_ManPoNum(pMan) - Saig_ManConstrNum(pMan);
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if ( pMan->vSeqModelVec == NULL || Vec_PtrCountZero(pMan->vSeqModelVec) == nOutputs )
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@ -2732,9 +2734,7 @@ int Abc_NtkDarPdr( Abc_Ntk_t * pNtk, Pdr_Par_t * pPars )
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}
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else
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{
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if ( RetValue == 1 )
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Abc_Print( 1, "Property proved. " );
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else if ( RetValue == 0 )
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if ( RetValue == 0 )
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{
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if ( pMan->pSeqModel == NULL )
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Abc_Print( 1, "Abc_NtkDarPdr(): Counter-example is not available.\n" );
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@ -590,7 +590,7 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
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if ( p->pPars->nFailOuts == Saig_ManPoNum(p->pAig) )
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return 0; // all SAT
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continue;
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}
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}
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// try to solve this output
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while ( 1 )
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{
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@ -624,6 +624,7 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
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}
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if ( RetValue == 0 )
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{
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Abc_Cex_t * pCex;
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if ( fPrintClauses )
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{
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Abc_Print( 1, "*** Clauses after frame %d:\n", k );
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@ -639,12 +640,13 @@ int Pdr_ManSolveInt( Pdr_Man_t * p )
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return 0; // SAT
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}
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p->pPars->nFailOuts++;
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Abc_Print( 1, "Output %*d was asserted in frame %2d (solved %*d out of %*d outputs).\n",
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nOutDigits, p->iOutCur, k, nOutDigits, p->pPars->nFailOuts, nOutDigits, Saig_ManPoNum(p->pAig) );
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if ( p->vCexes == NULL )
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p->vCexes = Vec_PtrStart( Saig_ManPoNum(p->pAig) );
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assert( Vec_PtrEntry(p->vCexes, p->iOutCur) == NULL );
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Vec_PtrWriteEntry( p->vCexes, p->iOutCur, Pdr_ManDeriveCex(p) );
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pCex = Pdr_ManDeriveCex(p);
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Vec_PtrWriteEntry( p->vCexes, p->iOutCur, pCex );
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Abc_Print( 1, "Output %*d was asserted in frame %2d (%2d) (solved %*d out of %*d outputs).\n",
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nOutDigits, p->iOutCur, pCex->iFrame, k, nOutDigits, p->pPars->nFailOuts, nOutDigits, Saig_ManPoNum(p->pAig) );
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if ( p->pPars->nFailOuts == Saig_ManPoNum(p->pAig) )
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return 0; // all SAT
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Pdr_QueueClean( p );
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@ -182,6 +182,9 @@ void Pdr_ManSetPropertyOutput( Pdr_Man_t * p, int k )
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pSat = Pdr_ManSolver(p, k);
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Saig_ManForEachPo( p->pAig, pObj, i )
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{
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// skip solved outputs
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if ( p->vCexes && Vec_PtrEntry(p->vCexes, i) )
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continue;
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Lit = toLitCond( Pdr_ObjSatVar(p, k, pObj), 1 ); // neg literal
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RetValue = sat_solver_addclause( pSat, &Lit, &Lit + 1 );
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assert( RetValue == 1 );
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@ -350,6 +350,7 @@ void Pdr_ManPrintCex( Aig_Man_t * pAig, Vec_Int_t * vCiObjs, Vec_Int_t * vCiVals
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***********************************************************************/
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Pdr_Set_t * Pdr_ManTernarySim( Pdr_Man_t * p, int k, Pdr_Set_t * pCube )
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{
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Pdr_Set_t * pRes;
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Vec_Int_t * vPrio = p->vPrio; // priority flops (flop indices)
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Vec_Int_t * vPiLits = p->vLits; // array of literals (0/1 PI values)
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Vec_Int_t * vCiObjs = p->vCiObjs; // cone leaves (CI obj IDs)
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@ -474,7 +475,9 @@ Pdr_ManPrintCex( p->pAig, vCiObjs, vCiVals, vCi2Rem );
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Pdr_ManDeriveResult( p->pAig, vCiObjs, vCiVals, vCi2Rem, vRes, vPiLits );
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assert( Vec_IntSize(vRes) > 0 );
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p->tTsim += clock() - clk;
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return Pdr_SetCreate( vRes, vPiLits );
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pRes = Pdr_SetCreate( vRes, vPiLits );
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assert( k == 0 || !Pdr_SetIsInit(pRes, -1) );
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return pRes;
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}
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////////////////////////////////////////////////////////////////////////
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@ -515,6 +515,7 @@ void Pdr_QueueClean( Pdr_Man_t * p )
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Pdr_Obl_t * pThis;
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while ( (pThis = Pdr_QueuePop(p)) )
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Pdr_OblDeref( pThis );
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pThis = NULL;
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}
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/**Function*************************************************************
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