mirror of https://github.com/YosysHQ/abc.git
Logic sharing for multi-input gates.
This commit is contained in:
Alan Mishchenko
parent
45f07795ef
commit
16cf6bf1ca
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@ -315,17 +315,19 @@ void Abc_NtkTraverseSupers( Abc_ShaMan_t * p, int fAnd )
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int i, nOnesMax;
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// create mapping of nodes into their column vectors
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vInputs = Vec_PtrStart( Abc_NtkObjNumMax(p->pNtk) );
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vInputs = Vec_PtrStart( Abc_NtkObjNumMax(p->pNtk) * (1 + fAnd) );
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Abc_NtkIncrementTravId( p->pNtk );
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if ( fAnd )
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{
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Abc_NtkForEachCo( p->pNtk, pObj, i )
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Abc_NtkTraverseSupersAnd_rec( p, Abc_ObjFanin0(pObj), vInputs );
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if ( Abc_ObjIsNode(Abc_ObjFanin0(pObj)) )
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Abc_NtkTraverseSupersAnd_rec( p, Abc_ObjFanin0(pObj), vInputs );
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}
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else
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{
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Abc_NtkForEachCo( p->pNtk, pObj, i )
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Abc_NtkTraverseSupersXor_rec( p, Abc_ObjFanin0(pObj), vInputs );
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if ( Abc_ObjIsNode(Abc_ObjFanin0(pObj)) )
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Abc_NtkTraverseSupersXor_rec( p, Abc_ObjFanin0(pObj), vInputs );
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}
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p->nStartCols = Vec_IntSize(p->vObj2Lit);
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@ -646,7 +648,10 @@ Abc_Ntk_t * Abc_NtkUpdateNetwork( Abc_ShaMan_t * p, int fAnd )
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// create map of originals
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vMap2Repl = Vec_IntStartFull( Abc_NtkObjNumMax(p->pNtk) );
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Vec_PtrForEachEntry( Abc_Obj_t *, vOrig, pObj, i )
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{
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// printf( "Replacing %d by %d.\n", Abc_ObjId(pObj), Abc_ObjToLit((Abc_Obj_t *)Vec_PtrEntry(vRepl, i)) );
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Vec_IntWriteEntry( vMap2Repl, Abc_ObjId(pObj), Abc_ObjToLit((Abc_Obj_t *)Vec_PtrEntry(vRepl, i)) );
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}
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Vec_PtrFree( vOrig );
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Vec_PtrFree( vRepl );
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@ -660,7 +665,7 @@ Abc_Ntk_t * Abc_NtkUpdateNetwork( Abc_ShaMan_t * p, int fAnd )
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{
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if ( iLit == iLitConst1 && fAnd )
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{
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pObj->fCompl0 = 1;
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pObj->fCompl0 ^= 1;
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Vec_IntWriteEntry( &pObj->vFanins, 0, Abc_Lit2Var(iLitConst1) );
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}
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else
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@ -677,7 +682,7 @@ Abc_Ntk_t * Abc_NtkUpdateNetwork( Abc_ShaMan_t * p, int fAnd )
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{
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if ( iLit == iLitConst1 && fAnd )
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{
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pObj->fCompl1 = 1;
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pObj->fCompl1 ^= 1;
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Vec_IntWriteEntry( &pObj->vFanins, 1, Abc_Lit2Var(iLitConst1) );
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}
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else
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@ -34,6 +34,150 @@ ABC_NAMESPACE_IMPL_START
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/// FUNCTION DEFINITIONS ///
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////////////////////////////////////////////////////////////////////////
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static inline word Dar_BalPack( int Lev, int Id ) { return (((word)Lev) << 32) | Id; }
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static inline int Dar_BalUnpackLev( word Num ) { return (Num >> 32); }
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static inline int Dar_BalUnpackId( word Num ) { return Num & 0xFFFF; }
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/**Function*************************************************************
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Synopsis [Collects one multi-input gate.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Vec_Wrd_t * Dar_BalSuperXor( Aig_Man_t * p, Aig_Obj_t * pObj, int * pfCompl )
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{
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Aig_Obj_t * pObj0, * pObj1, * pRoot = NULL;
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Vec_Wrd_t * vSuper;
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word Num, NumNext;
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int i, k, fCompl = 0;
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assert( !Aig_IsComplement(pObj) );
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assert( Aig_ObjIsExor(pObj) );
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// start iteration
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vSuper = Vec_WrdAlloc( 10 );
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Vec_WrdPush( vSuper, Dar_BalPack(Aig_ObjLevel(pObj), Aig_ObjId(pObj)) );
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while ( Vec_WrdSize(vSuper) > 0 && Vec_WrdSize(vSuper) < 10000 )
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{
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// make sure there are no duplicates
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Num = Vec_WrdEntry( vSuper, 0 );
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Vec_WrdForEachEntryStart( vSuper, NumNext, i, 1 )
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{
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assert( Num < NumNext );
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Num = NumNext;
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}
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// extract XOR gate decomposable on the topmost level
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Vec_WrdForEachEntryReverse( vSuper, Num, i )
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{
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pRoot = Aig_ManObj( p, Dar_BalUnpackId(Num) );
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if ( Aig_ObjIsExor(pRoot) && Aig_ObjRefs(pRoot) == 1 )
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{
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Vec_WrdRemove( vSuper, Num );
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break;
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}
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}
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if ( i == -1 )
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break;
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// extract
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assert( !Aig_ObjFaninC0(pObj) && !Aig_ObjFaninC1(pObj) );
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pObj0 = Aig_ObjChild0(pObj);
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pObj1 = Aig_ObjChild1(pObj);
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fCompl ^= Aig_IsComplement(pObj0); pObj0 = Aig_Regular(pObj0);
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fCompl ^= Aig_IsComplement(pObj1); pObj1 = Aig_Regular(pObj1);
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Vec_WrdPushOrder( vSuper, Dar_BalPack(Aig_ObjLevel(pObj0), Aig_ObjId(pObj0)) );
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Vec_WrdPushOrder( vSuper, Dar_BalPack(Aig_ObjLevel(pObj1), Aig_ObjId(pObj1)) );
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// remove duplicates
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k = 0;
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Vec_WrdForEachEntry( vSuper, Num, i )
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{
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if ( i + 1 == Vec_WrdSize(vSuper) )
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{
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Vec_WrdWriteEntry( vSuper, k++, Num );
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break;
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}
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NumNext = Vec_WrdEntry( vSuper, i+1 );
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assert( Num <= NumNext );
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if ( Num == NumNext )
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i++;
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else
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Vec_WrdWriteEntry( vSuper, k++, Num );
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}
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Vec_WrdShrink( vSuper, k );
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}
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*pfCompl = fCompl;
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Vec_WrdForEachEntry( vSuper, Num, i )
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Vec_WrdWriteEntry( vSuper, i, Dar_BalUnpackId(Num) );
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return vSuper;
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}
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Vec_Wrd_t * Dar_BalSuperAnd( Aig_Man_t * p, Aig_Obj_t * pObj )
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{
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Aig_Obj_t * pObj0, * pObj1, * pRoot = NULL;
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Vec_Wrd_t * vSuper;
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word Num, NumNext;
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int i, k;
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assert( !Aig_IsComplement(pObj) );
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// start iteration
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vSuper = Vec_WrdAlloc( 10 );
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Vec_WrdPush( vSuper, Dar_BalPack(Aig_ObjLevel(pObj), Aig_ObjToLit(pObj)) );
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while ( Vec_WrdSize(vSuper) > 0 && Vec_WrdSize(vSuper) < 10000 )
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{
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// make sure there are no duplicates
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Num = Vec_WrdEntry( vSuper, 0 );
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Vec_WrdForEachEntryStart( vSuper, NumNext, i, 1 )
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{
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assert( Num < NumNext );
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Num = NumNext;
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}
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// extract AND gate decomposable on the topmost level
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Vec_WrdForEachEntryReverse( vSuper, Num, i )
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{
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pRoot = Aig_ObjFromLit( p, Dar_BalUnpackId(Num) );
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if ( !Aig_IsComplement(pRoot) && Aig_ObjIsNode(pRoot) && Aig_ObjRefs(pRoot) == 1 )
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{
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Vec_WrdRemove( vSuper, Num );
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break;
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}
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}
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if ( i == -1 )
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break;
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// extract
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pObj0 = Aig_ObjChild0(pRoot);
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pObj1 = Aig_ObjChild1(pRoot);
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Vec_WrdPushOrder( vSuper, Dar_BalPack(Aig_ObjLevel(Aig_Regular(pObj0)), Aig_ObjToLit(pObj0)) );
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Vec_WrdPushOrder( vSuper, Dar_BalPack(Aig_ObjLevel(Aig_Regular(pObj1)), Aig_ObjToLit(pObj1)) );
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// remove duplicates
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k = 0;
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Vec_WrdForEachEntry( vSuper, Num, i )
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{
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if ( i + 1 == Vec_WrdSize(vSuper) )
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{
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Vec_WrdWriteEntry( vSuper, k++, Num );
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break;
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}
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NumNext = Vec_WrdEntry( vSuper, i+1 );
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assert( Num <= NumNext );
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if ( Num + 1 == NumNext && (NumNext & 1) ) // pos_lit & neg_lit = 0
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{
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Vec_WrdClear( vSuper );
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return vSuper;
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}
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if ( Num < NumNext )
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Vec_WrdWriteEntry( vSuper, k++, Num );
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}
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Vec_WrdShrink( vSuper, k );
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}
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Vec_WrdForEachEntry( vSuper, Num, i )
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Vec_WrdWriteEntry( vSuper, i, Dar_BalUnpackId(Num) );
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return vSuper;
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}
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/**Function*************************************************************
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Synopsis [Collects the nodes of the supergate.]
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@ -103,7 +247,7 @@ int Dar_BalanceCone_rec( Aig_Obj_t * pRoot, Aig_Obj_t * pObj, Vec_Ptr_t * vSuper
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SeeAlso []
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***********************************************************************/
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Vec_Ptr_t * Dar_BalanceCone( Aig_Obj_t * pObj, Vec_Vec_t * vStore, int Level )
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Vec_Ptr_t * Dar_BalanceCone( Aig_Man_t * p, Aig_Obj_t * pObj, Vec_Vec_t * vStore, int Level )
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{
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Vec_Ptr_t * vNodes;
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int RetValue, i;
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@ -127,6 +271,50 @@ Vec_Ptr_t * Dar_BalanceCone( Aig_Obj_t * pObj, Vec_Vec_t * vStore, int Level )
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return vNodes;
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}
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/**Function*************************************************************
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Synopsis [Collects the nodes of the supergate.]
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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Vec_Ptr_t * Dar_BalanceCone_( Aig_Man_t * p, Aig_Obj_t * pObj, Vec_Vec_t * vStore, int Level )
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{
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Vec_Wrd_t * vSuper;
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Vec_Ptr_t * vNodes;
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word Num;
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int i;
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assert( !Aig_IsComplement(pObj) );
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// extend the storage
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if ( Vec_VecSize( vStore ) <= Level )
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Vec_VecPush( vStore, Level, 0 );
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// get the temporary array of nodes
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vNodes = Vec_VecEntry( vStore, Level );
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Vec_PtrClear( vNodes );
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// collect the nodes in the implication supergate
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// load the result into the output array
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if ( Aig_ObjIsExor(pObj) )
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{
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int fCompl = 0;
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vSuper = Dar_BalSuperXor( p, pObj, &fCompl );
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Vec_WrdForEachEntry( vSuper, Num, i )
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Vec_PtrPush( vNodes, Aig_ManObj(p, Dar_BalUnpackId(Num)) );
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assert( fCompl == 0 );
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}
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else
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{
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vSuper = Dar_BalSuperAnd( p, pObj );
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Vec_WrdForEachEntry( vSuper, Num, i )
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Vec_PtrPush( vNodes, Aig_ObjFromLit(p, Dar_BalUnpackId(Num)) );
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}
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Vec_WrdFree( vSuper );
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return vNodes;
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}
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/**Function*************************************************************
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Synopsis [Finds the left bound on the next candidate to be paired.]
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@ -404,7 +592,7 @@ Aig_Obj_t * Dar_BalanceBuildSuperTop( Aig_Man_t * p, Vec_Ptr_t * vSuper, Aig_Typ
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SeeAlso []
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***********************************************************************/
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Aig_Obj_t * Dar_Balance_rec( Aig_Man_t * pNew, Aig_Obj_t * pObjOld, Vec_Vec_t * vStore, int Level, int fUpdateLevel )
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Aig_Obj_t * Dar_Balance_rec( Aig_Man_t * pNew, Aig_Man_t * p, Aig_Obj_t * pObjOld, Vec_Vec_t * vStore, int Level, int fUpdateLevel )
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{
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Aig_Obj_t * pObjNew;
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Vec_Ptr_t * vSuper;
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@ -416,7 +604,7 @@ Aig_Obj_t * Dar_Balance_rec( Aig_Man_t * pNew, Aig_Obj_t * pObjOld, Vec_Vec_t *
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return (Aig_Obj_t *)pObjOld->pData;
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assert( Aig_ObjIsNode(pObjOld) );
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// get the implication supergate
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vSuper = Dar_BalanceCone( pObjOld, vStore, Level );
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vSuper = Dar_BalanceCone( p, pObjOld, vStore, Level );
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// check if supergate contains two nodes in the opposite polarity
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if ( vSuper->nSize == 0 )
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return (Aig_Obj_t *)(pObjOld->pData = Aig_ManConst0(pNew));
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@ -427,7 +615,7 @@ Aig_Obj_t * Dar_Balance_rec( Aig_Man_t * pNew, Aig_Obj_t * pObjOld, Vec_Vec_t *
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// for each old node, derive the new well-balanced node
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for ( i = 0; i < Vec_PtrSize(vSuper); i++ )
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{
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pObjNew = Dar_Balance_rec( pNew, Aig_Regular((Aig_Obj_t *)vSuper->pArray[i]), vStore, Level + 1, fUpdateLevel );
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pObjNew = Dar_Balance_rec( pNew, p, Aig_Regular((Aig_Obj_t *)vSuper->pArray[i]), vStore, Level + 1, fUpdateLevel );
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vSuper->pArray[i] = Aig_NotCond( pObjNew, Aig_IsComplement((Aig_Obj_t *)vSuper->pArray[i]) );
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}
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// build the supergate
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@ -514,7 +702,7 @@ Aig_Man_t * Dar_ManBalance( Aig_Man_t * p, int fUpdateLevel )
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{
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// perform balancing
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pDriver = Aig_ObjReal_rec( Aig_ObjChild0(pObj) );
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pObjNew = Dar_Balance_rec( pNew, Aig_Regular(pDriver), vStore, 0, fUpdateLevel );
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pObjNew = Dar_Balance_rec( pNew, p, Aig_Regular(pDriver), vStore, 0, fUpdateLevel );
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pObjNew = Aig_NotCond( pObjNew, Aig_IsComplement(pDriver) );
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// save arrival time of the output
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arrTime = (float)Aig_Regular(pObjNew)->Level;
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@ -541,7 +729,7 @@ Aig_Man_t * Dar_ManBalance( Aig_Man_t * p, int fUpdateLevel )
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Aig_ManForEachCo( p, pObj, i )
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{
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pDriver = Aig_ObjReal_rec( Aig_ObjChild0(pObj) );
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pObjNew = Dar_Balance_rec( pNew, Aig_Regular(pDriver), vStore, 0, fUpdateLevel );
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pObjNew = Dar_Balance_rec( pNew, p, Aig_Regular(pDriver), vStore, 0, fUpdateLevel );
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pObjNew = Aig_NotCond( pObjNew, Aig_IsComplement(pDriver) );
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pObjNew = Aig_ObjCreateCo( pNew, pObjNew );
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pObjNew->pHaig = pObj->pHaig;
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@ -640,6 +828,5 @@ void Dar_BalancePrintStats( Aig_Man_t * p )
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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ABC_NAMESPACE_IMPL_END
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