mirror of https://github.com/YosysHQ/abc.git
Added model ID inside the design.
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@ -193,6 +193,7 @@ struct Abc_Ntk_t_
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Abc_Lib_t * pDesign;
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short fHieVisited; // flag to mark the visited network
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short fHiePath; // flag to mark the network on the path
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int Id; // model ID
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// miscellaneous data members
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int nTravIds; // the unique traversal IDs of nodes
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Mem_Fixed_t * pMmObj; // memory manager for objects
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@ -174,6 +174,8 @@ int Abc_LibAddModel( Abc_Lib_t * pLib, Abc_Ntk_t * pNtk )
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if ( st_is_member( pLib->tModules, (char *)pNtk->pName ) )
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return 0;
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st_insert( pLib->tModules, (char *)pNtk->pName, (char *)pNtk );
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assert( pNtk->Id == 0 );
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pNtk->Id = Vec_PtrSize(pLib->vModules);
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Vec_PtrPush( pLib->vModules, pNtk );
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pNtk->pDesign = pLib;
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return 1;
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