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Bug fixes in the Verilog parser.

This commit is contained in:
Alan Mishchenko 2012-01-14 22:21:23 -08:00
parent c7e215ca31
commit ac7e665bf6
4 changed files with 16 additions and 6 deletions
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4
src/base/abc/abcHie.c
View File

@ -463,6 +463,8 @@ void Abc_NtkPrintBoxInfo( Abc_Ntk_t * pNtk )
Abc_NtkForEachBox( pModel, pObj, k )
{
pBoxModel = (Abc_Ntk_t *)pObj->pData;
if ( pBoxModel == NULL )
continue;
Num = Vec_PtrFind( vMods, pBoxModel );
assert( Num >= 0 && Num < Vec_PtrSize(vMods) );
Vec_IntAddToEntry( vCounts, Num, 1 );
@ -474,7 +476,7 @@ void Abc_NtkPrintBoxInfo( Abc_Ntk_t * pNtk )
printf( "PI=%6d ", Abc_NtkPiNum(pModel) );
printf( "PO=%6d ", Abc_NtkPoNum(pModel) );
printf( "BB=%6d ", Abc_NtkBoxNum(pModel) );
printf( "ND=%6d ", Abc_NtkNodeNum(pModel)-2 ); // sans constants
printf( "ND=%6d ", Abc_NtkNodeNum(pModel) ); // sans constants
printf( "Lev=%5d ", Abc_NtkLevel(pModel) );
printf( "\n" );

14
src/base/io/ioReadVerilog.c
View File

@ -47,9 +47,9 @@ ABC_NAMESPACE_IMPL_START
***********************************************************************/
Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck )
{
Abc_Ntk_t * pNtk;
Abc_Ntk_t * pNtk, * pTemp;
Abc_Lib_t * pDesign;
int RetValue;
int i, RetValue;
// parse the verilog file
pDesign = Ver_ParseFile( pFileName, NULL, fCheck, 1 );
@ -60,8 +60,13 @@ Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck )
RetValue = Abc_LibFindTopLevelModels( pDesign );
pNtk = (Abc_Ntk_t *)Vec_PtrEntry( pDesign->vTops, 0 );
if ( RetValue > 1 )
printf( "Warning: The design has %d root-level modules. The first one (%s) will be used.\n",
Vec_PtrSize(pDesign->vTops), pNtk->pName );
{
printf( "Warning: The design has %d root-level modules: ", Vec_PtrSize(pDesign->vTops) );
Vec_PtrForEachEntry( Abc_Ntk_t *, pDesign->vTops, pTemp, i )
printf( " %s", Abc_NtkName(pTemp) );
printf( "\n" );
printf( "The first one (%s) will be used.\n", pNtk->pName );
}
// extract the master network
pNtk->pDesign = pDesign;
@ -83,6 +88,7 @@ Abc_Ntk_t * Io_ReadVerilog( char * pFileName, int fCheck )
}
//Io_WriteVerilog( pNtk, "_temp.v" );
Abc_NtkPrintBoxInfo( pNtk );
return pNtk;
}

2
src/base/ver/verCore.c
View File

@ -1098,6 +1098,8 @@ int Ver_ParseAssign( Ver_Man_t * pMan, Abc_Ntk_t * pNtk )
pWord = Ver_ParseGetName( pMan );
if ( pWord == NULL )
return 0;
if ( strcmp(pWord, "#1") == 0 )
continue;
// check for vector-inputs
if ( !Ver_ParseLookupSuffix( pMan, pWord, &nMsb, &nLsb ) )
return 0;

2
src/base/ver/verParse.c
View File

@ -116,7 +116,7 @@ char * Ver_ParseGetName( Ver_Man_t * pMan )
}
else
pWord = Ver_StreamGetWord( p, " \t\n\r(),;" );
if ( !Ver_ParseSkipComments( pMan ) )
if ( Ver_StreamIsOkey(p) && !Ver_ParseSkipComments( pMan ) )
return NULL;
return pWord;
}