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Handling constant nodes in gate sizing.

This commit is contained in:
Alan Mishchenko 2012-08-30 13:58:26 -07:00
parent b9a1c6ec87
commit 3400670839
6 changed files with 12 additions and 8 deletions
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3
src/base/abc/abc.h
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@ -463,6 +463,9 @@ static inline void Abc_ObjSetMvVar( Abc_Obj_t * pObj, void * pV) { Vec_At
#define Abc_NtkForEachNode( pNtk, pNode, i ) \
for ( i = 0; (i < Vec_PtrSize((pNtk)->vObjs)) && (((pNode) = Abc_NtkObj(pNtk, i)), 1); i++ ) \
if ( (pNode) == NULL || !Abc_ObjIsNode(pNode) ) {} else
#define Abc_NtkForEachNode1( pNtk, pNode, i ) \
for ( i = 0; (i < Vec_PtrSize((pNtk)->vObjs)) && (((pNode) = Abc_NtkObj(pNtk, i)), 1); i++ ) \
if ( (pNode) == NULL || !Abc_ObjIsNode(pNode) || !Abc_ObjFaninNum(pNode) ) {} else
#define Abc_NtkForEachNodeReverse( pNtk, pNode, i ) \
for ( i = Vec_PtrSize((pNtk)->vObjs) - 1; (i >= 0) && (((pNode) = Abc_NtkObj(pNtk, i)), 1); i-- ) \
if ( (pNode) == NULL || !Abc_ObjIsNode(pNode) ) {} else

4
src/map/scl/sclLoad.c
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@ -132,7 +132,7 @@ void Abc_SclComputeLoad( SC_Man * p )
pLoad->rise = pLoad->fall = 0.0;
}
// add cell load
Abc_NtkForEachNode( p->pNtk, pObj, i )
Abc_NtkForEachNode1( p->pNtk, pObj, i )
{
SC_Cell * pCell = Abc_SclObjCell( p, pObj );
Abc_ObjForEachFanin( pObj, pFanin, k )
@ -147,7 +147,7 @@ void Abc_SclComputeLoad( SC_Man * p )
vWireCaps = Abc_SclFindWireCaps( p );
if ( vWireCaps )
{
Abc_NtkForEachNode( p->pNtk, pObj, i )
Abc_NtkForEachNode1( p->pNtk, pObj, i )
{
SC_Pair * pLoad = Abc_SclObjLoad( p, pObj );
k = Abc_MinInt( Vec_FltSize(vWireCaps)-1, Abc_ObjFanoutNum(pObj) );

2
src/map/scl/sclMan.h
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@ -181,7 +181,7 @@ static inline float Abc_SclGetTotalArea( SC_Man * p )
double Area = 0;
Abc_Obj_t * pObj;
int i;
Abc_NtkForEachNode( p->pNtk, pObj, i )
Abc_NtkForEachNode1( p->pNtk, pObj, i )
Area += Abc_SclObjCell( p, pObj )->area;
return Area;
}

2
src/map/scl/sclSize.c
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@ -49,7 +49,7 @@ Vec_Int_t * Abc_SclCollectNodes( Abc_Ntk_t * p )
Abc_Obj_t * pObj;
int i;
vRes = Vec_IntAlloc( Abc_NtkNodeNum(p) );
Abc_NtkForEachNode( p, pObj, i )
Abc_NtkForEachNode1( p, pObj, i )
Vec_IntPush( vRes, i );
return vRes;
}

5
src/map/scl/sclTime.c
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@ -108,7 +108,8 @@ void Abc_SclTimeNtkPrint( SC_Man * p, int fShowAll )
{
// printf( "Timing information for all nodes: \n" );
Abc_NtkForEachNodeReverse( p->pNtk, pObj, i )
Abc_SclTimeGatePrint( p, pObj, -1 );
if ( Abc_ObjFaninNum(pObj) > 0 )
Abc_SclTimeGatePrint( p, pObj, -1 );
}
else
{
@ -238,7 +239,7 @@ void Abc_SclTimeNtk( SC_Man * p )
{
Abc_Obj_t * pObj;
int i;
Abc_NtkForEachNode( p->pNtk, pObj, i )
Abc_NtkForEachNode1( p->pNtk, pObj, i )
Abc_SclTimeGate( p, pObj );
Abc_NtkForEachCo( p->pNtk, pObj, i )
Abc_SclObjDupFanin( p, pObj );

4
src/map/scl/sclUtil.c
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@ -198,7 +198,7 @@ Vec_Int_t * Abc_SclManFindGates( SC_Lib * pLib, Abc_Ntk_t * p )
Abc_Obj_t * pObj;
int i;
vVec = Vec_IntStartFull( Abc_NtkObjNumMax(p) );
Abc_NtkForEachNode( p, pObj, i )
Abc_NtkForEachNode1( p, pObj, i )
{
char * pName = Mio_GateReadName((Mio_Gate_t *)pObj->pData);
int gateId = Abc_SclCellFind( pLib, pName );
@ -212,7 +212,7 @@ void Abc_SclManSetGates( SC_Lib * pLib, Abc_Ntk_t * p, Vec_Int_t * vGates )
{
Abc_Obj_t * pObj;
int i;
Abc_NtkForEachNode( p, pObj, i )
Abc_NtkForEachNode1( p, pObj, i )
{
SC_Cell * pCell = SC_LibCell( pLib, Vec_IntEntry(vGates, Abc_ObjId(pObj)) );
assert( pCell->n_inputs == Abc_ObjFaninNum(pObj) );