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Fixing Verilog writer's way of writing module names.

This commit is contained in:
Alan Mishchenko 2012-09-11 18:44:07 -07:00
parent 759b7c0855
commit 784a3579e5
1 changed files with 1 additions and 1 deletions
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2
src/base/io/ioWriteVerilog.c
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@ -116,7 +116,7 @@ void Io_WriteVerilogInt( FILE * pFile, Abc_Ntk_t * pNtk )
{
// write inputs and outputs
// fprintf( pFile, "module %s ( gclk,\n ", Abc_NtkName(pNtk) );
fprintf( pFile, "module %s ( ", Abc_NtkName(pNtk) );
fprintf( pFile, "module %s ( ", Io_WriteVerilogGetName(Abc_NtkName(pNtk)) );
// add the clock signal if it does not exist
if ( Abc_NtkLatchNum(pNtk) > 0 && Nm_ManFindIdByName(pNtk->pManName, "clock", ABC_OBJ_PI) == -1 )
fprintf( pFile, "clock, " );